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Tue, 22 Jan 2019 18:51:57 +0000 From: Honnappa Nagarahalli To: "yskoh@mellanox.com" CC: "thomas@monjalon.net" , "jerinj@marvell.com" , Shahaf Shuler , "Gavin Hu (Arm Technology China)" , "bluca@debian.org" , "dev@dpdk.org" , nd , nd Thread-Topic: [EXT] [PATCH] config: change default cache line size for ARMv8 with meson Thread-Index: AQHUqANwBsxpViT04kqgbgFyIl5wDqWmungAgAAHewCAAAreAIAAFkAAgAAL/oCAAA6ZAIAACYIAgActIwCAABfmsIAC4XTQgAUOO4CABW0UwA== Date: Tue, 22 Jan 2019 18:51:57 +0000 Message-ID: References: <20190109093915.40882-1-yskoh@mellanox.com> <3649611.6SvQ7ZztEu@xps> <6f5a14e478d7c92d1f08a749afac8bb785b3b492.camel@marvell.com> <4346565.rU6Rjy1soH@xps> <04F82086-5151-459B-9026-008BFD89074A@mellanox.com> <20190119070934.GA21963@yongseok-MBP.local> In-Reply-To: <20190119070934.GA21963@yongseok-MBP.local> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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SFP:1101; SCL:1; SRVR:AM6PR08MB3304; H:AM6PR08MB3672.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: h/eMayWpVajurpclslD+V2vehynOcW4VA81L+WcUNORLi5SZMFloVuweX7vClQ1rB7mm+AcqCw6VzUcoqv6qHRK8wwsl6sdNvNw3CA+Uycky6IhN8tOx2W7oluzYzrEgy4VIT2wNrS7l0voIhORsO9I8urdiWCckNgaHmeaNSpQsVGciFFFPGbUUSBQmDqyoHEEv3aYz+JQm6M4YGudNtyvFfBXQQ8vPSjkpJ0A6mLBwWNUZuZ+JEv5yBxG2MWOP9nSwnf4+/r5m1hnfoDILETBNEdbP57EUud3MsDYpe8YqoSNRct7MKYM/hAAuwfdn9Cm3WE5elwHlxfpOvHmwATQO2QK0/s2PafqPcQGduIAy87hYnoILljp5bx884S1QzjPTult7dTmpN04fUQ7wgtEByx132w2VJboZ0eaMw2U= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 06508ac2-bdb1-49ca-b734-08d6809aaf56 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jan 2019 18:51:57.3547 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3304 Subject: Re: [dpdk-dev] [EXT] [PATCH] config: change default cache line size for ARMv8 with meson X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jan 2019 18:51:59 -0000 Removed tspeier@qti.qualcomm.com as the email address is not reachable. > > > > I'll come up with a new patch based on the discussion here. > > > > A few things noted, > > > > - we still want it to be 128B for generic build > > > > - we at least agreed on changing it to 64B for A72 > > > How will this be done? Will you add > > > config/arm/arm64_bluefield_linuxapp_gcc? > > I asked this question as there was a proposal containing 'a72' in the > > file name. IMO, the file name should contain 'bluefield', not on a72. >=20 > Sorry for late reply. It's been buried for some reason. :-) No problem >=20 > Nope, I won't create such a file. That's for cross-compiler AFAIK. > I'm thinking about changing meson.build. Currently, one CL size is applie= d to > all kinds of cores. Consequently, for armv8a, both 'default' and 'a72' ha= ve to > have the same CL size. And one more thing raised from ARM was that > 'crypto' in -march can't be a default. Yes, crypto is optional. So, the distro builds (and any other builds for bi= nary compatibility) should not expect crypto to be present by default. >=20 > > > > - As Qualcomm Centriq CPU has 128B cache line with A72, they should > > > > create a profile in meson.build based on their impl_id. > > > Qualcomm is not A72 core. Can it not use RTE_CACHE_LINE_SIZE from > > > 'flags_generic' in config/arm/meson.build? >=20 > We can add flags_qualcomm for their processor. >=20 > Thanks, > Yongseok