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Mon, 12 Nov 2018 18:34:08 +0000 From: Honnappa Nagarahalli To: Bruce Richardson , "dev@dpdk.org" CC: "stable@dpdk.org" , Yipeng Wang , nd Thread-Topic: [dpdk-dev] [PATCH v2 2/4] hash: add local cache for TSX region Thread-Index: AQHUenUnhTpWWqfANECzeFHeMz/st6VMZdSg Date: Mon, 12 Nov 2018 18:34:08 +0000 Message-ID: References: <20181105173913.61225-1-bruce.richardson@intel.com> <20181112104719.62568-1-bruce.richardson@intel.com> <20181112104719.62568-3-bruce.richardson@intel.com> In-Reply-To: <20181112104719.62568-3-bruce.richardson@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR08MB3656; 6:42hE0fgSb/CSpUQnOOhkTZfdz+9DZGo99L+qvPCquciGcQ9SfcIoZRd65l0IxvQGUdeaulzE7XtoZTC0KpF/u+qsYCJ8+pFgr5OTUab9EJna3JqHtf9FTs4f7Kc6tFDtbQN5s5l4Rnrrm1LgvcWfrdFfbG9jcbdzCjoQwSdNq48V/hMZmCeakb2DPhAgdEDgPcjRXFLcJvCSvFSu5NACY7LfHJRhcirBDFnrnnc446x6P+0BQ3Zd3o7srYf5aLofNu59kTHvtHsmHB7qHH1GoAA5pxvkjbVTTomyfPRfkCUH57AJEcyyMpPOT0VyU786oy1kzBJmmPqIApelH21R2qQStRfxq+TUaS3E5Cc5wRuCbZMHS/TiPVhFu86CGrab243IFZOzffdfY6GDKBqOLtaUM3kr94joIo4CL1G11aemPOsRduQzC0eLmCjZ9cOqdvKHS74hh+gTl+q5NdbR7A==; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 75ba81d2-3490-4d8d-659b-08d648cd6e9e X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Nov 2018 18:34:08.0583 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3656 Subject: Re: [dpdk-dev] [PATCH v2 2/4] hash: add local cache for TSX region X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Nov 2018 18:34:09 -0000 >=20 > From: Yipeng Wang >=20 > This patch adds back the local cache when TSX support is turned on. >=20 > When TSX is turned on, free key-data slot ring would be contended by vari= ous > TSX regions. The purpose of this commit is to reduce possible memory > collisions during key insertion. >=20 > Signed-off-by: Yipeng Wang > Acked-by: Bruce Richardson > --- > lib/librte_hash/rte_cuckoo_hash.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) >=20 > diff --git a/lib/librte_hash/rte_cuckoo_hash.c > b/lib/librte_hash/rte_cuckoo_hash.c > index 76f5dc8..5d5f9f1 100644 > --- a/lib/librte_hash/rte_cuckoo_hash.c > +++ b/lib/librte_hash/rte_cuckoo_hash.c > @@ -180,8 +180,10 @@ struct rte_hash * > } >=20 > /* Check extra flags field to check extra options. */ > - if (params->extra_flag & > RTE_HASH_EXTRA_FLAGS_TRANS_MEM_SUPPORT) > + if (params->extra_flag & > RTE_HASH_EXTRA_FLAGS_TRANS_MEM_SUPPORT) { > + use_local_cache =3D 1; Do you see the issue even in the case of single writer? Enabling this flag = creates local caches on all the data plane cores. This increases the memory= usage for the single writer use case. Then there is 'writers on the contro= l plane' use case, the requirement on hash_add rate is comparatively lower = when compared to 'writers on the data plane'. The writers also are not pinn= ed to any core as well. In this use case, I am not sure how much having a l= ocal cache matters. Enabling this flag effectively changes the free slot allocation from a ring= to a stack data structure. Does it indicate that for single writer use cas= e with TSX, the free slot (global) data structure should be a stack (rather= than a ring)? =20 > hw_trans_mem_support =3D 1; > + } >=20 > if (params->extra_flag & > RTE_HASH_EXTRA_FLAGS_MULTI_WRITER_ADD) { > use_local_cache =3D 1; > -- > 1.8.5.6