From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
To: "jerinj@marvell.com" <jerinj@marvell.com>,
"Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>,
"yskoh@mellanox.com" <yskoh@mellanox.com>
Cc: nd <nd@arm.com>, "russell@mellanox.com" <russell@mellanox.com>,
"mrosenbluth@mellanox.com" <mrosenbluth@mellanox.com>,
"dev@dpdk.org" <dev@dpdk.org>,
Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
nd <nd@arm.com>
Subject: Re: [dpdk-dev] [EXT] Default cacheline size for ARM
Date: Mon, 14 Jan 2019 07:47:43 +0000 [thread overview]
Message-ID: <AM6PR08MB3672D260863B0D2CB361831D98800@AM6PR08MB3672.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <67770ecb60ce7b7742fb44b294a2a5d9864103ce.camel@marvell.com>
> On Sat, 2019-01-05 at 22:47 +0000, Honnappa Nagarahalli wrote:
> > > On Fri, 2019-01-04 at 19:59 +0000, Yongseok Koh wrote:
> > > > ---------------------------------------------------------------
> > > > ----
> > > > ---
> > > > Hi,
> > > >
> > > > The cacheline size (RTE_CACHE_LINE_SIZE) for ARM CPUs is set to be
> > > > 128B by default. Mellanox's BlueField is an ARM CPU having
> > > > Cortex-A72
> > > > and its CL size is 64B.
> > Just wondering how many devices are out there with 128B cache line? I
> > also have not heard about any future devices with 128B cache line. If
> > the majority is 64B, why not keep 64B as the default?
>
> The problem is, In the armv8 spec the cache line size is IMPLEMENTATION
> DEFINED. Marvell's embedded processors has 128B CL and Server processors
> has 64B CL.
>
> Assuming the defconfig_arm64-armv8a-linuxapp-gcc will be used by distro
> folks then that configuration should support all the devices with
> armv8.1 spec. For instance, marvells new chips are armv8.2 but we can not
> make that as default.
What will happen in the future when we will have v9, v10 etc? I think the distro(generic/binary portable) config should get rid of v8.
>
> Target specific configuration can be used for optimized target specific
> configuration.
>
> Or any other ideas for distro config.
>
> >
> > > > I can add config/defconfig_arm64-bluefield-linuxapp-gcc for legacy
> > > > build anyway.
> > > >
> > >
> > > Makes sense.
> > >
> > > > For the meson build, I know it parses the Main ID register to
> > > > figure
> > > > out Implementor ID and Part Number. However, Mellanox doesn't
> > > > program
> > > > our own ID yet but we set the Part Number as 0xd08 (A72).
> > > > According to my folks, ARM's A53, A57, A72, and A73 designs all
> > > > have
> > > > 64B CL. If that's true, can I push a patch to make the change?
> > >
> > > Yes. Broadcom Stingray has the same situation i.e Use
> > > flags_generic,
> > > machine_args_generic
> > >
> > This will solve only the native compilation issue. It will not
> > address distro compilation (may be this is not your goal?).
>
> See above.
>
> >
> > > > Please comment.
> > > >
> > > >
> > > > Thanks,
> > > > Yongseok
> > > >
next prev parent reply other threads:[~2019-01-14 7:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-04 19:59 [dpdk-dev] " Yongseok Koh
2019-01-05 5:14 ` [dpdk-dev] [EXT] " Jerin Jacob Kollanukkaran
2019-01-05 22:47 ` Honnappa Nagarahalli
2019-01-06 7:56 ` Jerin Jacob Kollanukkaran
2019-01-14 7:47 ` Honnappa Nagarahalli [this message]
2019-01-14 8:05 ` Jerin Jacob Kollanukkaran
2019-01-16 1:57 ` Honnappa Nagarahalli
2019-01-18 5:50 ` Honnappa Nagarahalli
2019-01-23 9:05 ` Jerin Jacob Kollanukkaran
2019-01-23 16:28 ` Honnappa Nagarahalli
2019-01-28 12:56 ` Jerin Jacob Kollanukkaran
2019-01-31 18:09 ` Honnappa Nagarahalli
2019-02-01 17:16 ` Jerin Jacob Kollanukkaran
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