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DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2021 06:39:24.8182 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1cb4d38-0202-452c-fc37-08d99202069d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB7256 Subject: Re: [dpdk-dev] [RFC] eal/arm: remove CASP constraints for GCC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: pbhagavatula@marvell.com > Sent: Monday, October 4, 2021 6:03 PM > To: jerinj@marvell.com; Ruifeng Wang > Cc: dev@dpdk.org; Pavan Nikhilesh > Subject: [dpdk-dev] [RFC] eal/arm: remove CASP constraints for GCC >=20 > From: Pavan Nikhilesh >=20 > GCC now assigns even register pairs for CASP, the fix has also been > backported to all stable releases of older GCC versions. > Removing the manual register allocation allows GCC to inline the function= s > and pick optimal registers for performing CASP. >=20 > Signed-off-by: Pavan Nikhilesh > --- > lib/eal/arm/include/rte_atomic_64.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) >=20 > diff --git a/lib/eal/arm/include/rte_atomic_64.h > b/lib/eal/arm/include/rte_atomic_64.h > index fa6f334c0d..f6f31ae777 100644 > --- a/lib/eal/arm/include/rte_atomic_64.h > +++ b/lib/eal/arm/include/rte_atomic_64.h > @@ -52,6 +52,7 @@ rte_atomic_thread_fence(int memorder) > #define __LSE_PREAMBLE "" > #endif >=20 > +#if defined(__clang__) > #define __ATOMIC128_CAS_OP(cas_op_name, op_string) = \ > static __rte_noinline void = \ > cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) > \ > @@ -76,6 +77,19 @@ cas_op_name(rte_int128_t *dst, rte_int128_t *old, > rte_int128_t updated) \ > old->val[0] =3D x0; \ > old->val[1] =3D x1; \ > } > +#else > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) = \ > +static __rte_always_inline void = \ > +cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) > \ > +{ = \ > + asm volatile( \ > + __LSE_PREAMBLE \ Change looks good. One minor comment, gcc doesn't need this PREAMBLE. Thanks, Ruifeng > + op_string " %[old], %H[old], %[upd], %H[upd], [%[dst]]" \ > + : [old] "+r"(old->int128) \ > + : [upd] "r"(updated.int128), [dst] "r"(dst) \ > + : "memory"); \ > +} > +#endif >=20 > __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp") > __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa") > -- > 2.17.1