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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(83380400001)(7696005)(110136005)(316002)(70206006)(70586007)(53546011)(186003)(8676002)(336012)(356005)(26005)(33656002)(6506007)(9686003)(55016002)(54906003)(8936002)(36860700001)(52536014)(47076005)(508600001)(63370400001)(86362001)(2906002)(63350400001)(81166007)(4326008)(5660300002)(82310400003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2021 06:41:04.1414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbc58f1e-6835-4c2f-3868-08d9a0273d4b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6643 Subject: Re: [dpdk-dev] [PATCH v4 14/14] net/mlx5: add shared Rx queue port datapath support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Xueming Li > Sent: Thursday, November 4, 2021 8:33 PM > To: dev@dpdk.org > Cc: Viacheslav Ovsiienko ; xuemingl@nvidia.com; > Lior Margalit ; Matan Azrad ; > David Christensen ; Ruifeng Wang > ; Bruce Richardson > ; Konstantin Ananyev > > Subject: [PATCH v4 14/14] net/mlx5: add shared Rx queue port datapath > support >=20 > From: Viacheslav Ovsiienko >=20 > When receive packet, mlx5 PMD saves mbuf port number from RxQ data. >=20 > To support shared RxQ, save port number into RQ context as user index. > Received packet resolve port number from CQE user index which derived > from RQ context. >=20 > Legacy Verbs API doesn't support RQ user index setting, still read from R= xQ > port number. >=20 > Signed-off-by: Xueming Li > Signed-off-by: Viacheslav Ovsiienko > Acked-by: Slava Ovsiienko > --- > drivers/net/mlx5/mlx5_devx.c | 1 + > drivers/net/mlx5/mlx5_rx.c | 1 + > drivers/net/mlx5/mlx5_rxq.c | 3 ++- > drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 6 ++++++ > drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 12 +++++++++++- > drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 8 +++++++- > 6 files changed, 28 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c > index d3d189ab7f2..a9f9f4af700 100644 > --- a/drivers/net/mlx5/mlx5_devx.c > +++ b/drivers/net/mlx5/mlx5_devx.c > @@ -277,6 +277,7 @@ mlx5_rxq_create_devx_rq_resources(struct > mlx5_rxq_priv *rxq) >=20 > MLX5_WQ_END_PAD_MODE_NONE; > rq_attr.wq_attr.pd =3D cdev->pdn; > rq_attr.counter_set_id =3D priv->counter_set_id; > + rq_attr.user_index =3D rte_cpu_to_be_16(priv->dev_data->port_id); > if (rxq_data->shared) /* Create RMP based RQ. */ > rxq->devx_rq.rmp =3D &rxq_ctrl->obj->devx_rmp; > /* Create RQ using DevX API. */ > diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c inde= x > 1ffa1b95b88..4d85f64accd 100644 > --- a/drivers/net/mlx5/mlx5_rx.c > +++ b/drivers/net/mlx5/mlx5_rx.c > @@ -709,6 +709,7 @@ rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct > rte_mbuf *pkt, { > /* Update packet information. */ > pkt->packet_type =3D rxq_cq_to_pkt_type(rxq, cqe, mcqe); > + pkt->port =3D unlikely(rxq->shared) ? cqe->user_index_low : > +rxq->port_id; >=20 > if (rxq->rss_hash) { > uint32_t rss_hash_res =3D 0; > diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c > index 8feb3e2c0fb..4515d531835 100644 > --- a/drivers/net/mlx5/mlx5_rxq.c > +++ b/drivers/net/mlx5/mlx5_rxq.c > @@ -186,7 +186,8 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl) > mbuf_init->data_off =3D RTE_PKTMBUF_HEADROOM; > rte_mbuf_refcnt_set(mbuf_init, 1); > mbuf_init->nb_segs =3D 1; > - mbuf_init->port =3D rxq->port_id; > + /* For shared queues port is provided in CQE */ > + mbuf_init->port =3D rxq->shared ? 0 : rxq->port_id; > if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF) > mbuf_init->ol_flags =3D RTE_MBUF_F_EXTERNAL; > /* > diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > index 1d00c1c43d1..423e229508c 100644 > --- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h > @@ -1189,6 +1189,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, >=20 > /* D.5 fill in mbuf - rearm_data and packet_type. */ > rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); > + if (unlikely(rxq->shared)) { > + pkts[pos]->port =3D cq[pos].user_index_low; > + pkts[pos + p1]->port =3D cq[pos + p1].user_index_low; > + pkts[pos + p2]->port =3D cq[pos + p2].user_index_low; > + pkts[pos + p3]->port =3D cq[pos + p3].user_index_low; > + } > if (rxq->hw_timestamp) { > int offset =3D rxq->timestamp_offset; > if (rxq->rt_timestamp) { > diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > index aa36df29a09..b1d16baa619 100644 > --- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > @@ -787,7 +787,17 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, > /* C.4 fill in mbuf - rearm_data and packet_type. */ > rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag, > opcode, &elts[pos]); > - if (rxq->hw_timestamp) { > + if (unlikely(rxq->shared)) { > + elts[pos]->port =3D container_of(p0, struct mlx5_cqe, > + pkt_info)->user_index_low; I don't know hardware details on CQE, just comparing with other parts. 1. Is there a need to convert 'user_index_low' with rte_be_to_cpu_16? 2. 'cq' is available as input parameter. Can we directly use cq[pos] instea= d of using container_of(p0), just like what was done on other architectures= ? Thanks. > + elts[pos + 1]->port =3D container_of(p1, struct > mlx5_cqe, > + pkt_info)->user_index_low; > + elts[pos + 2]->port =3D container_of(p2, struct > mlx5_cqe, > + pkt_info)->user_index_low; > + elts[pos + 3]->port =3D container_of(p3, struct > mlx5_cqe, > + pkt_info)->user_index_low; > + } > + if (unlikely(rxq->hw_timestamp)) { > int offset =3D rxq->timestamp_offset; > if (rxq->rt_timestamp) { > struct mlx5_dev_ctx_shared *sh =3D rxq->sh; > diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > index b0fc29d7b9e..f3d838389e2 100644 > --- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h > @@ -736,7 +736,13 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, > *err |=3D _mm_cvtsi128_si64(opcode); > /* D.5 fill in mbuf - rearm_data and packet_type. */ > rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]); > - if (rxq->hw_timestamp) { > + if (unlikely(rxq->shared)) { > + pkts[pos]->port =3D cq[pos].user_index_low; > + pkts[pos + p1]->port =3D cq[pos + p1].user_index_low; > + pkts[pos + p2]->port =3D cq[pos + p2].user_index_low; > + pkts[pos + p3]->port =3D cq[pos + p3].user_index_low; > + } > + if (unlikely(rxq->hw_timestamp)) { > int offset =3D rxq->timestamp_offset; > if (rxq->rt_timestamp) { > struct mlx5_dev_ctx_shared *sh =3D rxq->sh; > -- > 2.33.0