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Jan Viktorin ; Ruifeng > Wang ; Bruce Richardson > > Cc: dev@dpdk.org; Pavan Nikhilesh > Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes >=20 > From: Pavan Nikhilesh >=20 > Mempool elements are by default aligned to CACHELINE_SIZE. > In CN10K cacheline size is 64B but the RoC requires buffers to be aligned= to > 128B. > Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned > 128 bytes. >=20 > Signed-off-by: Pavan Nikhilesh > --- > config/arm/meson.build | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > 213324d262..33afe1a9ad 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -276,7 +276,8 @@ soc_cn10k =3D { > 'implementer' : '0x41', > 'flags': [ > ['RTE_MAX_LCORE', 24], > - ['RTE_MAX_NUMA_NODES', 1] > + ['RTE_MAX_NUMA_NODES', 1], > + ['RTE_MEMPOOL_ALIGN', 128] > ], > 'part_number': '0xd49', > 'extra_march_features': ['crypto'], > -- > 2.17.1 Reviewed-by: Ruifeng Wang