From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36E5CA04B3; Mon, 16 Dec 2019 02:57:13 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CDF6F1BFD5; Mon, 16 Dec 2019 02:57:11 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 5EE9D1BFAD; Mon, 16 Dec 2019 02:57:08 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Dec 2019 17:57:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,320,1571727600"; d="scan'208";a="416285652" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga006.fm.intel.com with ESMTP; 15 Dec 2019 17:57:06 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 15 Dec 2019 17:57:06 -0800 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 15 Dec 2019 17:57:06 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.19]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.71]) with mapi id 14.03.0439.000; Mon, 16 Dec 2019 09:57:03 +0800 From: "Li, Xiaoyun" To: "Gavin Hu (Arm Technology China)" , "Wu, Jingjing" , "Maslekar, Omkar" CC: "dev@dpdk.org" , "stable@dpdk.org" , nd Thread-Topic: [dpdk-dev] [PATCH] raw/ntb: fix write memory barrier issue Thread-Index: AQHVqrafrDFad6NjtU+4AUbpkeX43Ke5SxwAgALHVwA= Date: Mon, 16 Dec 2019 01:57:02 +0000 Message-ID: References: <20191204151916.12607-1-xiaoyun.li@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] raw/ntb: fix write memory barrier issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Didn't notice that. Will fix it in v2. Thanks! > -----Original Message----- > From: Gavin Hu (Arm Technology China) [mailto:Gavin.Hu@arm.com] > Sent: Saturday, December 14, 2019 23:30 > To: Li, Xiaoyun ; Wu, Jingjing > Cc: dev@dpdk.org; stable@dpdk.org; nd > Subject: RE: [dpdk-dev] [PATCH] raw/ntb: fix write memory barrier issue >=20 > Hi Xiaoyun, >=20 > > -----Original Message----- > > From: dev On Behalf Of Xiaoyun Li > > Sent: Wednesday, December 4, 2019 11:19 PM > > To: jingjing.wu@intel.com > > Cc: dev@dpdk.org; Xiaoyun Li ; stable@dpdk.org > > Subject: [dpdk-dev] [PATCH] raw/ntb: fix write memory barrier issue > > > > All buffers and ring info should be written before tail register update= . > > This patch relocates the write memory barrier before updating tail regi= ster > > to avoid potential issues. > > > > Fixes: 11b5c7daf019 ("raw/ntb: add enqueue and dequeue functions") > > Cc: stable@dpdk.org > > > > Signed-off-by: Xiaoyun Li > > --- > > drivers/raw/ntb/ntb.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/raw/ntb/ntb.c b/drivers/raw/ntb/ntb.c > > index ad7f6abfd..dd0b72f8c 100644 > > --- a/drivers/raw/ntb/ntb.c > > +++ b/drivers/raw/ntb/ntb.c > > @@ -683,8 +683,8 @@ ntb_enqueue_bufs(struct rte_rawdev *dev, > > sizeof(struct ntb_used) * nb1); > > rte_memcpy(txq->tx_used_ring, tx_used + nb1, > > sizeof(struct ntb_used) * nb2); > > - *txq->used_cnt =3D txq->last_used; > > rte_wmb(); > > + *txq->used_cnt =3D txq->last_used; > I am ok with the re-location of the barrier, but why not the rte_io_wmb i= nstead > of rte_wmb? > Rte_io_wmb is sufficient to guarantee the preceding stores are visible to= the > device, rte_wmb is overkill. > https://code.dpdk.org/dpdk/latest/source/lib/librte_eal/common/include/ge= ner > ic/rte_atomic.h#L92 > > > > /* update queue stats */ > > hw->ntb_xstats[NTB_TX_BYTES_ID + off] +=3D bytes; > > @@ -789,8 +789,8 @@ ntb_dequeue_bufs(struct rte_rawdev *dev, > > sizeof(struct ntb_desc) * nb1); > > rte_memcpy(rxq->rx_desc_ring, rx_desc + nb1, > > sizeof(struct ntb_desc) * nb2); > > - *rxq->avail_cnt =3D rxq->last_avail; > > rte_wmb(); > > + *rxq->avail_cnt =3D rxq->last_avail; > > > > /* update queue stats */ > > off =3D NTB_XSTATS_NUM * ((size_t)context + 1); > > -- > > 2.17.1