From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id DDE8823C for ; Sun, 6 May 2018 02:52:43 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 May 2018 17:52:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,367,1520924400"; d="scan'208";a="53508069" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga001.jf.intel.com with ESMTP; 05 May 2018 17:52:42 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sat, 5 May 2018 17:52:41 -0700 Received: from cdsmsx102.ccr.corp.intel.com (172.17.3.35) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sat, 5 May 2018 17:52:40 -0700 Received: from cdsmsx104.ccr.corp.intel.com ([169.254.4.183]) by CDSMSX102.ccr.corp.intel.com ([169.254.2.185]) with mapi id 14.03.0319.002; Sun, 6 May 2018 08:52:38 +0800 From: "Zhang, Tianfei" To: Shreyansh Jain , "Xu, Rosen" , "dev@dpdk.org" CC: "Doherty, Declan" , "Richardson, Bruce" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Liu, Song" , "Wu, Hao" , "gaetan.rivet@6wind.com" , "Wu, Yanglong" Thread-Topic: [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver Thread-Index: AQHT47GZ8yCs6dWYTUuyByDOF3NdzKQg+7IAgADhuIA= Date: Sun, 6 May 2018 00:52:38 +0000 Message-ID: References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1525443062-43231-1-git-send-email-rosen.xu@intel.com> <1525443062-43231-4-git-send-email-rosen.xu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODMxOWU0NDItOWE3Yi00N2QxLWJhOTktMjg0YWNhZjBiZjgwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiIrRUMrN1wvNDRLQW5uMjU4QkJ4MGhNalo5ZDRHUG5vNXIxOVlFSFNKQXh0V1h3aEYybU9OWGJWN3BjSFpSYkxIRSJ9 x-ctpclassification: CTP_NT x-originating-ip: [172.17.6.105] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 06 May 2018 00:52:44 -0000 > -----Original Message----- > From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com] > Sent: Sunday, May 6, 2018 3:10 AM > To: Xu, Rosen ; dev@dpdk.org > Cc: Doherty, Declan ; Richardson, Bruce > ; Yigit, Ferruh ; > Ananyev, Konstantin ; Zhang, Tianfei > ; Liu, Song ; Wu, Hao > ; gaetan.rivet@6wind.com; Wu, Yanglong > > Subject: RE: [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver >=20 > Though I had already acked this, I had a quick comment: >=20 > > -----Original Message----- > > From: Xu, Rosen [mailto:rosen.xu@intel.com] > > Sent: Friday, May 4, 2018 7:41 PM > > To: dev@dpdk.org > > Cc: rosen.xu@intel.com; declan.doherty@intel.com; > > bruce.richardson@intel.com; Shreyansh Jain ; > > ferruh.yigit@intel.com; konstantin.ananyev@intel.com; > > tianfei.zhang@intel.com; song.liu@intel.com; hao.wu@intel.com; > > gaetan.rivet@6wind.com; Yanglong Wu > > Subject: [PATCH v7 3/5] iFPGA: Add Intel FPGA BUS Rawdev Driver > > > > From: Rosen Xu > > > > Add Intel FPGA BUS Rawdev Driver which is based on librte_rawdev > > library. > > > > Signed-off-by: Rosen Xu > > Signed-off-by: Yanglong Wu > > Signed-off-by: Figo zhang > > --- >=20 > [...] >=20 > > diff --git a/mk/rte.app.mk b/mk/rte.app.mk index f47bbe8..b0a994f > > 100644 > > --- a/mk/rte.app.mk > > +++ b/mk/rte.app.mk > > @@ -253,6 +253,7 @@ endif # CONFIG_RTE_LIBRTE_EVENTDEV > > > > ifeq ($(CONFIG_RTE_LIBRTE_RAWDEV),y) > > _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SKELETON_RAWDEV) +=3D - > > lrte_pmd_skeleton_rawdev > > +_LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_RAWDEV) +=3D > -lrte_ifpga_rawdev > > endif # CONFIG_RTE_LIBRTE_RAWDEV >=20 > This driver is dependent on CONFIG_RTE_LIBRTE_IFPGA_BUS and if > someone disables that, it would lead to build issues. I think you should > enclose the IFPGA_RAWDEV compilation into conditional for > CONFIG_RTE_LIBRTE_IFPGA_BUS=3Dy. >=20 > Though, I do faintly remember a discussion in past that such thing > should/can be left to individual environment configuration and it can be > safely assumed that such erroneous configuration would be > user-responsibility (at least until a dependency based configuration syst= em is > available in DPDK). So, it is a good-to-have rather a necessity. Good point, we will add RAWDEV condition in our Patch 1: ifeq ($(CONFIG_RTE_LIBRTE_RAWDEV),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) +=3D -lrte_bus_ifpga endif # CONFIG_RTE_LIBRTE_RAWDEV and add IFGA_BUS condition checking in Patch 3, like this: ifeq ($(CONFIG_RTE_LIBRTE_RAWDEV),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_SKELETON_RAWDEV) +=3D -lrte_pmd_skeleton_r= awdevi _LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) +=3D -lrte_bus_ifpga ifeq($(CONFIG_RTE_LIBRTE_IFPGA_BUS),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_RAWDEV) +=3D -lrte_ifpga_rawdev endif# CONFIG_RTE_LIBRTE_IFPGA_BUS endif # CONFIG_RTE_LIBRTE_RAWDEV