From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 3D073160 for ; Sun, 6 May 2018 16:24:42 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 May 2018 07:24:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,370,1520924400"; d="scan'208";a="48680031" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga003.jf.intel.com with ESMTP; 06 May 2018 07:24:39 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 6 May 2018 07:24:39 -0700 Received: from cdsmsx102.ccr.corp.intel.com (172.17.3.35) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 6 May 2018 07:24:38 -0700 Received: from cdsmsx104.ccr.corp.intel.com ([169.254.4.183]) by CDSMSX102.ccr.corp.intel.com ([169.254.2.185]) with mapi id 14.03.0319.002; Sun, 6 May 2018 22:24:36 +0800 From: "Zhang, Tianfei" To: Shreyansh Jain , "Xu, Rosen" , "dev@dpdk.org" , "thomas@monjalon.net" CC: "Doherty, Declan" , "Richardson, Bruce" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Liu, Song" , "Wu, Hao" , "gaetan.rivet@6wind.com" Thread-Topic: [PATCH v8 5/5] iFPGA: add document for iFPGA driver Thread-Index: AQHT5RXWzIiVMVdGkUCZjgSXamHNtaQiEaOAgACviLA= Date: Sun, 6 May 2018 14:24:35 +0000 Message-ID: References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1525596044-84881-1-git-send-email-rosen.xu@intel.com> <1525596044-84881-6-git-send-email-rosen.xu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTc2Mzc0YTMtOTNjZC00MWQzLWExN2YtZDNlMzFjZDIzMTYyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJyR3Zub0FDZkVQWllacm9YRkpSR043aTdrMFwvRVVyY1duV0ZZNWJUbHNkZ05UNVczcGtcL1ZZRVFYRFJUTEJtdE0ifQ== x-ctpclassification: CTP_NT x-originating-ip: [172.17.6.105] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v8 5/5] iFPGA: add document for iFPGA driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 06 May 2018 14:24:43 -0000 > -----Original Message----- > From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com] > Sent: Sunday, May 6, 2018 7:54 PM > To: Xu, Rosen ; dev@dpdk.org; > thomas@monjalon.net > Cc: Doherty, Declan ; Richardson, Bruce > ; Yigit, Ferruh ; > Ananyev, Konstantin ; Zhang, Tianfei > ; Liu, Song ; Wu, Hao > ; gaetan.rivet@6wind.com > Subject: RE: [PATCH v8 5/5] iFPGA: add document for iFPGA driver >=20 > Hi Rosen, >=20 > > -----Original Message----- > > From: Xu, Rosen [mailto:rosen.xu@intel.com] > > Sent: Sunday, May 6, 2018 2:11 PM > > To: dev@dpdk.org > > Cc: rosen.xu@intel.com; declan.doherty@intel.com; > > bruce.richardson@intel.com; Shreyansh Jain ; > > ferruh.yigit@intel.com; konstantin.ananyev@intel.com; > > tianfei.zhang@intel.com; song.liu@intel.com; hao.wu@intel.com; > > gaetan.rivet@6wind.com > > Subject: [PATCH v8 5/5] iFPGA: add document for iFPGA driver > > > > From: Figo Zhang > > > > add some introduction, motivation and usage for iFPGA driver. > > > > Signed-off-by: Rosen Xu > > Signed-off-by: Figo Zhang > > --- > > doc/guides/rawdevs/ifpga_rawdev.rst | 112 > > +++++++++++++++++++++++++++++++++ > > doc/guides/rel_notes/release_18_05.rst | 13 ++++ > > 2 files changed, 125 insertions(+) > > create mode 100644 doc/guides/rawdevs/ifpga_rawdev.rst > > > > diff --git a/doc/guides/rawdevs/ifpga_rawdev.rst > > b/doc/guides/rawdevs/ifpga_rawdev.rst > > new file mode 100644 > > index 0000000..37ae4cc > > --- /dev/null > > +++ b/doc/guides/rawdevs/ifpga_rawdev.rst > > @@ -0,0 +1,112 @@ > > +.. SPDX-License-Identifier: BSD-3-Clause > > + Copyright(c) 2018 Intel Corporation. > > + > > +IFPGA Rawdev Driver > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > + > > +FPGA is used more and more widely in Cloud and NFV, one primary > > +reason > > is > > +that FPGA not only provides ASIC performance but also it's more > > flexible > > +than ASIC. > > + > > +FPGA uses Partial Reconfigure (PR) Parts of Bit Stream to achieve its > > +flexibility. That means one FPGA Device Bit Stream is divided into > > many Parts > > +of Bit Stream(each Part of Bit Stream is defined as AFU-Accelerated > > Function > > +Unit), and each AFU is a hardware acceleration unit which can be > > dynamically > > +reloaded respectively. > > + > > +By PR (Partial Reconfiguration) AFUs, one FPGA resources can be time- > > shared by > > +different users. FPGA hot upgrade and fault tolerance can be provided > > easily. > > + > > +The SW IFPGA Rawdev Driver (**ifpga_rawdev**) provides a Rawdev > > +driver that utilizes Intel FPGA Software Stack OPAE(Open Programmable > > Acceleration > > +Engine) for FPGA management. > > + > > +Implementation details > > +---------------------- > > + > > +Each instance of IFPGA Rawdev Driver is probed by Intel FpgaDev. In > > coordination > > +with OPAE share code IFPGA Rawdev Driver provides common FPGA > > management ops > > +for FPGA operation, OPAE provides all following operations: > > +- FPGA PR (Partial Reconfiguration) management > > +- FPGA AFUs Identifying > > +- FPGA Thermal Management > > +- FPGA Power Management > > +- FPGA Performance reporting > > +- FPGA Remote Debug > > + > > +All configuration parameters are taken by vdev_ifpga_cfg driver. > > Besides > > +configuration, vdev_ifpga_cfg driver also hot plugs in IFPGA Bus. > > + > > +All of the AFUs of one FPGA may share same PCI BDF and AFUs scan > > depend on > > +IFPGA Rawdev Driver so IFPGA Bus takes AFU device scan and AFU > > +drivers > > probe. > > +All AFU device driver bind to AFU device by its UUID (Universally > > Unique > > +Identifier). > > + > > +To avoid unnecessary code duplication and ensure maximum > performance, > > +handling of AFU devices is left to different PMDs; all the design as > > +summarized by the following block diagram:: > > + > > + +---------------------------------------------------------------+ > > + | Application(s) > | > > + +----------------------------.----------------------------------+ > > + | > > + | > > + +----------------------------'----------------------------------+ > > + | DPDK Framework (APIs) > | > > + +----------|------------|--------.---------------------|--------+ > > + / \ > | > > + / \ > | > > + +-------'-------+ +-------'-------+ +--------'--------+ > > + | Eth PMD | | Crypto PMD | | > | > > + +-------.-------+ +-------.-------+ | | > > + | | | > | > > + | | | > | > > + +-------'-------+ +-------'-------+ | IFPGA | > > + | Eth AFU Dev | |Crypto AFU Dev | | Rawdev > Driver | > > + +-------.-------+ +-------.-------+ |(OPAE Share Code)| > > + | | | > | > > + | | Rawdev | > | > > + +-------'------------------'-------+ Ops | | > > + | IFPGA Bus | -------->| > | > > + +-----------------.----------------+ +--------.--------+ > > + | > | > > + Hot-plugin -->| | > > + | > | > > + +-----------------'------------------+ +--------'--------+ > > + | vdev_ifpga_cfg driver | | Intel > FpgaDev | > > + +------------------------------------+ +-----------------+ > > + > > +Build options > > +------------- > > + > > +- ``CONFIG_RTE_LIBRTE_IFPGA_BUS`` (default ``y``) > > + > > + Toggle compilation of IFPGA Bus library. > > + > > +- ``CONFIG_RTE_LIBRTE_IFPGA_RAWDEV`` (default ``y``) > > + > > + Toggle compilation of the ``ifpga_rawdev`` driver. > > + > > +Run-time parameters > > +------------------- > > + > > +This driver is invoked automatically in systems added with Intel > > +FPGA, but PR and IFPGA Bus scan is trigged by command line using > > +``--vdev 'net_ifpga_cfg`` EAL option. > > + > > +The following device parameters are supported: > > + > > +- ``ifpga`` [string] > > + > > + Provide a specific Intel FPGA device PCI BDF. Can be provided > > multiple > > + times for additional instances. > > + > > +- ``port`` [int] > > + > > + Each FPGA can provide many channels to PR AFU by software, each > > channels > > + is identified by this parameter. > > + > > +- ``afu_bts`` [string] > > + > > + If null, the AFU Bit Stream has been PR in FPGA, if not forces PR > > and > > + identifies AFU Bit Stream file. >=20 > [...] >=20 > If you don't introduce this file into doc/guides/rawdevs/index.rst (like = your > v7), the doc index won't be generated. > I think you misunderstood my comment in [1] - I meant that you will have = to > rebase over CMDIF because it has already introduced the > doc/guides/rawdevs/index.rst file. Your patch v7 was adding this file. It > would have conflicted for Thomas' eventual merge. >=20 > [1] http://dpdk.org/ml/archives/dev/2018-May/100313.html >=20 > Unfortunately, you might have to send a v9 or maybe Thomas can take care > of this while merging. Hi Shreyansh, Do you mean we donot need this patch on V9.=20 Reset this patch when the CMDIF patches have merged into mainline, right?