From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23F14A0613 for ; Wed, 25 Sep 2019 02:58:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B9B962BF2; Wed, 25 Sep 2019 02:58:24 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 686E82BEA for ; Wed, 25 Sep 2019 02:58:22 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Sep 2019 17:58:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,546,1559545200"; d="scan'208";a="183094084" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga008.jf.intel.com with ESMTP; 24 Sep 2019 17:58:21 -0700 Received: from fmsmsx121.amr.corp.intel.com (10.18.125.36) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 24 Sep 2019 17:58:20 -0700 Received: from cdsmsx152.ccr.corp.intel.com (172.17.4.41) by fmsmsx121.amr.corp.intel.com (10.18.125.36) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 24 Sep 2019 17:58:20 -0700 Received: from cdsmsx104.ccr.corp.intel.com ([169.254.4.171]) by CDSMSX152.ccr.corp.intel.com ([169.254.6.180]) with mapi id 14.03.0439.000; Wed, 25 Sep 2019 08:58:17 +0800 From: "Zhang, Tianfei" To: "Ye, Xiaolong" , "Pei, Andy" CC: "dev@dpdk.org" , "Xu, Rosen" , "Zhang, Qi Z" , "Lomartire, David" , "Yigit, Ferruh" Thread-Topic: [PATCH v6 02/17] raw/ifpga/base: add irq support Thread-Index: AQHVbssSMzAZsBKWIk6JnAD8+mQJuKc6fzMAgAEbLnA= Date: Wed, 25 Sep 2019 00:58:17 +0000 Message-ID: References: <1568881185-89233-2-git-send-email-andy.pei@intel.com> <1568883774-92149-1-git-send-email-andy.pei@intel.com> <1568883774-92149-3-git-send-email-andy.pei@intel.com> <20190924160222.GC67866@intel.com> In-Reply-To: <20190924160222.GC67866@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.17.6.105] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v6 02/17] raw/ifpga/base: add irq support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Ye, Xiaolong > Sent: Wednesday, September 25, 2019 12:02 AM > To: Pei, Andy > Cc: dev@dpdk.org; Xu, Rosen ; Zhang, Tianfei > ; Zhang, Qi Z ; Lomartire, > David ; Yigit, Ferruh > Subject: Re: [PATCH v6 02/17] raw/ifpga/base: add irq support >=20 > On 09/19, Andy Pei wrote: > >From: Tianfei zhang > > > >Add irq support for ifpga FME globle error, port error and uint unit. >=20 > s/globle/global Thanks, will fix in next version. >=20 > >We implmented this feature by vfio interrupt mechanism. > > > >Signed-off-by: Tianfei zhang > >Signed-off-by: Andy Pei > >--- > > drivers/raw/ifpga/base/ifpga_feature_dev.c | 60 > ++++++++++++++++++++++++++++++ > > drivers/raw/ifpga/base/ifpga_fme_error.c | 22 +++++++++++ > > drivers/raw/ifpga/base/ifpga_port.c | 20 ++++++++++ > > drivers/raw/ifpga/base/ifpga_port_error.c | 21 +++++++++++ > > 4 files changed, 123 insertions(+) > > > >diff --git a/drivers/raw/ifpga/base/ifpga_feature_dev.c > >b/drivers/raw/ifpga/base/ifpga_feature_dev.c > >index 63c8bcc..f0fb242 100644 > >--- a/drivers/raw/ifpga/base/ifpga_feature_dev.c > >+++ b/drivers/raw/ifpga/base/ifpga_feature_dev.c > >@@ -3,6 +3,7 @@ > > */ > > > > #include > >+#include > > > > #include "ifpga_feature_dev.h" > > > >@@ -331,3 +332,62 @@ int port_hw_init(struct ifpga_port_hw *port) > > port_hw_uinit(port); > > return ret; > > } > >+ > >+/* > >+ * FIXME: we should get msix vec count during pci enumeration instead > >+of > >+ * below hardcode value. > >+ */ > >+#define FPGA_MSIX_VEC_COUNT 20 >=20 > So what is preventing us from getting msix vec count from pci enumeration= ? >=20 > >+/* irq set buffer length for interrupt */ #define MSIX_IRQ_SET_BUF_LEN > >+(sizeof(struct vfio_irq_set) + \ > >+ sizeof(int) * FPGA_MSIX_VEC_COUNT) > >+ > >+/* only support msix for now*/ > >+static int vfio_msix_enable_block(s32 vfio_dev_fd, unsigned int vec_sta= rt, > >+ unsigned int count, s32 *fds) >=20 > DPDK convention is put the function return type in a separate line. >=20 > >+{ > >+ char irq_set_buf[MSIX_IRQ_SET_BUF_LEN]; > >+ struct vfio_irq_set *irq_set; > >+ int len, ret; > >+ int *fd_ptr; > >+ > >+ len =3D sizeof(irq_set_buf); > >+ > >+ irq_set =3D (struct vfio_irq_set *)irq_set_buf; > >+ irq_set->argsz =3D len; > >+ irq_set->count =3D count; > >+ irq_set->flags =3D VFIO_IRQ_SET_DATA_EVENTFD | > >+ VFIO_IRQ_SET_ACTION_TRIGGER; > >+ irq_set->index =3D VFIO_PCI_MSIX_IRQ_INDEX; > >+ irq_set->start =3D vec_start; > >+ > >+ fd_ptr =3D (int *)&irq_set->data; > >+ opae_memcpy(fd_ptr, fds, sizeof(int) * count); > >+ > >+ ret =3D ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set); > >+ if (ret) > >+ printf("Error enabling MSI-X interrupts\n"); > >+ > >+ return ret; > >+} > >+ > >+int fpga_msix_set_block(struct ifpga_feature *feature, unsigned int sta= rt, > >+ unsigned int count, s32 *fds) >=20 > Ditto. >=20 > >+{ > >+ struct feature_irq_ctx *ctx =3D feature->ctx; > >+ unsigned int i; > >+ int ret; > >+ > >+ if (start >=3D feature->ctx_num || start + count > feature->ctx_num) > >+ return -EINVAL; > >+ > >+ /* assume that each feature has continuous vector space in msix*/ > >+ ret =3D vfio_msix_enable_block(feature->vfio_dev_fd, > >+ ctx[start].idx, count, fds); > >+ if (!ret) { > >+ for (i =3D 0; i < count; i++) > >+ ctx[i].eventfd =3D fds[i]; > >+ } > >+ > >+ return ret; > >+} > >diff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c > >b/drivers/raw/ifpga/base/ifpga_fme_error.c > >index 3794564..068f52c 100644 > >--- a/drivers/raw/ifpga/base/ifpga_fme_error.c > >+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c > >@@ -373,9 +373,31 @@ static int fme_global_error_set_prop(struct > ifpga_feature *feature, > > return -ENOENT; > > } > > > >+static int fme_global_err_set_irq(struct ifpga_feature *feature, void > >+*irq_set) >=20 > Ditto. >=20 > >+{ > >+ struct fpga_fme_err_irq_set *err_irq_set =3D > >+ (struct fpga_fme_err_irq_set *)irq_set; >=20 > Cast is not needed for void *. Will fix in next version. >=20 > >+ struct ifpga_fme_hw *fme; > >+ int ret; > >+ > >+ fme =3D (struct ifpga_fme_hw *)feature->parent; >=20 > Ditto. >=20 > >+ > >+ spinlock_lock(&fme->lock); > >+ if (!(fme->capability & FPGA_FME_CAP_ERR_IRQ)) { > >+ spinlock_unlock(&fme->lock); > >+ return -ENODEV; > >+ } > >+ > >+ ret =3D fpga_msix_set_block(feature, 0, 1, &err_irq_set->evtfd); > >+ spinlock_unlock(&fme->lock); > >+ > >+ return ret; > >+} > >+ > > struct ifpga_feature_ops fme_global_err_ops =3D { > > .init =3D fme_global_error_init, > > .uinit =3D fme_global_error_uinit, > > .get_prop =3D fme_global_error_get_prop, > > .set_prop =3D fme_global_error_set_prop, > >+ .set_irq =3D fme_global_err_set_irq, > > }; > >diff --git a/drivers/raw/ifpga/base/ifpga_port.c > >b/drivers/raw/ifpga/base/ifpga_port.c > >index 6c41164..56b04a6 100644 > >--- a/drivers/raw/ifpga/base/ifpga_port.c > >+++ b/drivers/raw/ifpga/base/ifpga_port.c > >@@ -384,9 +384,29 @@ static void port_uint_uinit(struct ifpga_feature > *feature) > > dev_info(NULL, "PORT UINT UInit.\n"); } > > > >+static int port_uint_set_irq(struct ifpga_feature *feature, void > >+*irq_set) >=20 > Ditto. >=20 > >+{ > >+ struct fpga_uafu_irq_set *uafu_irq_set =3D irq_set; > >+ struct ifpga_port_hw *port =3D feature->parent; > >+ int ret; > >+ > >+ spinlock_lock(&port->lock); > >+ if (!(port->capability & FPGA_PORT_CAP_UAFU_IRQ)) { > >+ spinlock_unlock(&port->lock); > >+ return -ENODEV; > >+ } > >+ > >+ ret =3D fpga_msix_set_block(feature, uafu_irq_set->start, > >+ uafu_irq_set->count, uafu_irq_set->evtfds); > >+ spinlock_unlock(&port->lock); > >+ > >+ return ret; > >+} > >+ > > struct ifpga_feature_ops ifpga_rawdev_port_uint_ops =3D { > > .init =3D port_uint_init, > > .uinit =3D port_uint_uinit, > >+ .set_irq =3D port_uint_set_irq, > > }; > > > > static int port_afu_init(struct ifpga_feature *feature) diff --git > >a/drivers/raw/ifpga/base/ifpga_port_error.c > >b/drivers/raw/ifpga/base/ifpga_port_error.c > >index 138284e..8aef7d7 100644 > >--- a/drivers/raw/ifpga/base/ifpga_port_error.c > >+++ b/drivers/raw/ifpga/base/ifpga_port_error.c > >@@ -136,9 +136,30 @@ static int port_error_set_prop(struct ifpga_feature > *feature, > > return -ENOENT; > > } > > > >+static int port_error_set_irq(struct ifpga_feature *feature, void > >+*irq_set) >=20 > Ditto. >=20 > >+{ > >+ struct fpga_port_err_irq_set *err_irq_set =3D irq_set; > >+ struct ifpga_port_hw *port; > >+ int ret; > >+ > >+ port =3D feature->parent; > >+ > >+ spinlock_lock(&port->lock); > >+ if (!(port->capability & FPGA_PORT_CAP_ERR_IRQ)) { > >+ spinlock_unlock(&port->lock); > >+ return -ENODEV; > >+ } > >+ > >+ ret =3D fpga_msix_set_block(feature, 0, 1, &err_irq_set->evtfd); > >+ spinlock_unlock(&port->lock); > >+ > >+ return ret; > >+} > >+ >=20 > Above 3 new functions have a lot of similarity, better to extract out com= mon > function to reduce duplication. Good suggestion, will fix in next version. >=20 > Thanks, > Xiaolong >=20 > > struct ifpga_feature_ops ifpga_rawdev_port_error_ops =3D { > > .init =3D port_error_init, > > .uinit =3D port_error_uinit, > > .get_prop =3D port_error_get_prop, > > .set_prop =3D port_error_set_prop, > >+ .set_irq =3D port_error_set_irq, > > }; > >-- > >1.8.3.1 > >