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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL0PR11MB3043.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3f6f2113-abe0-4228-5681-08d96c6884f6 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Aug 2021 10:17:21.1981 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lOx9cgJGr+bWAKOtQKR3qm3oUB9j2w2hm6jtBKt/eHmhyVD3hmH5RMYX3L+4oHyCH6Z1cd2NwvsJ5TJxp3s7jA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4077 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 05/10] ipsec: add support for AEAD algorithms X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Radu, > -----Original Message----- > From: dev On Behalf Of Radu Nicolau > Sent: Friday, August 13, 2021 10:30 AM > To: Ananyev, Konstantin ; Iremonger, > Bernard ; Medvedkin, Vladimir > > Cc: dev@dpdk.org; mdr@ashroe.eu; Richardson, Bruce > ; hemant.agrawal@nxp.com; > gakhil@marvell.com; anoobj@marvell.com; Doherty, Declan > ; Sinha, Abhijit ; > Buckley, Daniel M ; marchana@marvell.com; > ktejasree@marvell.com; matan@nvidia.com; Nicolau, Radu > > Subject: [dpdk-dev] [PATCH v3 05/10] ipsec: add support for AEAD algorith= ms >=20 > Add support for AES_CCM, CHACHA20_POLY1305 and AES_GMAC. >=20 > Signed-off-by: Declan Doherty > Signed-off-by: Radu Nicolau > Signed-off-by: Abhijit Sinha > Signed-off-by: Daniel Martin Buckley > --- > + > +/* > + * RFC 4106, 5 AAD Construction > + * spi and sqn should already be converted into network byte order. [Fan: Comments is incorrect, should be RFC7643]=20 > + * Make sure that not used bytes are zeroed. > + */ > +static inline void > +aead_chacha20_poly1305_aad_fill(struct aead_chacha20_poly1305_aad > *aad, > + rte_be32_t spi, rte_be64_t sqn, > + int esn) > +{ > + aad->spi =3D spi; > + if (esn) > + aad->sqn.u64 =3D sqn; > + else { > + aad->sqn.u32[0] =3D sqn_low32(sqn); > + aad->sqn.u32[1] =3D 0; > + } > + aad->align0 =3D 0; > +} > + > /*