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From: "Yang, Qiming" <qiming.yang@intel.com>
To: "Xu, Ting" <ting.xu@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "Zhang, Qi Z" <qi.z.zhang@intel.com>,
	"Wu, Jingjing" <jingjing.wu@intel.com>,
	"Xing, Beilei" <beilei.xing@intel.com>,
	"Kovacevic, Marko" <marko.kovacevic@intel.com>,
	"Mcnamara, John" <john.mcnamara@intel.com>,
	"Ye, Xiaolong" <xiaolong.ye@intel.com>
Subject: Re: [dpdk-dev] [PATCH v3 02/12] net/ice: complete device info get in DCF
Date: Thu, 18 Jun 2020 06:44:51 +0000	[thread overview]
Message-ID: <BN6PR11MB00177423FE662948B28F9958E59B0@BN6PR11MB0017.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20200616124112.108014-3-ting.xu@intel.com>



> -----Original Message-----
> From: Xu, Ting <ting.xu@intel.com>
> Sent: Tuesday, June 16, 2020 20:41
> To: dev@dpdk.org
> Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Yang, Qiming
> <qiming.yang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>; Xing, Beilei
> <beilei.xing@intel.com>; Kovacevic, Marko <marko.kovacevic@intel.com>;
> Mcnamara, John <john.mcnamara@intel.com>; Ye, Xiaolong
> <xiaolong.ye@intel.com>
> Subject: [PATCH v3 02/12] net/ice: complete device info get in DCF
> 
> From: Qi Zhang <qi.z.zhang@intel.com>
> 
> Add support to get complete device information for DCF, including Rx/Tx
> offload capabilities and default configuration.
> 
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> Signed-off-by: Ting Xu <ting.xu@intel.com>
> ---
>  drivers/net/ice/ice_dcf_ethdev.c | 72
> ++++++++++++++++++++++++++++++--
>  1 file changed, 69 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/ice/ice_dcf_ethdev.c
> b/drivers/net/ice/ice_dcf_ethdev.c
> index e5ba1a61f..7f24ef81a 100644
> --- a/drivers/net/ice/ice_dcf_ethdev.c
> +++ b/drivers/net/ice/ice_dcf_ethdev.c
> @@ -24,6 +24,7 @@
> 
>  #include "ice_generic_flow.h"
>  #include "ice_dcf_ethdev.h"
> +#include "ice_rxtx.h"
> 
>  static uint16_t
>  ice_dcf_recv_pkts(__rte_unused void *rx_queue, @@ -66,11 +67,76 @@
> ice_dcf_dev_info_get(struct rte_eth_dev *dev,
>  		     struct rte_eth_dev_info *dev_info)  {
>  	struct ice_dcf_adapter *adapter = dev->data->dev_private;
> +	struct ice_dcf_hw *hw = &adapter->real_hw;
> 
>  	dev_info->max_mac_addrs = 1;
> -	dev_info->max_rx_pktlen = (uint32_t)-1;
> -	dev_info->max_rx_queues = RTE_DIM(adapter->rxqs);
> -	dev_info->max_tx_queues = RTE_DIM(adapter->txqs);
> +	dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs;
> +	dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs;
> +	dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
> +	dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
> +	dev_info->hash_key_size = hw->vf_res->rss_key_size;
> +	dev_info->reta_size = hw->vf_res->rss_lut_size;
> +	dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
> +
> +	dev_info->rx_offload_capa =
> +		DEV_RX_OFFLOAD_VLAN_STRIP |
> +		DEV_RX_OFFLOAD_QINQ_STRIP |

Do we support QINQ in DCF now?

> +		DEV_RX_OFFLOAD_IPV4_CKSUM |
> +		DEV_RX_OFFLOAD_UDP_CKSUM |
> +		DEV_RX_OFFLOAD_TCP_CKSUM |
> +		DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
> +		DEV_RX_OFFLOAD_SCATTER |
> +		DEV_RX_OFFLOAD_JUMBO_FRAME |
> +		DEV_RX_OFFLOAD_VLAN_FILTER |
> +		DEV_RX_OFFLOAD_RSS_HASH;
> +	dev_info->tx_offload_capa =
> +		DEV_TX_OFFLOAD_VLAN_INSERT |
> +		DEV_TX_OFFLOAD_QINQ_INSERT |

Same as above

> +		DEV_TX_OFFLOAD_IPV4_CKSUM |
> +		DEV_TX_OFFLOAD_UDP_CKSUM |
> +		DEV_TX_OFFLOAD_TCP_CKSUM |
> +		DEV_TX_OFFLOAD_SCTP_CKSUM |
> +		DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
> +		DEV_TX_OFFLOAD_TCP_TSO |
> +		DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
> +		DEV_TX_OFFLOAD_GRE_TNL_TSO |
> +		DEV_TX_OFFLOAD_IPIP_TNL_TSO |
> +		DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
> +		DEV_TX_OFFLOAD_MULTI_SEGS;
> +
> +	dev_info->default_rxconf = (struct rte_eth_rxconf) {
> +		.rx_thresh = {
> +			.pthresh = ICE_DEFAULT_RX_PTHRESH,
> +			.hthresh = ICE_DEFAULT_RX_HTHRESH,
> +			.wthresh = ICE_DEFAULT_RX_WTHRESH,
> +		},
> +		.rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
> +		.rx_drop_en = 0,
> +		.offloads = 0,
> +	};
> +
> +	dev_info->default_txconf = (struct rte_eth_txconf) {
> +		.tx_thresh = {
> +			.pthresh = ICE_DEFAULT_TX_PTHRESH,
> +			.hthresh = ICE_DEFAULT_TX_HTHRESH,
> +			.wthresh = ICE_DEFAULT_TX_WTHRESH,
> +		},
> +		.tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
> +		.tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
> +		.offloads = 0,
> +	};
> +
> +	dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
> +		.nb_max = ICE_MAX_RING_DESC,
> +		.nb_min = ICE_MIN_RING_DESC,
> +		.nb_align = ICE_ALIGN_RING_DESC,
> +	};
> +
> +	dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
> +		.nb_max = ICE_MAX_RING_DESC,
> +		.nb_min = ICE_MIN_RING_DESC,
> +		.nb_align = ICE_ALIGN_RING_DESC,
> +	};
> 
>  	return 0;
>  }
> --
> 2.17.1


  reply	other threads:[~2020-06-18  6:45 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-16 12:41 [dpdk-dev] [PATCH v3 00/12] enable DCF datapath configuration Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 01/12] net/ice: init RSS and supported RXDID in DCF Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 02/12] net/ice: complete device info get " Ting Xu
2020-06-18  6:44   ` Yang, Qiming [this message]
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 03/12] net/ice: complete dev configure " Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 04/12] net/ice: complete queue setup " Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 05/12] net/ice: add stop flag for device start / stop Ting Xu
2020-06-18  6:48   ` Yang, Qiming
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 06/12] net/ice: add Rx queue init in DCF Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 07/12] net/ice: init RSS during DCF start Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 08/12] net/ice: add queue config in DCF Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 09/12] net/ice: add queue start and stop for DCF Ting Xu
2020-06-18  6:39   ` Yang, Qiming
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 10/12] net/ice: enable stats " Ting Xu
2020-06-18  6:31   ` Yang, Qiming
2020-06-19  2:44     ` Xu, Ting
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 11/12] net/ice: set MAC filter during dev start " Ting Xu
2020-06-16 12:41 ` [dpdk-dev] [PATCH v3 12/12] doc: enable DCF datapath configuration Ting Xu

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