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Mon, 10 Aug 2020 04:50:10 +0000 From: "Hyong Youb Kim (hyonkim)" To: Ciara Power , "dev@dpdk.org" CC: "bruce.richardson@intel.com" , "John Daley (johndale)" Thread-Topic: [PATCH 20.11 06/12] net/enic: add checks for max SIMD bitwidth Thread-Index: AQHWbNTKBCChtr3KREesNW0VQML7YKkwyTug Date: Mon, 10 Aug 2020 04:50:10 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200807155859.63888-7-ciara.power@intel.com> In-Reply-To: <20200807155859.63888-7-ciara.power@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=cisco.com; x-originating-ip: [123.111.163.40] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4b4d0204-fd9a-4feb-e3dd-08d83ce8dcb6 x-ms-traffictypediagnostic: BN6PR11MB1841: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3826; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN7PR11MB2738.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4b4d0204-fd9a-4feb-e3dd-08d83ce8dcb6 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Aug 2020 04:50:10.3179 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 5ae1af62-9505-4097-a69a-c1553ef7840e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +PqNyIDx4+nkm/QnQ9mLcqjLvXDGepDuobbaa4Swwk0kj7W/QKui4ruesurOtpMHs8O2EUj80C8AORXb1y7P8A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1841 X-OriginatorOrg: cisco.com X-Outbound-SMTP-Client: 173.37.102.13, xch-rcd-003.cisco.com X-Outbound-Node: alln-core-10.cisco.com Subject: Re: [dpdk-dev] [PATCH 20.11 06/12] net/enic: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Ciara Power > Sent: Saturday, August 8, 2020 12:59 AM > To: dev@dpdk.org > Cc: bruce.richardson@intel.com; Ciara Power ; > John Daley (johndale) ; Hyong Youb Kim (hyonkim) > > Subject: [PATCH 20.11 06/12] net/enic: add checks for max SIMD bitwidth >=20 > When choosing a vector path to take, an extra condition must be > satisfied to ensure the max SIMD bitwidth allows for the CPU enabled > path. >=20 > Cc: John Daley > Cc: Hyong Youb Kim >=20 > Signed-off-by: Ciara Power > --- > drivers/net/enic/enic_rxtx_vec_avx2.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/enic/enic_rxtx_vec_avx2.c > b/drivers/net/enic/enic_rxtx_vec_avx2.c > index 676b9f5fdb..5db43bdbb8 100644 > --- a/drivers/net/enic/enic_rxtx_vec_avx2.c > +++ b/drivers/net/enic/enic_rxtx_vec_avx2.c > @@ -821,7 +821,8 @@ enic_use_vector_rx_handler(struct rte_eth_dev > *eth_dev) > fconf =3D ð_dev->data->dev_conf.fdir_conf; > if (fconf->mode !=3D RTE_FDIR_MODE_NONE) > return false; > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) { > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && > + rte_get_max_simd_bitwidth() >=3D > RTE_MAX_256_SIMD) { > ENICPMD_LOG(DEBUG, " use the non-scatter avx2 Rx > handler"); > eth_dev->rx_pkt_burst =3D &enic_noscatter_vec_recv_pkts; > enic->use_noscatter_vec_rx_handler =3D 1; > -- > 2.17.1 Acked-by: Hyong Youb Kim Thanks.. -Hyong