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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN7PR12MB2707.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3b8e91c6-ace1-4af5-3edf-08d8552a0091 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Sep 2020 01:36:55.7612 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: W7Tz40q5VZk973Gmyq24mWz+nXV6amm3xOiP5xBuK4p8sEHWhmExrxgOSfBc5bwEB0ZgDxrNQufEHXhWk7dfrA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1779 X-OriginatorOrg: Nvidia.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1599701775; bh=onaLQAC7iWFqax0At9pMuAzH6esOanM63cNMHpKfY80=; h=X-PGP-Universal:ARC-Seal:ARC-Message-Signature: ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic: Thread-Index:Date:Message-ID:References:In-Reply-To: Accept-Language:Content-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-ms-traffictypediagnostic:x-ld-processed: x-microsoft-antispam-prvs:x-ms-exchange-transport-forked: x-ms-oob-tlc-oobclassifiers:x-ms-exchange-senderadcheck: x-microsoft-antispam:x-microsoft-antispam-message-info: x-forefront-antispam-report:x-ms-exchange-antispam-messagedata: Content-Type:Content-Transfer-Encoding:MIME-Version: X-MS-Exchange-CrossTenant-AuthAs: X-MS-Exchange-CrossTenant-AuthSource: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-CrossTenant-userprincipalname: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg; b=lQQDrfKHOMWCja8hu1BXjzPZfFWPtMTRo0iAE2b4aGExecglOdwGGlp+GtYjxSlBA mT2HrasBZ9bfp6jKmDrw9kib7jf+cvbZRQ2kCmaBMJ2BTQcB8oUcjfY+4YSbn5dREv 17REq+6vQWbOpKxLqZktT2a3MQ5nKqk2kBlUtuLE1opTv2b7HGLjOZZDRLsrGVyq9n 0SVp3FpC0V/JBhhp5cdvP2yBLjrUfBtA/sc8zqBlFepffq1epeeFXAJMzlqBV213jl TjXDwamYJ1V/oTKXlbaxubNTOQ9/SYfjqxBbhIZqnJ0NWmPLZmYZlCNBdsORt1YSSR 3bqsWO2zwYCCQ== Subject: Re: [dpdk-dev] [PATCH v4] net/mlx5: relaxed ordering for multi-packet RQ buffer refcnt X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > >=20 > > > > Use c11 atomics with RELAXED ordering instead of the rte_atomic ops > > which enforce unnecessary barriers on aarch64. > > > > Signed-off-by: Phil Yang > Looks good. >=20 > Reviewed-by: Honnappa Nagarahalli Acked-by: Alexander Kozyrev >=20 > > --- > > v4: > > Remove the unnecessary ACQUIRE barrier in rx burst path. (Honnappa) > > > > v3: > > Split from the patchset: > > https://nam11.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fpatc= h > > > work.dpdk.org%2Fcover%2F68159%2F&data=3D02%7C01%7Cakozyrev%40nv > idia. > > > com%7Cf16ba4e8cfb145f5d82008d85529348e%7C43083d15727340c1b7db39ef > d9ccc > > > 17a%7C0%7C0%7C637352982762038088&sdata=3D0HzTxbzh0Dqk0hZ5PIgEV > zieyV% > > 2BnLTivsVIFFxXFAtI%3D&reserved=3D0 > > > > drivers/net/mlx5/mlx5_rxq.c | 2 +- > > drivers/net/mlx5/mlx5_rxtx.c | 16 +++++++++------- > > drivers/net/mlx5/mlx5_rxtx.h | 2 +- > > 3 files changed, 11 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c > > index > > 79eb8f8..40e0239 100644 > > --- a/drivers/net/mlx5/mlx5_rxq.c > > +++ b/drivers/net/mlx5/mlx5_rxq.c > > @@ -2012,7 +2012,7 @@ mlx5_mprq_buf_init(struct rte_mempool *mp, void > > *opaque_arg, > > > > memset(_m, 0, sizeof(*buf)); > > buf->mp =3D mp; > > - rte_atomic16_set(&buf->refcnt, 1); > > + __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED); > > for (j =3D 0; j !=3D strd_n; ++j) { > > shinfo =3D &buf->shinfos[j]; > > shinfo->free_cb =3D mlx5_mprq_buf_free_cb; diff --git > > a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c index > > 1b71e94..549477b 100644 > > --- a/drivers/net/mlx5/mlx5_rxtx.c > > +++ b/drivers/net/mlx5/mlx5_rxtx.c > > @@ -1626,10 +1626,11 @@ mlx5_mprq_buf_free_cb(void *addr > __rte_unused, > > void *opaque) { > > struct mlx5_mprq_buf *buf =3D opaque; > > > > - if (rte_atomic16_read(&buf->refcnt) =3D=3D 1) { > > + if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) =3D=3D 1) { > > rte_mempool_put(buf->mp, buf); > > - } else if (rte_atomic16_add_return(&buf->refcnt, -1) =3D=3D 0) { > > - rte_atomic16_set(&buf->refcnt, 1); > > + } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1, > > + __ATOMIC_RELAXED) =3D=3D 0)) { > > + __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED); > > rte_mempool_put(buf->mp, buf); > > } > > } > > @@ -1709,7 +1710,8 @@ mlx5_rx_burst_mprq(void *dpdk_rxq, struct > > rte_mbuf **pkts, uint16_t pkts_n) > > > > if (consumed_strd =3D=3D strd_n) { > > /* Replace WQE only if the buffer is still in use. */ > > - if (rte_atomic16_read(&buf->refcnt) > 1) { > > + if (__atomic_load_n(&buf->refcnt, > > + __ATOMIC_RELAXED) > 1) { > > mprq_buf_replace(rxq, rq_ci & wq_mask, > strd_n); > > /* Release the old buffer. */ > > mlx5_mprq_buf_free(buf); > > @@ -1821,9 +1823,9 @@ mlx5_rx_burst_mprq(void *dpdk_rxq, struct > > rte_mbuf **pkts, uint16_t pkts_n) > > void *buf_addr; > > > > /* Increment the refcnt of the whole chunk. */ > > - rte_atomic16_add_return(&buf->refcnt, 1); > > - MLX5_ASSERT((uint16_t)rte_atomic16_read(&buf- > > >refcnt) <=3D > > - strd_n + 1); > > + __atomic_add_fetch(&buf->refcnt, 1, > > __ATOMIC_RELAXED); > > + MLX5_ASSERT(__atomic_load_n(&buf->refcnt, > > + __ATOMIC_RELAXED) <=3D strd_n + 1); > > buf_addr =3D RTE_PTR_SUB(addr, > > RTE_PKTMBUF_HEADROOM); > > /* > > * MLX5 device doesn't use iova but it is necessary in a > diff > > --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h > > index c02a007..467f31d 100644 > > --- a/drivers/net/mlx5/mlx5_rxtx.h > > +++ b/drivers/net/mlx5/mlx5_rxtx.h > > @@ -68,7 +68,7 @@ struct rxq_zip { > > /* Multi-Packet RQ buffer header. */ > > struct mlx5_mprq_buf { > > struct rte_mempool *mp; > > - rte_atomic16_t refcnt; /* Atomically accessed refcnt. */ > > + uint16_t refcnt; /* Atomically accessed refcnt. */ > > uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first > packet. > > */ > > struct rte_mbuf_ext_shared_info shinfos[]; > > /* > > -- > > 2.7.4