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Wed, 7 Oct 2020 05:01:39 +0000 Received: from BN8PR11MB3795.namprd11.prod.outlook.com ([fe80::e4a8:91ab:e032:b8ae]) by BN8PR11MB3795.namprd11.prod.outlook.com ([fe80::e4a8:91ab:e032:b8ae%5]) with mapi id 15.20.3455.021; Wed, 7 Oct 2020 05:01:39 +0000 From: "Wang, Xiao W" To: "Power, Ciara" , "dev@dpdk.org" CC: "Zhang, Qi Z" Thread-Topic: [PATCH v2 08/17] net/fm10k: add checks for max SIMD bitwidth Thread-Index: AQHWfI17WYayJN2i6EqbUoErgVA7lqmL1JTQ Date: Wed, 7 Oct 2020 05:01:39 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200827161304.32300-1-ciara.power@intel.com> <20200827161304.32300-9-ciara.power@intel.com> In-Reply-To: <20200827161304.32300-9-ciara.power@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: OUwR5Vh8EjT1fVmYBWA6IZwO1kn1xpL3645IV6tcCn80WpFlir3xrxd+ddZNp+u9HkAP73rUQOSRTNO3jirTb/ZQnZ5IKsyBcmMc51SbO3E/c0EwwCRh4lnSZlo1LjW0RTOm4dFVvMQAHgfmA9XM/GLqOmadrmspV+6XvubZ7W3VXBkM8BrJGCFTotEUWg3l+uF1xvFkc+HW8e+vD7s4seM4caGp0rWXqJTCBbWnMzf3TonquQqacPQotAHaiI8H/ZzzIBqaMnptLRPz6UeSJK2vFUDFML0007xTSAfiX1HXjY92VQnSoogkUDyLFlcrLojR8cOaXKPTtMmR2ib4iF/KF8DryzT0+sMDWaX4+MGW93bUrCa1TCUR0gkF2BnR3nd7KJUqLP/x9RvNYTK1ItucouhMbNBmh0SWKgDHl9khCTcosn9AVJFflee4DHTuhsusLpvbpJfAlybQzNQBghSwVcz2V5Lv2hR9fJ4fiXNp07dMxp9koIR/XewTLCrVTM15igoPqP9ZZQFTivJERtgXp8HLgAmmsvrFPAioA2c+IuFeDPS2yoby+jx30XTzM4GcQ+hzlAh+qfqbCwp3wV5qG3Q8BnNmNPvezKUNSbTUd0GK6ggVIE9Je8bFZqVhH1uTtM89Wz37WaVEs1bkIQ== Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN8PR11MB3795.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 29d43ec3-a769-4fc2-57fd-08d86a7e1366 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Oct 2020 05:01:39.4774 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ndwTPtehZ7Q5qqAbv2CykvbtSa9VETDc8I0HhwpWN//QKcaFeeWUBL3NieOCNW+RI1t0kfvBxL309C1aGeSaRA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB3971 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 08/17] net/fm10k: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Ciara, BRs, Xiao > -----Original Message----- > From: Power, Ciara > Sent: Friday, August 28, 2020 12:13 AM > To: dev@dpdk.org > Cc: Power, Ciara ; Zhang, Qi Z > ; Wang, Xiao W > Subject: [PATCH v2 08/17] net/fm10k: add checks for max SIMD bitwidth >=20 > When choosing a vector path to take, an extra condition must be > satisfied to ensure the max SIMD bitwidth allows for the CPU enabled > path. >=20 > Cc: Qi Zhang > Cc: Xiao Wang >=20 > Signed-off-by: Ciara Power > --- > drivers/net/fm10k/fm10k_ethdev.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/net/fm10k/fm10k_ethdev.c > b/drivers/net/fm10k/fm10k_ethdev.c > index b574693bca..f7c41d4377 100644 > --- a/drivers/net/fm10k/fm10k_ethdev.c > +++ b/drivers/net/fm10k/fm10k_ethdev.c > @@ -2937,7 +2937,9 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) > if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) { > /* primary process has set the ftag flag and offloads */ > txq =3D dev->data->tx_queues[0]; > - if (fm10k_tx_vec_condition_check(txq)) { > + if (fm10k_tx_vec_condition_check(txq) || > + rte_get_max_simd_bitwidth() > + < RTE_MAX_128_SIMD) { > dev->tx_pkt_burst =3D fm10k_xmit_pkts; > dev->tx_pkt_prepare =3D fm10k_prep_pkts; > PMD_INIT_LOG(DEBUG, "Use regular Tx func"); > @@ -2956,7 +2958,8 @@ fm10k_set_tx_function(struct rte_eth_dev *dev) > txq =3D dev->data->tx_queues[i]; > txq->tx_ftag_en =3D tx_ftag_en; > /* Check if Vector Tx is satisfied */ > - if (fm10k_tx_vec_condition_check(txq)) > + if (fm10k_tx_vec_condition_check(txq) || > + rte_get_max_simd_bitwidth() < > RTE_MAX_128_SIMD) > use_sse =3D 0; > } >=20 > @@ -2990,7 +2993,9 @@ fm10k_set_rx_function(struct rte_eth_dev *dev) > * conditions to be met. > */ > if (!fm10k_rx_vec_condition_check(dev) && > - dev_info->rx_vec_allowed && !rx_ftag_en) { > + dev_info->rx_vec_allowed && !rx_ftag_en && > + rte_get_max_simd_bitwidth() > + >=3D RTE_MAX_128_SIMD) { > if (dev->data->scattered_rx) > dev->rx_pkt_burst =3D fm10k_recv_scattered_pkts_vec; > else > -- > 2.17.1 Acked-by: Xiao Wang Thanks~