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From: "Wang, Haiyue" <haiyue.wang@intel.com>
To: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>, "Power, Ciara"
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CC: "Zhao1, Wei" <wei.zhao1@intel.com>, "Guo, Jia" <jia.guo@intel.com>
Thread-Topic: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth
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Subject: Re: [dpdk-dev] [PATCH v3 11/18] net/ixgbe: add checks for max SIMD
	bitwidth
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> -----Original Message-----
> From: Ananyev, Konstantin <konstantin.ananyev@intel.com>
> Sent: Monday, October 12, 2020 17:09
> To: Wang, Haiyue <haiyue.wang@intel.com>; Power, Ciara <ciara.power@intel=
.com>; dev@dpdk.org
> Cc: Zhao1, Wei <wei.zhao1@intel.com>; Guo, Jia <jia.guo@intel.com>
> Subject: RE: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth
>=20
> > > > > From: Power, Ciara <ciara.power@intel.com>
> > > > > Sent: Wednesday, September 30, 2020 21:04
> > > > > To: dev@dpdk.org
> > > > > Cc: Power, Ciara <ciara.power@intel.com>; Zhao1, Wei <wei.zhao1@i=
ntel.com>; Guo, Jia
> > > > > <jia.guo@intel.com>; Wang, Haiyue <haiyue.wang@intel.com>
> > > > > Subject: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitw=
idth
> > > > >
> > > > > When choosing a vector path to take, an extra condition must be
> > > > > satisfied to ensure the max SIMD bitwidth allows for the CPU enab=
led
> > > > > path.
> > > > >
> > > > > Cc: Wei Zhao <wei.zhao1@intel.com>
> > > > > Cc: Jeff Guo <jia.guo@intel.com>
> > > > >
> > > > > Signed-off-by: Ciara Power <ciara.power@intel.com>
> > > > > ---
> > > > >  drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++--
> > > > >  1 file changed, 5 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/i=
xgbe_rxtx.c
> > > > > index 977ecf5137..eadc7183f2 100644
> > > > > --- a/drivers/net/ixgbe/ixgbe_rxtx.c
> > > > > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c
> > > > > @@ -2503,7 +2503,9 @@ ixgbe_set_tx_function(struct rte_eth_dev *d=
ev, struct ixgbe_tx_queue
> *txq)
> > > > >  		dev->tx_pkt_prepare =3D NULL;
> > > > >  		if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
> > > > >  				(rte_eal_process_type() !=3D RTE_PROC_PRIMARY ||
> > > > > -					ixgbe_txq_vec_setup(txq) =3D=3D 0)) {
> > > > > +					ixgbe_txq_vec_setup(txq) =3D=3D 0) &&
> > > > > +				rte_get_max_simd_bitwidth()
> > > >
> > > > As Konstantin mentioned: " I think it is a bit safer to do all chec=
ks first before
> > > >  doing txq_vec_setup()."
> > > >
> > > > Fox x86 & arm platforms, the setup is always 0, since 'sw_ring_v' i=
s union with
> > > > 'sw_ring' which is initialize at 'ixgbe_dev_tx_queue_setup'.
> > > >
> > > > 	union {
> > > > 		struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scala=
r PMD. */
> > > > 		struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for v=
ector PMD */
> > > > 	};
> > > >
> > > > static inline int
> > > > ixgbe_txq_vec_setup_default(struct ixgbe_tx_queue *txq,
> > > > 			    const struct ixgbe_txq_ops *txq_ops)
> > > > {
> > > > 	if (txq->sw_ring_v =3D=3D NULL)
> > > > 		return -1;
> > > >
> > > > 	/* leave the first one for overflow */
> > > > 	txq->sw_ring_v =3D txq->sw_ring_v + 1;
> > > > 	txq->ops =3D txq_ops;
> > > >
> > > > 	return 0;
> > > > }
> > > >
> > > > So we need check the SIMD bitwidth firstly to avoid changing the sw=
_ring* pointer address.
> > > >
> > > >
> > > > Also, looks like we need to add check on:
> > > >
> > > > int
> > > > ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt)
> > > > {
> > > > 	struct ixgbe_tx_queue *txq =3D (struct ixgbe_tx_queue *)tx_queue;
> > > > 	if (txq->offloads =3D=3D 0 &&
> > > > #ifdef RTE_LIBRTE_SECURITY
> > > > 			!(txq->using_ipsec) &&
> > > > #endif
> > > > 			txq->tx_rs_thresh >=3D RTE_PMD_IXGBE_TX_MAX_BURST) {
> > > > 		if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
> > > >                                                      <-------------=
------ Add the same check
> > > > 				(rte_eal_process_type() !=3D RTE_PROC_PRIMARY ||
> > > > 					txq->sw_ring_v !=3D NULL)) {
> > > > 			return ixgbe_tx_done_cleanup_vec(txq, free_cnt);
> > >
> > > Could you probably explain a bit more why it is needed?
> >
> > To align with the vector selection path:
> >
> > 		if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
> > 				(rte_eal_process_type() !=3D RTE_PROC_PRIMARY ||
> > 					ixgbe_txq_vec_setup(txq) =3D=3D 0))
>=20
>=20
> Ok, so to make sure that TX is running in vector mode?

That's right, since no variable to save the vector mode selection,
then the check condition should be the same.

> If so, then doesn't txq->sw_ring_v !=3D NULL was intended to do so?
> BTW, is it a valid check? Considering that sw_ring and sw_ring_v
> is a union?

Yes, sw_ring_v should always be !NULL ;-)

>=20
> >
> >
> > >
> > > > 		} else {
> > > > 			return ixgbe_tx_done_cleanup_simple(txq, free_cnt);
> > > > 		}
> >
> >
> > > > > 2.17.1