From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35BB0A04B6; Mon, 12 Oct 2020 18:04:47 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0F0F41D90E; Mon, 12 Oct 2020 18:04:46 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 19DED1D8FE for ; Mon, 12 Oct 2020 18:04:42 +0200 (CEST) IronPort-SDR: 27JJarvXIz330SI1vA1tJceBssyVh7scoQb1VwH6/TCtOSU7dnwheK1NGFzlJqvVZhghtc6kH2 g6rmSdPlHzQA== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165874568" X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="165874568" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2020 09:04:38 -0700 IronPort-SDR: BQQd3ENMPjhGelDqK0fjpwFL7V6BvGL+yQLvJgS4ZH/bOrFFYhbEZWKqlyYXj0fAcLxZ3DTPUD 85dWJtwFfcoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="345899360" Received: from orsmsx605.amr.corp.intel.com ([10.22.229.18]) by orsmga008.jf.intel.com with ESMTP; 12 Oct 2020 09:04:37 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX605.amr.corp.intel.com (10.22.229.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 12 Oct 2020 09:04:37 -0700 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 12 Oct 2020 09:04:37 -0700 Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Mon, 12 Oct 2020 09:04:37 -0700 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (104.47.74.42) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Mon, 12 Oct 2020 09:04:34 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gv9ptcphohc0+OCEpJkwcipkAs0SDVXAWSBMNiqGzHKBydPMAxrURNXlOdicl9j20ysqRN7ljGvUVv6LPcI2ZmUP0KT5uw9RoxBvlXixjX8FnV+RmtcgXkq95hSiXV21nOEz1YySn2yAUWtwx+7j5VVl9k5KFVu9YJAEKucUigfMsKHcG7qRlvwjW5ZpfIfuU7Sy/6RUc9hl7w0kFBKi9V9wHIrREIJK6xEqrHsGqjaxx9FTCOsQFwILc+kt7A4CkIxJJMC8OX08T4H/r+/VtkVRUXDle6AAYiiBzPWSYo/zSFlQYi6KXSqy0qBxAOdE5j/vrhBIr3oMW7GwM9xEuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MtQV5t75BU01qW7Rr8Gl+CRmow/8LnaqxSkvZA0m9KQ=; b=LHdjUO1wTxkMD2W4YVZ6wvgowElbFxLew5Wp9eAVpirmNtDuWjn/mlI66ixJZRv+yx3l5tQikuko46ud2WMUSUJ47o8rDbxEAQpc3YeDB2dIS9FIPd5ox+94UIn/o7ilqCjH6Goljl2z9KhT6XDxO9Gb6XPXYH95bvrUrZ7LefeKblMLDfB74hLDvoa4NxYpAEioP/JiEz5kZmplf2iCyGmVUnW5joBUTfATDrEM5MYjmvBcz6wGq0w4ZLN9dAzU/aur0wuO+Hb93e5Nw32ppJVAwJFBiO6I5jbu6GTGyhfukd9AlVdEAeSYA2PFL0czYkzxbJkOKZ02ybld+Q+V6g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MtQV5t75BU01qW7Rr8Gl+CRmow/8LnaqxSkvZA0m9KQ=; b=Bs2DrmfzT1blud/i1gEorGYEOP1+CxZKn34U0YefIsJ3ING6jKr2Py8V3UIrtxnFCxCnlpqiS3WssYxhVKE2ZkdPGQvH1I+pn2snCenURcej8RuIgRxNc4qfdftVsbCmo9Ayw/UklJRfX9m2bACwnkPk9wgdC8ThDikwimIp7rc= Received: from BN8PR11MB3795.namprd11.prod.outlook.com (2603:10b6:408:82::31) by BN6PR11MB0033.namprd11.prod.outlook.com (2603:10b6:405:63::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.28; Mon, 12 Oct 2020 16:04:29 +0000 Received: from BN8PR11MB3795.namprd11.prod.outlook.com ([fe80::e4a8:91ab:e032:b8ae]) by BN8PR11MB3795.namprd11.prod.outlook.com ([fe80::e4a8:91ab:e032:b8ae%5]) with mapi id 15.20.3455.029; Mon, 12 Oct 2020 16:04:29 +0000 From: "Wang, Haiyue" To: "Ananyev, Konstantin" , "Power, Ciara" , "dev@dpdk.org" CC: "Zhao1, Wei" , "Guo, Jia" Thread-Topic: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth Thread-Index: AQHWlyrQ+9L43nHRjUSWL5f7XEr8jqmQ3VfggAIw0oCAADFtkIAAgNoAgAByjuA= Date: Mon, 12 Oct 2020 16:04:29 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-12-ciara.power@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.211] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1e2d8f8e-e8d5-4365-d5f0-08d86ec8801e x-ms-traffictypediagnostic: BN6PR11MB0033: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: jxuLIGsHH9dCmO7DRWksVs9CPMya3ts0ikA/oePybvBhAvrdE3SpS31HlQlXRIH1NyxugQ3nsFsMOyoH0gPjJC4uEr7gCzqRNV5vvdJj8cc8VVxoWtwwbHq78QWwCM+ERgx2m1LUBVwbY5qP2tAS7UbirUg8xqihIa+m3wBxqAdpTYf5o0+sIESCZ3ggfqU+G75k9RMyAexupP0SG0NdIzgeKNmvVUH2gn0V4Bya0cSy6KOxZvHcK2MR5+TJelynhSjoFfeL+GYCWCAXjYO0BT3BO1kkRt/Ce6EIZ1ZMdPdRENWE8J/YfikHmDH8kMXoth0ZFEBcDiRU+RhUseE56Q== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN8PR11MB3795.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(346002)(376002)(136003)(396003)(366004)(39860400002)(33656002)(55016002)(110136005)(7696005)(8676002)(83380400001)(316002)(54906003)(8936002)(52536014)(86362001)(66476007)(478600001)(66446008)(5660300002)(66946007)(186003)(26005)(71200400001)(76116006)(66556008)(9686003)(64756008)(4326008)(6506007)(53546011)(2906002)(107886003); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: J+MOiRAkRzi2QtNtNhnw/gsT52IVRZVWBmhx+HCKsmxLzmLHJyjyTlx2AkAHRqo2CO+rO9lps9IfAmsPqCFhg1Hk7+XsO65d7AtTMZAyK8bWXUVvZCgzLBd2dFoRRwRGDGmSmfOuYGFF1FCZW4Uqj7U72OSlflkvvZuKuU0wpyNeW2bMffM6T2x7hpCKKcajMyeuF/GEhWlh6Ur8xa4VTFpbwSU/76MOSb4oTpJhEmxxsEz33NQpadLMz0swF9A97CptyU5bvc+2ab3F6FNp/ltqPQtjXVNMTHhB2BFTtI8U2ujJJMvD09bj1gujzznTgp6wNObcxnHkwQi4Cf33M3hkyQBXDKRAivxm3w4iREkIam15iI+cTkbqXZcHRW5M/CEI5xv6DcxGj2PMSTygpoY0Kz5KHl8D8j+Ru+E2U7nAscdk4HX866GlGP9/cujlNxHlQDzVPioL5oQNAXbbFe0wZxNSec6AhLB8TPjkMVD2My6S83p1C5v5Fmz2oLgjlo5Lh1/biF75DBeg3vACwnVXfsDBhw3AE2Rjw+5F1Wl7LGC3XBMuUPYOVORKjjAKGKjqS/Bwet/YMY+d7EyHovoj66KQHTYIvwo8R4jeiiohQWbNY3EuMgrNAo1JKsw1rY+l7Ir4paIh2Ca+RAjjhQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN8PR11MB3795.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e2d8f8e-e8d5-4365-d5f0-08d86ec8801e X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2020 16:04:29.2445 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mwK7WBTTawX1NwMqd543QJEoK8uNg325kJtYpPxAiNeKwVtfFqES/zkTJ16VUwthsoRKyH70QnNSGGXTfAFLWw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB0033 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: > -----Original Message----- > From: Ananyev, Konstantin > Sent: Monday, October 12, 2020 17:09 > To: Wang, Haiyue ; Power, Ciara ; dev@dpdk.org > Cc: Zhao1, Wei ; Guo, Jia > Subject: RE: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth >=20 > > > > > From: Power, Ciara > > > > > Sent: Wednesday, September 30, 2020 21:04 > > > > > To: dev@dpdk.org > > > > > Cc: Power, Ciara ; Zhao1, Wei ; Guo, Jia > > > > > ; Wang, Haiyue > > > > > Subject: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitw= idth > > > > > > > > > > When choosing a vector path to take, an extra condition must be > > > > > satisfied to ensure the max SIMD bitwidth allows for the CPU enab= led > > > > > path. > > > > > > > > > > Cc: Wei Zhao > > > > > Cc: Jeff Guo > > > > > > > > > > Signed-off-by: Ciara Power > > > > > --- > > > > > drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++-- > > > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/i= xgbe_rxtx.c > > > > > index 977ecf5137..eadc7183f2 100644 > > > > > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > > > > > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > > > > > @@ -2503,7 +2503,9 @@ ixgbe_set_tx_function(struct rte_eth_dev *d= ev, struct ixgbe_tx_queue > *txq) > > > > > dev->tx_pkt_prepare =3D NULL; > > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > > > - ixgbe_txq_vec_setup(txq) =3D=3D 0)) { > > > > > + ixgbe_txq_vec_setup(txq) =3D=3D 0) && > > > > > + rte_get_max_simd_bitwidth() > > > > > > > > As Konstantin mentioned: " I think it is a bit safer to do all chec= ks first before > > > > doing txq_vec_setup()." > > > > > > > > Fox x86 & arm platforms, the setup is always 0, since 'sw_ring_v' i= s union with > > > > 'sw_ring' which is initialize at 'ixgbe_dev_tx_queue_setup'. > > > > > > > > union { > > > > struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scala= r PMD. */ > > > > struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for v= ector PMD */ > > > > }; > > > > > > > > static inline int > > > > ixgbe_txq_vec_setup_default(struct ixgbe_tx_queue *txq, > > > > const struct ixgbe_txq_ops *txq_ops) > > > > { > > > > if (txq->sw_ring_v =3D=3D NULL) > > > > return -1; > > > > > > > > /* leave the first one for overflow */ > > > > txq->sw_ring_v =3D txq->sw_ring_v + 1; > > > > txq->ops =3D txq_ops; > > > > > > > > return 0; > > > > } > > > > > > > > So we need check the SIMD bitwidth firstly to avoid changing the sw= _ring* pointer address. > > > > > > > > > > > > Also, looks like we need to add check on: > > > > > > > > int > > > > ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) > > > > { > > > > struct ixgbe_tx_queue *txq =3D (struct ixgbe_tx_queue *)tx_queue; > > > > if (txq->offloads =3D=3D 0 && > > > > #ifdef RTE_LIBRTE_SECURITY > > > > !(txq->using_ipsec) && > > > > #endif > > > > txq->tx_rs_thresh >=3D RTE_PMD_IXGBE_TX_MAX_BURST) { > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > > <-------------= ------ Add the same check > > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > > txq->sw_ring_v !=3D NULL)) { > > > > return ixgbe_tx_done_cleanup_vec(txq, free_cnt); > > > > > > Could you probably explain a bit more why it is needed? > > > > To align with the vector selection path: > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > ixgbe_txq_vec_setup(txq) =3D=3D 0)) >=20 >=20 > Ok, so to make sure that TX is running in vector mode? That's right, since no variable to save the vector mode selection, then the check condition should be the same. > If so, then doesn't txq->sw_ring_v !=3D NULL was intended to do so? > BTW, is it a valid check? Considering that sw_ring and sw_ring_v > is a union? Yes, sw_ring_v should always be !NULL ;-) >=20 > > > > > > > > > > > } else { > > > > return ixgbe_tx_done_cleanup_simple(txq, free_cnt); > > > > } > > > > > > > > > 2.17.1