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Mon, 12 Oct 2020 08:09:38 +0000 From: "Wang, Haiyue" To: "Burakov, Anatoly" , "dev@dpdk.org" CC: "Ma, Liang J" , "Guo, Jia" , "Hunt, David" , "Ananyev, Konstantin" , "jerinjacobk@gmail.com" , "Richardson, Bruce" , "thomas@monjalon.net" , "McDaniel, Timothy" , "Eads, Gage" , "Macnamara, Chris" Thread-Topic: [PATCH v5 06/10] net/ixgbe: implement power management API Thread-Index: AQHWnlXYcFvgO3qBbkShoOmKIm/VC6mTnuqA Date: Mon, 12 Oct 2020 08:09:38 +0000 Message-ID: References: <1601647919-25312-1-git-send-email-liang.j.ma@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.102.204.37] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bf0ab37c-0656-4c48-0455-08d86e862a50 x-ms-traffictypediagnostic: BN6PR11MB1841: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5236; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN8PR11MB3795.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf0ab37c-0656-4c48-0455-08d86e862a50 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2020 08:09:38.6925 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: x5AGWV5Vfr/7YSaQITL8PSDh3hKSURVziC6Zy7gjsTSFuN+3PrL+0w58HuNJwnpoDFFQq4SrG/k9jzfELRWWCQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1841 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v5 06/10] net/ixgbe: implement power management API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Liang, > -----Original Message----- > From: Burakov, Anatoly > Sent: Saturday, October 10, 2020 00:02 > To: dev@dpdk.org > Cc: Ma, Liang J ; Guo, Jia ; Wan= g, Haiyue > ; Hunt, David ; Ananyev, Kon= stantin > ; jerinjacobk@gmail.com; Richardson, Bruce = ; > thomas@monjalon.net; McDaniel, Timothy ; Eads= , Gage ; > Macnamara, Chris > Subject: [PATCH v5 06/10] net/ixgbe: implement power management API >=20 > From: Liang Ma >=20 > Implement support for the power management API by implementing a > `get_wake_addr` function that will return an address of an RX ring's > status bit. >=20 > Signed-off-by: Anatoly Burakov > Signed-off-by: Liang Ma > --- > drivers/net/ixgbe/ixgbe_ethdev.c | 1 + > drivers/net/ixgbe/ixgbe_rxtx.c | 22 ++++++++++++++++++++++ > drivers/net/ixgbe/ixgbe_rxtx.h | 2 ++ > 3 files changed, 25 insertions(+) >=20 >=20 > +int ixgbe_get_wake_addr(void *rx_queue, volatile void **tail_desc_addr, > + uint64_t *expected, uint64_t *mask) > +{ > + volatile union ixgbe_adv_rx_desc *rxdp; > + struct ixgbe_rx_queue *rxq =3D rx_queue; > + uint16_t desc; > + > + desc =3D rxq->rx_tail; > + rxdp =3D &rxq->rx_ring[desc]; > + /* watch for changes in status bit */ > + *tail_desc_addr =3D &rxdp->wb.upper.status_error; > + > + /* > + * we expect the DD bit to be set to 1 if this descriptor was already > + * written to. > + */ > + *expected =3D rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD); > + *mask =3D rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD); > + Seems have one issue about the byte endian: Like for BIG endian: *expected =3D rte_bswap32(IXGBE_RXDADV_STAT_DD) !=3D *expected =3D rte_bswap64(IXGBE_RXDADV_STAT_DD) And in API 'rte_power_monitor', use uint64_t type to access the wake up data: static inline void rte_power_monitor(const volatile void *p, const uint64_t expected_value, const uint64_t value_mask, const uint64_t tsc_timestamp) { if (value_mask) { const uint64_t cur_value =3D *(const volatile uint64_t *)p; const uint64_t masked =3D cur_value & value_mask; /* if the masked value is already matching, abort */ if (masked =3D=3D expected_value) return; } So that we need the wake up address type like 16/32/64b ? > -- > 2.17.1