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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: gZEQCbuLaHGklUKbg2pwfW2pmnBC5mlVSAKnyYOFJyYT1uzq3WTSWpr6jU3QKp9iM865LCXVEy5Pnvvod7H2dX/hDa/07CvTu9UnzvBQKlCigGihdQR7t6/kXON6B5atZrGYG5AWwOwJOnr/IwluNdd6oalo2NnLK+0YRPz12vHjBmT6SY4CzkIRA2zXy5RV7HSMLD7q1ztjzeml0oheKmncrDkmhMloDLx4pOry9SI+YyoJa4DvzPoB+tyvz2G5eMWuPuxVjV2xNR7zpA+0jHBjMrQg1KKCNkcxx/97O4Q88BWkXSysJr7QyNeboD5tVERvmRQbsnONeHg6Utc6+L3N0XYYxH9gkRqpnbCowEmGys2acVV4lQayHpcGOO1SxcGZMqz6j8yVdiWwh9jJJq4wEOBcUz+BNmZZq7O7q/9iitXAq117aeRR2s6DU1NimTtzAoffQhiVBIiaKLv6exf5Ufl7MMaA48FAYTMLkyKrrYr8Wll1VTMiexgOecNbuCk3GqD853+NnVpzrRqES7QJVYtwdYhFmga4TZtwUnL6BZIThQjwiydkGnxm+p4VSl9DlUEcj4A7wD1VpY0y35xpqb6UaoRVi8+Po+RlESeAAd4lk7UnRmPDhKgJyCQe4P8qTgZjsSHvIElYeFUjqg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN8PR11MB3795.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 93386b6e-496c-456c-f540-08d86f1506b3 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Oct 2020 01:12:16.9868 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SHTjC2bMlFwMfA1/FJ89WB59IVihGkkMpqZzrZyyqLky5iP+0GCFcxOmV4GI3wTvf27mKaA2nmvzYvvuaA6/Dg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1101MB2113 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Ananyev, Konstantin > Sent: Tuesday, October 13, 2020 00:25 > To: Wang, Haiyue ; Power, Ciara ; dev@dpdk.org > Cc: Zhao1, Wei ; Guo, Jia > Subject: RE: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth >=20 >=20 > > > -----Original Message----- > > > From: Ananyev, Konstantin > > > Sent: Monday, October 12, 2020 17:09 > > > To: Wang, Haiyue ; Power, Ciara ; dev@dpdk.org > > > Cc: Zhao1, Wei ; Guo, Jia > > > Subject: RE: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitw= idth > > > > > > > > > > From: Power, Ciara > > > > > > > Sent: Wednesday, September 30, 2020 21:04 > > > > > > > To: dev@dpdk.org > > > > > > > Cc: Power, Ciara ; Zhao1, Wei ; Guo, Jia > > > > > > > ; Wang, Haiyue > > > > > > > Subject: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD = bitwidth > > > > > > > > > > > > > > When choosing a vector path to take, an extra condition must = be > > > > > > > satisfied to ensure the max SIMD bitwidth allows for the CPU = enabled > > > > > > > path. > > > > > > > > > > > > > > Cc: Wei Zhao > > > > > > > Cc: Jeff Guo > > > > > > > > > > > > > > Signed-off-by: Ciara Power > > > > > > > --- > > > > > > > drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++-- > > > > > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixg= be/ixgbe_rxtx.c > > > > > > > index 977ecf5137..eadc7183f2 100644 > > > > > > > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > > > > > > > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > > > > > > > @@ -2503,7 +2503,9 @@ ixgbe_set_tx_function(struct rte_eth_de= v *dev, struct ixgbe_tx_queue > > > *txq) > > > > > > > dev->tx_pkt_prepare =3D NULL; > > > > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > > > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > > > > > - ixgbe_txq_vec_setup(txq) =3D=3D 0)) { > > > > > > > + ixgbe_txq_vec_setup(txq) =3D=3D 0) && > > > > > > > + rte_get_max_simd_bitwidth() > > > > > > > > > > > > As Konstantin mentioned: " I think it is a bit safer to do all = checks first before > > > > > > doing txq_vec_setup()." > > > > > > > > > > > > Fox x86 & arm platforms, the setup is always 0, since 'sw_ring_= v' is union with > > > > > > 'sw_ring' which is initialize at 'ixgbe_dev_tx_queue_setup'. > > > > > > > > > > > > union { > > > > > > struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for s= calar PMD. */ > > > > > > struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring f= or vector PMD */ > > > > > > }; > > > > > > > > > > > > static inline int > > > > > > ixgbe_txq_vec_setup_default(struct ixgbe_tx_queue *txq, > > > > > > const struct ixgbe_txq_ops *txq_ops) > > > > > > { > > > > > > if (txq->sw_ring_v =3D=3D NULL) > > > > > > return -1; > > > > > > > > > > > > /* leave the first one for overflow */ > > > > > > txq->sw_ring_v =3D txq->sw_ring_v + 1; > > > > > > txq->ops =3D txq_ops; > > > > > > > > > > > > return 0; > > > > > > } > > > > > > > > > > > > So we need check the SIMD bitwidth firstly to avoid changing th= e sw_ring* pointer address. > > > > > > > > > > > > > > > > > > Also, looks like we need to add check on: > > > > > > > > > > > > int > > > > > > ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) > > > > > > { > > > > > > struct ixgbe_tx_queue *txq =3D (struct ixgbe_tx_queue *)tx_que= ue; > > > > > > if (txq->offloads =3D=3D 0 && > > > > > > #ifdef RTE_LIBRTE_SECURITY > > > > > > !(txq->using_ipsec) && > > > > > > #endif > > > > > > txq->tx_rs_thresh >=3D RTE_PMD_IXGBE_TX_MAX_BURST) { > > > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > > > > <---------= ---------- Add the same check > > > > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > > > > txq->sw_ring_v !=3D NULL)) { > > > > > > return ixgbe_tx_done_cleanup_vec(txq, free_cnt); > > > > > > > > > > Could you probably explain a bit more why it is needed? > > > > > > > > To align with the vector selection path: > > > > > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > > ixgbe_txq_vec_setup(txq) =3D=3D 0)) > > > > > > > > > Ok, so to make sure that TX is running in vector mode? > > > > That's right, since no variable to save the vector mode selection, > > then the check condition should be the same. >=20 > What I am saying, that here instead of conditions we should check > was vector mode already selected or not. > Probably the easiest way to do it - check what tx function is setup. >=20 Misunderstood, yes, this is more intuitive and clean. > > > > > > > 2.17.1