From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E1342A0A0E; Wed, 12 May 2021 03:13:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 605734003F; Wed, 12 May 2021 03:13:50 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 95C0B4003E; Wed, 12 May 2021 03:13:48 +0200 (CEST) IronPort-SDR: 2sPc2uKTVJJ9WJUm0rwOa6Uqevw3+DulqYPBXrmFl69kJOYZ3n8rCPBqHNUhcd5rzjWYpn76qO BLmORuuLIZLg== X-IronPort-AV: E=McAfee;i="6200,9189,9981"; a="199639324" X-IronPort-AV: E=Sophos;i="5.82,292,1613462400"; d="scan'208";a="199639324" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 18:13:46 -0700 IronPort-SDR: 8/PSqvDhiJ8ZnYsz+TubbTBkeljMaWjo9sueX7i1AY+YzCOUDwvvXHX1Q77F55A7dk2rnVeAwE isNKhi81yZiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,292,1613462400"; d="scan'208";a="469170483" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga002.fm.intel.com with ESMTP; 11 May 2021 18:13:46 -0700 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 11 May 2021 18:13:45 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 11 May 2021 18:13:45 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2 via Frontend Transport; Tue, 11 May 2021 18:13:45 -0700 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (104.47.66.43) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2106.2; Tue, 11 May 2021 18:13:45 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YxK70gl/W5WVpoulINlEYNwHk/zo2CKrYVIjWWMUkWRAdK9qlIyZJt8ucJl0k9zzvV9iIWEjxiTf9qBhs0hHnmf1uWywHl4DXGbvmneHlRhSUy7tk6rK0XxCaSDgq14hxhhRMNIOjVenofPWaWLBYTSczu0XwWvNStSoFbum5uoh2W9F0Wg0f674VJt6dte0LFxiW9bWJ6Jp+DAmTlSHThlDrplv+hl+tQnbj3NqT84uVXslwmMphCzg9vJkGybqXBLCLWFYCgbJke8Ynr7V7CH33h6y3YMFp4dzq91gtQwtVBH1hGLN+mAbtb/BkdvYEw8QPkbpIGnxoI75JdU6Ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uOOFUzTWGEDI/UHALbBBre00CMmdQi7s+0ETqR91C+w=; b=BIwt0663irLSdSSFPVBC/ynPJUtE3NHHRcaAuDL7uPM6h6jGW1gasWqM3OcidRYBtLbVNvfUh+Vu4fm+wkK6KUZxkQj1Ok/G9ebJzmf89jywXMvDYPTzqePp8P5aP9X6z8bzXR+NvsI68OKj/nt1+ltNyCWNiDUWyZ3MnxBNb1wwZdS9k7BRH6g1NHs4DXMXM+GZ1wtRtoJBLxnwd5xqg4jymc/LN25aagwQwCC12370yEBIG4plFpxyCRzlqkNKtFfQIlBWOgUk3yqEaFlrr0sJ3CGE5HRdYwjNxaNLzCAfp40b3cqmIDF5lzBLO6j1YbNyiAk0NxzPlPMIwYQqaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uOOFUzTWGEDI/UHALbBBre00CMmdQi7s+0ETqR91C+w=; b=sfllu0WZKRoMFYNtpyo/Op0MvZihUy8ZuVOhnl8IiyrBfiUSwNxJIoS/j6+hAxK3rLorP8FUh0xHlkQNCQ878LO2a62U2YpJ95S29EeugfivNMQ13BcaGQdp15JTNuZiXcRaapeNSBqh24nVvkjYB3oE1QXTo+0B4eiOjaX5Yus= Received: from BN8PR11MB3795.namprd11.prod.outlook.com (2603:10b6:408:82::31) by BN6PR11MB1363.namprd11.prod.outlook.com (2603:10b6:404:4a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.29; Wed, 12 May 2021 01:13:41 +0000 Received: from BN8PR11MB3795.namprd11.prod.outlook.com ([fe80::2dfc:3be2:c305:6346]) by BN8PR11MB3795.namprd11.prod.outlook.com ([fe80::2dfc:3be2:c305:6346%6]) with mapi id 15.20.4108.031; Wed, 12 May 2021 01:13:41 +0000 From: "Wang, Haiyue" To: Pavan Nikhilesh Bhagavatula , "david.marchand@redhat.com" , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko , Jiawen Wu , Jian Wang , "Chautru, Nicolas" , Thomas Monjalon , "Yigit, Ferruh" , Andrew Rybchenko CC: "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v3 2/2] eal: fix side effects in ptr align macros Thread-Index: AQHXRdRdxXcJzxJzZES0IhVxYyPnU6rdhwOQgABxGwCAARGasA== Date: Wed, 12 May 2021 01:13:41 +0000 Message-ID: References: <20210510140214.2627-1-pbhagavatula@marvell.com> <20210510194008.403-1-pbhagavatula@marvell.com> <20210510194008.403-2-pbhagavatula@marvell.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.0.76 authentication-results: marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.55.46.54] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6e930868-d775-437a-f831-08d914e32e6c x-ms-traffictypediagnostic: BN6PR11MB1363: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: wkxJtl8Ds7blGXpXULtzHPHBBPE5EMtqnwzEZNR/HoN+NWNygoL1snvL9MEkHFZX2dIJU5q51Kcblyz0Q1tnq44m8FT6Dw6BLZEythxQ1st09Qv4OzQhWI8mg/vWC56WaVMTxh+m4+b3LOZx1gitO9RpGu5MJai80Bv1BYC+ilwKUw5yZBnJmGk9EChNvuoIK8esT7FYfChdfN046JN4fer3hMvQHGiNTeX6j9noEzUDQ5WZ4KCAF+wNlX9shnnEejgHJjm2baQTiIpIE++GNZ790oYpZUcoUlVdxO3BLhGXwPAied9PhJi4ThTJ/NL3VMX9f9IVrXQUsBdL6ED8J9pvD7UJ3pT+TkmuzkkWcOTERhMyJZTo/VrfZ1KPYVNOdaL/u5EM3b23uGTKISAADebsWJ5p7H7V1/IGm6ev7zrrJTIwUdIWCpYun29IJEXRyr7hi+yT8+eDj7hpXAfSXTkfG/TWw3GGt7hpozYIo3rZRCUzdptsD5+Wrw3pF2vznnpGNnlTH7Iltd0obh9KTFXUxzW5T/53lUJs6pPfa1ZEfC2YTCgs2a5r9/V3ayN1ln6olYsfZRnxvCKZgh0Ox4s0O/QCMJiV2fId3ocsn5mIqdeeFgXoSVErg4nxbgtYh8/EkHAsjKkYXEFw4d/6PO+PwL5N7y4PVfv91cZqOKgQFfi5O4Eob4aOPsK/pFOU x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN8PR11MB3795.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(376002)(136003)(396003)(366004)(346002)(39860400002)(4326008)(8936002)(186003)(7416002)(76116006)(66476007)(54906003)(110136005)(8676002)(6506007)(66946007)(478600001)(316002)(2906002)(53546011)(7696005)(9686003)(66446008)(64756008)(5660300002)(52536014)(71200400001)(38100700002)(33656002)(86362001)(55016002)(83380400001)(26005)(122000001)(921005)(66556008)(56340200001); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: =?us-ascii?Q?o9qsUIIJnzEYFHRMXNTlU/TK69Rk9KC/7Wyeg5m2lVa6PaNIhJHGIlK3hPxS?= =?us-ascii?Q?V+ZWbZOx0gtmeW5nBqX8nn/p5ZM+nU6tZxvvtZzg4CQ8WQcbsip2txCNBu7Z?= =?us-ascii?Q?pSdo28qZcJXjo4ghIh6UqlCg0ndVeFiaUd0XY3eD7yN4pOatdAo6YTU5CZee?= =?us-ascii?Q?0PrSaCOIvkbXHn61KT6ut/2PKAPrvhDDaME8YPH/FwexCml0TPh5ydCzGMKt?= =?us-ascii?Q?uOzcqOho1s4X+GLiCfjcNb3lXxZyn58ECUAWQZpRSYPrr0MG7zH0JgQcx00R?= =?us-ascii?Q?9kshTFPYKVmmFTyT5f97oSjO6BLhiH78MsQtg9onuEMupt7R8gjT6C8FZPgn?= =?us-ascii?Q?JlCH5ILhECu20E6pcX5F6PE8R7WOyE1m4WQQY4z6p3ngNruNOtF8/ZdD9wdz?= =?us-ascii?Q?+6GIJuzNwzWqE6V83HqLX7I8rBhI2ZCIa13Nt+TkTIw+qCecwVleDCGPzKsQ?= =?us-ascii?Q?81d2mqtjNuXe7PsIVbdpf5kKt0Q7hY+H2s87upxrY9l4Y1+NGZGMZ7ryYnQZ?= =?us-ascii?Q?fRzcs/aVwRnF0oKeT9gqVK0lyPBNjtkOkQfjNlTMqwOU3fpq3cPfspq5tsFV?= =?us-ascii?Q?GLsM0eykqZBlwUIq490VrkLt0fwqN4Zsd/OvJshFddQHFQh+QvWaC2smxMMi?= =?us-ascii?Q?mftp6uvr9nGM3bsfxR06VsDFTYs3UOn9Gshpn0nSbBXjskz/Es7mX7E/BqgC?= =?us-ascii?Q?9FASJTMCwgRF+/GHGv2emmoGXFN+my9jdmf5oAfuk9SSaHrMWie8wsvBEKEh?= =?us-ascii?Q?q1+ZyUxm93F6w4RQpoF9xy92ZTbDxIqlYoFnmSBSHmENz4EXwjd6g45BrEe2?= =?us-ascii?Q?Q2e4iaQtg8QMqaIXG3oRlWZ1AvT3WfQfSXsezi7mEBtVAWw0amyokGSSrEX6?= =?us-ascii?Q?ATbKouQusPpHNGrv54ZZnAza1oN2QT//NX5RuBXLo/bR7b6djceWkgowXSoe?= =?us-ascii?Q?XZVTufEZx12Bs0ICmnr9KARf2ZqNf5RA48i7nLlGjqui9hricbEnX0CUP+WA?= =?us-ascii?Q?+sLFi+n94SAdhJ8YRzGdoZWUuYcoVPT0zZd5Zo26gk0ec57pdjEtmcC/v9cr?= =?us-ascii?Q?BiFhaXqVAPsnaS1PH7p7go7Uw/daBz6+1RPUvl+Q8y/4Fomic4Mi3GFZg9Ti?= =?us-ascii?Q?3uOIw38s9VYvwUa3emcqt4RTi7ul+9ymNcoC9B21ie6rfNaDkvO2yVQAPKIJ?= =?us-ascii?Q?8D6djFMFkH7CSndd6QyIWWA2QnimrqcOvzyIDbTLU6SDbqE0Lv7GBi2qEF2Y?= =?us-ascii?Q?DMUMgzvPViEzrfvRL5IwUYUQfBtHte+tLADAoJKtr4WQJ0M6/jy1L/1lxxnw?= =?us-ascii?Q?dvs=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN8PR11MB3795.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6e930868-d775-437a-f831-08d914e32e6c X-MS-Exchange-CrossTenant-originalarrivaltime: 12 May 2021 01:13:41.7271 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4EztRB/Hp/xXQ276orSDoi+F6VJI+JtRJ/EHIOT24993TfC8lic/Pm6rPkZFwnHAF/MVLeFaB/PoZURn8vTAWA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1363 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 2/2] eal: fix side effects in ptr align macros X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Pavan Nikhilesh Bhagavatula > Sent: Tuesday, May 11, 2021 16:45 > To: Wang, Haiyue ; david.marchand@redhat.com; Mata= n Azrad ; > Shahaf Shuler ; Viacheslav Ovsiienko ; Jiawen Wu > ; Jian Wang ; Chautru, = Nicolas > ; Thomas Monjalon ; Yigit= , Ferruh > ; Andrew Rybchenko > Cc: dev@dpdk.org; stable@dpdk.org > Subject: RE: [dpdk-dev] [PATCH v3 2/2] eal: fix side effects in ptr align= macros >=20 > >> -----Original Message----- > >> From: pbhagavatula@marvell.com > >> Sent: Tuesday, May 11, 2021 03:40 > >> To: david.marchand@redhat.com; Wang, Haiyue > >; Matan Azrad ; > >> Shahaf Shuler ; Viacheslav Ovsiienko > >; Jiawen Wu > >> ; Jian Wang ; > >Chautru, Nicolas > >> ; Thomas Monjalon > >; Yigit, Ferruh > >> ; Andrew Rybchenko > > > >> Cc: dev@dpdk.org; Pavan Nikhilesh ; > >stable@dpdk.org > >> Subject: [dpdk-dev] [PATCH v3 2/2] eal: fix side effects in ptr align > >macros > >> > >> From: Pavan Nikhilesh > >> > >> Avoid expanding parameters inside RTE_*_ALIGN macros. > >> Update common_autotest to detect macro side effects. > >> Workaround static arrays relying on RTE_ALIGN macros. > >> > >> Fixes: af75078fece3 ("first public release") > >> Cc: stable@dpdk.org > >> > >> Signed-off-by: Pavan Nikhilesh > >> Signed-off-by: David Marchand > >> --- > >> app/test/test_common.c | 6 ++++++ > >> drivers/net/e1000/e1000_ethdev.h | 7 ++++--- > >> drivers/net/ixgbe/ixgbe_ethdev.h | 6 ++++-- > >> drivers/net/mlx5/mlx5_rxtx_vec.h | 7 ++++--- > >> drivers/net/txgbe/txgbe_ethdev.h | 6 ++++-- > >> examples/bbdev_app/main.c | 2 +- > >> lib/eal/include/rte_common.h | 17 +++++++++++++---- > >> lib/ethdev/rte_eth_ctrl.h | 5 +++-- > >> 8 files changed, 39 insertions(+), 17 deletions(-) > >> > >> diff --git a/app/test/test_common.c b/app/test/test_common.c > >> index 0dbb87e741..9efe3b10f9 100644 > >> --- a/app/test/test_common.c > >> +++ b/app/test/test_common.c > >> @@ -69,6 +69,12 @@ test_macros(int __rte_unused unused_parm) > >> TEST_SIDE_EFFECT_2(RTE_PTR_ADD, void *, size_t); > >> TEST_SIDE_EFFECT_2(RTE_PTR_DIFF, void *, void *); > >> TEST_SIDE_EFFECT_2(RTE_PTR_SUB, void *, size_t); > >> + TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN, void *, size_t); > >> + TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN_CEIL, void *, size_t); > >> + TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN_FLOOR, void *, size_t); > >> + TEST_SIDE_EFFECT_2(RTE_ALIGN, unsigned int, unsigned int); > >> + TEST_SIDE_EFFECT_2(RTE_ALIGN_CEIL, unsigned int, unsigned > >int); > >> + TEST_SIDE_EFFECT_2(RTE_ALIGN_FLOOR, unsigned int, > >unsigned int); > >> TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_CEIL, unsigned int, > >unsigned int); > >> TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_FLOOR, unsigned int, > >unsigned int); > >> TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_NEAR, unsigned int, > >unsigned int); > >> diff --git a/drivers/net/e1000/e1000_ethdev.h > >b/drivers/net/e1000/e1000_ethdev.h > >> index 3b4d9c3ee6..155d825d89 100644 > >> --- a/drivers/net/e1000/e1000_ethdev.h > >> +++ b/drivers/net/e1000/e1000_ethdev.h > >> @@ -332,9 +332,10 @@ struct igb_eth_syn_filter_ele { > >> }; > >> > >> #define IGB_FLEX_FILTER_MAXLEN 128 /**< bytes to use in flex > >filter. */ > >> -#define IGB_FLEX_FILTER_MASK_SIZE \ > >> - (RTE_ALIGN(IGB_FLEX_FILTER_MAXLEN, CHAR_BIT) / > >CHAR_BIT) > >> - /**< mask bytes in flex filter. */ > >> +#define IGB_FLEX_FILTER_MASK_SIZE = \ > >> + (RTE_ALIGN_FLOOR(IGB_FLEX_FILTER_MAXLEN + (CHAR_BIT - > >1), CHAR_BIT) / \ > >> + CHAR_BIT) > >> +/**< mask bytes in flex filter. */ > >> > > > >Since: > >RTE_ALIGN --> RTE_ALIGN_CEIL(val, align) --> RTE_ALIGN_FLOOR(...) > > > >Why only change 'RTE_ALIGN_CEIL', but then call 'RTE_ALIGN_FLOOR' > >directly ? > >Sorry, can't get the point. : - ( > > >=20 > RTE_ALIGN_CEIL is prone to macro side effects since it uses align twice i= n the macro. > To fix it RTE_ALIGN_CEIL first expands the val and align values to tempor= ary values > and then calls ALIGN_FLOOR. > Due to this we can no longer use ALIGN/ALIGN_CEIL in static array declara= tions >=20 > Example: > In file included from ../lib/eal/x86/include/rte_atomic.h:13, > from ../examples/bbdev_app/main.c:21: > ../lib/eal/include/rte_common.h:312:15: error: braced-group within expres= sion allowed only inside a > function > __extension__({ = \ > ^ > ../examples/bbdev_app/main.c:48:18: note: in expansion of macro 'RTE_ALIG= N_CEIL' > #define NCB (3 * RTE_ALIGN_CEIL(K + 4, 32)) > ^~~~~~~~~~~~~~ > ../examples/bbdev_app/main.c:145:23: note: in expansion of macro 'NCB' > uint8_t llr_temp_buf[NCB]; >=20 > To workaround this I had to call RTE_ALIGN_FLOOR for known constants dire= ctly. >=20 Clear now, thanks. For Intel PMDs, Acked-by: Haiyue Wang BTW, I'm wondering that we can explicitly define the macro with type style like RTE_ALIGN_CEIL_TYPE, so that people can notice the side effects direct= ly, and choose the right ALIGN macro. And can still use ALIGN/ALIGN_CEIL in static array declarations, which is very simple. Just my thinking. ;-) > >Why not change 'RTE_ALIGN' if it has issue ? > > > >> > >> diff --git a/lib/eal/include/rte_common.h > >b/lib/eal/include/rte_common.h > >> index a142596587..6acd067b5c 100644 > >> --- a/lib/eal/include/rte_common.h > >> +++ b/lib/eal/include/rte_common.h > >> @@ -294,8 +294,13 @@ static void > >__attribute__((destructor(RTE_PRIO(prio)), used)) func(void) > >> * point to an address no lower than the first parameter. Second > >parameter > >> * must be a power-of-two value. > >> */ > >> -#define RTE_PTR_ALIGN_CEIL(ptr, align) \ > >> - RTE_PTR_ALIGN_FLOOR((typeof(ptr))RTE_PTR_ADD(ptr, (align) > >- 1), align) > >> +#define RTE_PTR_ALIGN_CEIL(ptr, align) = \ > >> + __extension__({ = \ > >> + typeof(ptr) _pc =3D (ptr); \ > >> + typeof(align) _ac =3D (align); \ > >> + > > RTE_PTR_ALIGN_FLOOR((typeof(ptr))RTE_PTR_ADD(_pc, _ac - > >1), \ > >> + _ac); \ > >> + }) > >> > >> /** > >> * Macro to align a value to a given power-of-two. The resultant valu= e > >> @@ -303,8 +308,12 @@ static void > >__attribute__((destructor(RTE_PRIO(prio)), used)) func(void) > >> * than the first parameter. Second parameter must be a power-of- > >two > >> * value. > >> */ > >> -#define RTE_ALIGN_CEIL(val, align) \ > >> - RTE_ALIGN_FLOOR(((val) + ((typeof(val)) (align) - 1)), align) > >> +#define RTE_ALIGN_CEIL(val, align) = \ > >> + __extension__({ = \ > >> + typeof(val) _vc =3D (val); \ > >> + typeof(val) _ac =3D (typeof(val))(align); \ > >> + RTE_ALIGN_FLOOR((_vc + _ac - 1), _ac); \ > >> + }) > >> > >> /** > >> * Macro to align a pointer to a given power-of-two. The resultant > >> diff --git a/lib/ethdev/rte_eth_ctrl.h b/lib/ethdev/rte_eth_ctrl.h > >> index 42652f9cce..863e56170b 100644 > >> --- a/lib/ethdev/rte_eth_ctrl.h > >> +++ b/lib/ethdev/rte_eth_ctrl.h > >> @@ -431,8 +431,9 @@ enum rte_fdir_mode { > >> }; > >> > >> #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t)) > >> -#define RTE_FLOW_MASK_ARRAY_SIZE \ > >> - (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) > >> +#define RTE_FLOW_MASK_ARRAY_SIZE = \ > >> + (RTE_ALIGN_FLOOR(RTE_ETH_FLOW_MAX + (UINT64_BIT - 1), > >UINT64_BIT) / \ > >> + UINT64_BIT) > >> > >> /** > >> * A structure used to get the information of flow director filter. > >> -- > >> 2.17.1