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Thu, 14 Oct 2021 09:31:06 +0000 From: Harman Kalra To: Thomas Monjalon , David Marchand CC: "dev@dpdk.org" , Raslan Darawsheh , Ray Kinsella , Dmitry Kozlyuk , "viacheslavo@nvidia.com" , "matan@nvidia.com" Thread-Topic: [dpdk-dev] [EXT] Re: [PATCH v1 2/7] eal/interrupts: implement get set APIs Thread-Index: AQHXv3z/vwDxAXEBi0ulm3+8amQc96vRLyBggAAJB3CAAA+/gIAA4m4AgAAQGMA= Date: Thu, 14 Oct 2021 09:31:05 +0000 Message-ID: References: <20210826145726.102081-1-hkalra@marvell.com> <24392547.dnzkRMgc80@thomas> <10896897.yJauvYxkRq@thomas> In-Reply-To: <10896897.yJauvYxkRq@thomas> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d9bebcf2-8951-4f1a-a5e1-08d98ef55907 x-ms-traffictypediagnostic: BN6PR18MB1458: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 2rkLZ7Kow71/rnXg4YsttyoNLfZiCY0eTsTO6R5t9Q5R3d6ujaWH0I0AAydnh0TW7c+M5vAlxUISyF7d/FMf2y2LmIj5hyBQ7QogDldsnGO2tdh7UsuBH0QFQU0o978671bU2ho3bStZWJx3SH/nUEV5hHdQObbJOo2TUdSSivZBowdTQ+CxeGmHGjYluEDqb6+sMtPIQUzdmC94dpx8iGWMtCDR9me2DmdWLkQJ86U0rnDrzJxYp4V/HdIlxTiBqHZMtgKW2K5CfxDV1OIijd/8gaTt5osaV71op8Rr5PwX2Qxf/lPe+RDXn59/g39CQ8DegUelNKmh6VCt5hGZGQBvBmBkBHW6jZS0M0g+Bdk3MYfAoot+AdhvRNyebu1xX9Qc6fobJ5XOXNJ2IJm6cmLrcDF8V2ondM0b+aWyc9Op/2UlJxVWhDE+ZnZwdUq9Z+JDEwQkQ/E0LO+biNyZortwQi0yBEZpBmYurc6MiPq8ng1oksdR6Arvy4kxd6cskgyN3yfUO56tdlu1lbztekURHwmHNbZa94GN+ZX9Z68P8k17kFZPrmxtNfJW4XaRBRXXlBiUtjRikDVTRhxD4f+q0h2z3hnSqr1U9K118u4F/kDY6ki4rmhp/e0bC0LOnHTWrwyMUX7YHLunqXw/ciopNZ3FWNCJsK5TVexmiAQOjJ+hXb5ZuQ3q8EDB7FKxSZ2Yraiz29WdUzJAFVPf5A== x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR18MB4204.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d9bebcf2-8951-4f1a-a5e1-08d98ef55907 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2021 09:31:05.9360 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: HW75mFtDTDIuFpcRHfHprXs63W4ipuJq76vfSMAgfxjJRXto32kgmaTMP5Ggo7lAVSwCY6KUDYNTKuaUkMD8Qg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR18MB1458 X-Proofpoint-GUID: vC7sJ59mUwWVsMiBFAIa2-17xbr1SCOF X-Proofpoint-ORIG-GUID: vC7sJ59mUwWVsMiBFAIa2-17xbr1SCOF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-14_03,2021-10-14_01,2020-04-07_01 Subject: Re: [dpdk-dev] [EXT] Re: [PATCH v1 2/7] eal/interrupts: implement get set APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Thomas Monjalon > Sent: Thursday, October 14, 2021 1:53 PM > To: Harman Kalra > Cc: dev@dpdk.org; Raslan Darawsheh ; Ray Kinsella > ; Dmitry Kozlyuk ; David > Marchand ; viacheslavo@nvidia.com; > matan@nvidia.com > Subject: Re: [dpdk-dev] [EXT] Re: [PATCH v1 2/7] eal/interrupts: implemen= t > get set APIs >=20 > 13/10/2021 20:52, Thomas Monjalon: > > 13/10/2021 19:57, Harman Kalra: > > > From: dev On Behalf Of Harman Kalra > > > > From: Thomas Monjalon > > > > > 04/10/2021 11:57, David Marchand: > > > > > > On Mon, Oct 4, 2021 at 10:51 AM Harman Kalra > > > > > > > > > > > wrote: > > > > > > > > > +struct rte_intr_handle *rte_intr_handle_instance_alloc(i= nt > size, > > > > > > > > > + > > > > > > > > > +bool > > > > > > > > > +from_hugepage) { > > > > > > > > > + struct rte_intr_handle *intr_handle; > > > > > > > > > + int i; > > > > > > > > > + > > > > > > > > > + if (from_hugepage) > > > > > > > > > + intr_handle =3D rte_zmalloc(NULL, > > > > > > > > > + size * sizeof(s= truct rte_intr_handle), > > > > > > > > > + 0); > > > > > > > > > + else > > > > > > > > > + intr_handle =3D calloc(1, size * > > > > > > > > > + sizeof(struct rte_intr_handle)); > > > > > > > > > > > > > > > > We can call DPDK allocator in all cases. > > > > > > > > That would avoid headaches on why multiprocess does not > > > > > > > > work in some rarely tested cases. > [...] > > > > > I agree with David. > > > > > I prefer a simpler API which always use rte_malloc, and make > > > > > sure interrupts are always handled between rte_eal_init and > rte_eal_cleanup. > [...] > > > > There are couple of more dependencies on glibc heap APIs: > > > > 1. "rte_eal_alarm_init()" allocates an interrupt instance which is > > > > used for timerfd, is called before "rte_eal_memory_init()" which > > > > does the memseg init. > > > > Not sure what all challenges we may face in moving alarm_init > > > > after memory_init as it might break some subsystem inits. > > > > Other option could be to allocate interrupt instance for timerfd > > > > on first alarm_setup call. > > > > Indeed it is an issue. > > > > [...] > > > > > > There are many other drivers which statically declares the > > > > interrupt handles inside their respective private structures and > > > > memory for those structure was allocated from heap. For such > > > > drivers I allocated interrupt instances also using glibc heap APIs. > > > > Could you use rte_malloc in these drivers? >=20 > If we take the direction of 2 different allocations mode for the interrup= ts, I > suggest we make it automatic without any API parameter. > We don't have any function to check rte_malloc readiness I think. > But we can detect whether shared memory is ready with this check: > rte_eal_get_configuration()->mem_config->magic =3D=3D RTE_MAGIC This chec= k > is true at the end of rte_eal_init, so it is false during probing. > Would it be enough? Or should we implement rte_malloc_is_ready()? Hi Thomas, It's a very good suggestion. Let's implement "rte_malloc_is_ready()" which = could be as simple as " rte_eal_get_configuration()->mem_config->magic =3D=3D RTE_MAGIC= " check. There may be more consumers for this API in future. If we are making it automatic detection, shall we now even have argument to= this alloc API? I added a flags argument (32 bit) in latest series where each bit of this f= lag can be an allocation capability. I used two bits for discriminating between glibc malloc and rte_malloc. Sha= ll we keep it or drop it? David, Dmitry please share your thoughts. Thanks Harman >=20