* [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device
@ 2022-04-27 18:16 Nicolas Chautru
2022-04-27 18:16 ` [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
` (7 more replies)
0 siblings, 8 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-04-27 18:16 UTC (permalink / raw)
To: dev, gakhil
Cc: trix, thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand, Nicolas Chautru
v2: Based on good feedback from Thomas and David,
now implementing the ACC101 PMD as a close derivative from
existing ACC100 PMD with hooks to have different behaviour based on variant.
This prevents code duplication and only rely on different functions and behaviour
when hardware requires or support differences.
Note that these are pending changes for ACC100 which would be specific to
that device and not ACC101 but these can be managed based on the new
implementation, ie. is_acc100() etc... (such incremental changes for ACC100
trending 22.11 but confirming this is future proof).
The serie also includes commits which were meant for ACC101 but are also
valuable for ACC100.
v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
This is a derivative from previous Mount Bryce ACC100 which includes silicon
improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
Nicolas Chautru (5):
baseband/acc100: introduce PMD for ACC101
baseband/acc100: modify validation code for ACC101
baseband/acc100: configuration of ACC101 from PF
baseband/acc100: start explicitly PF Monitor from PMD
baseband/acc100: add protection for some negative scenario
app/test-bbdev/test_bbdev_perf.c | 57 ++++
doc/guides/bbdevs/acc101.rst | 237 ++++++++++++++
doc/guides/bbdevs/features/acc101.ini | 13 +
doc/guides/bbdevs/index.rst | 1 +
doc/guides/rel_notes/release_22_07.rst | 4 +
drivers/baseband/acc100/rte_acc100_cfg.h | 17 +
drivers/baseband/acc100/rte_acc100_pmd.c | 546 ++++++++++++++++++++++++++++++-
drivers/baseband/acc100/rte_acc100_pmd.h | 12 +
drivers/baseband/acc100/rte_acc101_pmd.h | 61 ++++
drivers/baseband/acc100/version.map | 2 +-
10 files changed, 932 insertions(+), 18 deletions(-)
create mode 100644 doc/guides/bbdevs/acc101.rst
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
@ 2022-04-27 18:16 ` Nicolas Chautru
2022-05-08 13:02 ` Tom Rix
2022-04-27 18:17 ` [PATCH v2 2/5] baseband/acc100: modify validation code " Nicolas Chautru
` (6 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-04-27 18:16 UTC (permalink / raw)
To: dev, gakhil
Cc: trix, thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand, Nicolas Chautru
Support for ACC101 as a derivative of ACC100.
Reusing existing code when possible.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
doc/guides/bbdevs/acc101.rst | 237 +++++++++++++++++++++++++++++++
doc/guides/bbdevs/features/acc101.ini | 13 ++
doc/guides/bbdevs/index.rst | 1 +
doc/guides/rel_notes/release_22_07.rst | 4 +
drivers/baseband/acc100/rte_acc100_pmd.c | 194 ++++++++++++++++++++++++-
drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
drivers/baseband/acc100/rte_acc101_pmd.h | 61 ++++++++
7 files changed, 511 insertions(+), 5 deletions(-)
create mode 100644 doc/guides/bbdevs/acc101.rst
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
diff --git a/doc/guides/bbdevs/acc101.rst b/doc/guides/bbdevs/acc101.rst
new file mode 100644
index 0000000..46c310b
--- /dev/null
+++ b/doc/guides/bbdevs/acc101.rst
@@ -0,0 +1,237 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2020 Intel Corporation
+
+Intel(R) ACC101 5G/4G FEC Poll Mode Driver
+==========================================
+
+The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an
+implementation of a VRAN FEC wireless acceleration function.
+This device is also known as Mount Cirrus.
+This is a follow-up to Mount Bryce (ACC100) and includes fixes, improved
+feature set for error scenarios and performance capacity increase.
+
+Features
+--------
+
+ACC101 5G/4G FEC PMD supports the following features:
+
+- LDPC Encode in the DL (5GNR)
+- LDPC Decode in the UL (5GNR)
+- Turbo Encode in the DL (4G)
+- Turbo Decode in the UL (4G)
+- 16 VFs per PF (physical device)
+- Maximum of 128 queues per VF
+- PCIe Gen-3 x16 Interface
+- MSI
+- SR-IOV
+
+ACC101 5G/4G FEC PMD supports the following BBDEV capabilities:
+
+* For the LDPC encode operation:
+ - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
+ - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass
+ - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS`` : if set then bypass interleaver
+
+* For the LDPC decode operation:
+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
+ - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination
+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding
+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits
+ - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
+ - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION`` : supports compression of the HARQ input/output
+ - ``RTE_BBDEV_LDPC_LLR_COMPRESSION`` : supports LLR input compression
+
+* For the turbo encode operation:
+ - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
+ - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass
+ - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts
+ - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` : set to bypass RV index
+ - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` : supports scatter-gather for input/output data
+
+* For the turbo decode operation:
+ - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)
+ - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave
+ - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts
+ - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported
+ - ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN`` : set if positive LLR encoder i/p is supported
+ - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding
+ - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP`` : option to drop the code block CRC after decoding
+ - ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` : set early termination feature
+ - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
+ - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity
+
+Installation
+------------
+
+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
+
+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
+The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
+hugepage configuration of a server may be examined using:
+
+.. code-block:: console
+
+ grep Huge* /proc/meminfo
+
+
+Initialization
+--------------
+
+When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+
+.. code-block:: console
+
+ sudo lspci -vd8086:57c4
+
+The physical and virtual functions are compatible with Linux UIO drivers:
+``vfio`` and ``igb_uio``. However, in order to work the ACC101 5G/4G
+FEC device first needs to be bound to one of these linux drivers through DPDK.
+
+
+Bind PF UIO driver(s)
+~~~~~~~~~~~~~~~~~~~~~
+
+Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
+``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
+
+The igb_uio driver may be bound to the PF PCI device using one of two methods:
+
+
+1. PCI functions (physical or virtual, depending on the use case) can be bound to
+the UIO driver by repeating this command for every function.
+
+.. code-block:: console
+
+ cd <dpdk-top-level-directory>
+ insmod ./build/kmod/igb_uio.ko
+ echo "8086 57c4" > /sys/bus/pci/drivers/igb_uio/new_id
+ lspci -vd8086:57c4
+
+
+2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
+
+.. code-block:: console
+
+ cd <dpdk-top-level-directory>
+ ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
+
+where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:57c4
+
+
+In a similar way the ACC101 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
+
+
+Enable Virtual Functions
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Now, it should be visible in the printouts that PCI PF is under igb_uio control
+"``Kernel driver in use: igb_uio``"
+
+To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
+
+.. code-block:: console
+
+ cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
+
+ where 0000\:<b>\:<d>.<f> is the PCI device ID
+
+
+To enable VFs via igb_uio, echo the number of virtual functions intended to
+enable to ``max_vfs`` file..
+
+.. code-block:: console
+
+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
+
+
+Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
+way it was done with the physical function previously.
+
+Enabling SR-IOV via vfio driver is pretty much the same, except that the file
+name is different:
+
+.. code-block:: console
+
+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
+
+
+Configure the VFs through PF
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The PCI virtual functions must be configured before working or getting assigned
+to VMs/Containers. The configuration involves allocating the number of hardware
+queues, priorities, load balance, bandwidth and other settings necessary for the
+device to perform FEC functions.
+
+This configuration needs to be executed at least once after reboot or PCI FLR and can
+be achieved by using the function ``acc101_configure()``, which sets up the
+parameters defined in ``acc100_conf`` structure.
+
+Test Application
+----------------
+
+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
+the functionality of ACC101 5G/4G FEC encode and decode, depending on the device's
+capabilities. The test application is located under app->test-bbdev folder and has the
+following options:
+
+.. code-block:: console
+
+ "-p", "--testapp-path": specifies path to the bbdev test app.
+ "-e", "--eal-params" : EAL arguments which are passed to the test app.
+ "-t", "--timeout" : Timeout in seconds (default=300).
+ "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
+ "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
+ "-n", "--num-ops" : Number of operations to process on device (default=32).
+ "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
+ "-s", "--snr" : SNR in dB used when generating LLRs for bler tests.
+ "-s", "--iter_max" : Number of iterations for LDPC decoder.
+ "-l", "--num-lcores" : Number of lcores to run (default=16).
+ "-i", "--init-device" : Initialise PF device with default values.
+
+
+To execute the test application tool using simple decode or encode data,
+type one of the following:
+
+.. code-block:: console
+
+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
+
+
+The test application ``test-bbdev.py``, supports the ability to configure the PF device with
+a default set of values, if the "-i" or "- -init-device" option is included. The default values
+are defined in test_bbdev_perf.c.
+
+
+Test Vectors
+~~~~~~~~~~~~
+
+In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
+a range of additional tests under the test_vectors folder, which may be useful. The results
+of these tests will depend on the ACC101 5G/4G FEC capabilities which may cause some
+testcases to be skipped, but no failure should be reported.
+
+
+Alternate Baseband Device configuration tool
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+On top of the embedded configuration feature supported in test-bbdev using "- -init-device"
+option mentioned above, there is also a tool available to perform that device configuration
+using a companion application.
+The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF
+and not only limited to the PF as captured above.
+
+See for more details: https://github.com/intel/pf-bb-config
+
+Specifically for the BBDEV ACC101 PMD, the command below can be used:
+
+.. code-block:: console
+
+ ./pf_bb_config ACC101 -c acc101/acc101_config_4vf_4g5g.cfg
+ ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -l 1 -v ./ldpc_dec_default.data
\ No newline at end of file
diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
new file mode 100644
index 0000000..0e2c21a
--- /dev/null
+++ b/doc/guides/bbdevs/features/acc101.ini
@@ -0,0 +1,13 @@
+;
+; Supported features of the 'acc101' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G) = Y
+Turbo Encoder (4G) = Y
+LDPC Decoder (5G) = Y
+LDPC Encoder (5G) = Y
+LLR/HARQ Compression = Y
+External DDR Access = Y
+HW Accelerated = Y
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index cedd706..e76883c 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -14,4 +14,5 @@ Baseband Device Drivers
fpga_lte_fec
fpga_5gnr_fec
acc100
+ acc101
la12xx
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 42a5f2d..ef9906b 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -55,6 +55,10 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Added Intel ACC101 baseband PMD.**
+
+ * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
+ * See the :doc:`../bbdevs/acc101` for more details.
Removed Items
-------------
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index de7e4bc..fca27ef 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -22,6 +22,7 @@
#include <rte_bbdev.h>
#include <rte_bbdev_pmd.h>
#include "rte_acc100_pmd.h"
+#include "rte_acc101_pmd.h"
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
@@ -1286,6 +1287,12 @@
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
}
+static inline bool
+is_acc100(struct acc100_queue *q)
+{
+ return (q->d->device_variant == ACC100_VARIANT);
+}
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -1412,6 +1419,139 @@
}
}
+/* Convert offset to harq index for harq_layout structure */
+static inline uint32_t hq_index(uint32_t offset)
+{
+ return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
+}
+
+/* Fill in a frame control word for LDPC decoding for ACC101 */
+static inline void
+acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout)
+{
+ uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
+ uint32_t harq_index;
+ uint32_t l;
+
+ fcw->qm = op->ldpc_dec.q_m;
+ fcw->nfiller = op->ldpc_dec.n_filler;
+ fcw->BG = (op->ldpc_dec.basegraph - 1);
+ fcw->Zc = op->ldpc_dec.z_c;
+ fcw->ncb = op->ldpc_dec.n_cb;
+ fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
+ op->ldpc_dec.rv_index);
+ if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
+ fcw->rm_e = op->ldpc_dec.cb_params.e;
+ else
+ fcw->rm_e = (op->ldpc_dec.tb_params.r <
+ op->ldpc_dec.tb_params.cab) ?
+ op->ldpc_dec.tb_params.ea :
+ op->ldpc_dec.tb_params.eb;
+
+ if (unlikely(check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
+ (op->ldpc_dec.harq_combined_input.length == 0))) {
+ rte_bbdev_log(WARNING, "Null HARQ input size provided");
+ /* Disable HARQ input in that case to carry forward */
+ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+ }
+
+ fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+ fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+ fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+ fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DECODE_BYPASS);
+ fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
+ if (op->ldpc_dec.q_m == 1) {
+ fcw->bypass_intlv = 1;
+ fcw->qm = 2;
+ }
+ fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_LLR_COMPRESSION);
+ harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
+ if (fcw->hcin_en > 0) {
+ harq_in_length = op->ldpc_dec.harq_combined_input.length;
+ if (fcw->hcin_decomp_mode > 0)
+ harq_in_length = harq_in_length * 8 / 6;
+ harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
+ - op->ldpc_dec.n_filler);
+ /* Alignment on next 64B - Already enforced from HC output */
+ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
+ fcw->hcin_size0 = harq_in_length;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ } else {
+ fcw->hcin_size0 = 0;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ }
+
+ fcw->itmax = op->ldpc_dec.iter_max;
+ fcw->itstop = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+ fcw->synd_precoder = fcw->itstop;
+ /*
+ * These are all implicitly set
+ * fcw->synd_post = 0;
+ * fcw->so_en = 0;
+ * fcw->so_bypass_rm = 0;
+ * fcw->so_bypass_intlv = 0;
+ * fcw->dec_convllr = 0;
+ * fcw->hcout_convllr = 0;
+ * fcw->hcout_size1 = 0;
+ * fcw->so_it = 0;
+ * fcw->hcout_offset = 0;
+ * fcw->negstop_th = 0;
+ * fcw->negstop_it = 0;
+ * fcw->negstop_en = 0;
+ * fcw->gain_i = 1;
+ * fcw->gain_h = 1;
+ */
+ if (fcw->hcout_en > 0) {
+ parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
+ * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
+ k0_p = (fcw->k0 > parity_offset) ?
+ fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
+ ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
+ l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
+ harq_out_length = (uint16_t) fcw->hcin_size0;
+ harq_out_length = RTE_MAX(harq_out_length, l);
+ /* Cannot exceed the pruned Ncb circular buffer */
+ harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+ /* Alignment on next 64B */
+ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
+ fcw->hcout_size0 = harq_out_length;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ harq_layout[harq_index].offset = fcw->hcout_offset;
+ harq_layout[harq_index].size0 = fcw->hcout_size0;
+ } else {
+ fcw->hcout_size0 = 0;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ }
+}
+
+static inline void
+acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout, struct acc100_queue *q)
+{
+ if (is_acc100(q))
+ return acc100_fcw_ld_fill(op, fcw, harq_layout);
+ else
+ return acc101_fcw_ld_fill(op, fcw, harq_layout);
+}
+
+
/**
* Fills descriptor with data pointers of one block type.
*
@@ -2960,7 +3100,7 @@
struct acc100_fcw_ld *fcw;
uint32_t seg_total_left;
fcw = &desc->req.fcw_ld;
- acc100_fcw_ld_fill(op, fcw, harq_layout);
+ acc10x_fcw_ld_fill(op, fcw, harq_layout, q);
/* Special handling when overusing mbuf */
if (fcw->rm_e < ACC100_MAX_E_MBUF)
@@ -3027,7 +3167,7 @@
desc = q->ring_addr + desc_idx;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
- acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
+ acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q);
input = op->ldpc_dec.input.data;
h_output_head = h_output = op->ldpc_dec.hard_output.data;
@@ -4139,9 +4279,17 @@
dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
- ((struct acc100_device *) dev->data->dev_private)->pf_device =
- !strcmp(drv->driver.name,
- RTE_STR(ACC100PF_DRIVER_NAME));
+ if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) ||
+ (!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
+ } else {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
+ }
+
((struct acc100_device *) dev->data->dev_private)->mmio_base =
pci_dev->mem_resource[0].addr;
@@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);
RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);
+/* ACC101 PCI PF address map */
+static struct rte_pci_id pci_id_acc101_pf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+/* ACC101 PCI VF address map */
+static struct rte_pci_id pci_id_acc101_vf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+
+static struct rte_pci_driver acc101_pci_pf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_pf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+static struct rte_pci_driver acc101_pci_vf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_vf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);
+RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);
+
/*
* Workaround implementation to fix the power on status of some 5GUL engines
* This requires DMA permission if ported outside DPDK
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index cbcece2..6438031 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -22,6 +22,9 @@
#define rte_bbdev_log_debug(fmt, ...)
#endif
+#define ACC100_VARIANT 0
+#define ACC101_VARIANT 1
+
/* ACC100 PF and VF driver names */
#define ACC100PF_DRIVER_NAME intel_acc100_pf
#define ACC100VF_DRIVER_NAME intel_acc100_vf
@@ -67,6 +70,8 @@
#define ACC100_HARQ_LAYOUT (64*1024*1024)
/* Assume offset for HARQ in memory */
#define ACC100_HARQ_OFFSET (32*1024)
+#define ACC100_HARQ_OFFSET_SHIFT 15
+#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
#define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
/* Number of Virtual Functions ACC100 supports */
@@ -590,6 +595,7 @@ struct acc100_device {
uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
bool pf_device; /**< True if this is a PF ACC100 device */
bool configured; /**< True if this ACC100 device is configured */
+ uint16_t device_variant; /**< Device variant */
};
/**
diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h
new file mode 100644
index 0000000..efab400
--- /dev/null
+++ b/drivers/baseband/acc100/rte_acc101_pmd.h
@@ -0,0 +1,61 @@
+/* ACC101 PF and VF driver names */
+#define ACC101PF_DRIVER_NAME intel_acc101_pf
+#define ACC101VF_DRIVER_NAME intel_acc101_vf
+
+/* ACC101 PCI vendor & device IDs */
+#define RTE_ACC101_VENDOR_ID (0x8086)
+#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
+#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
+
+/* Define as 1 to use only a single FEC engine */
+#ifndef RTE_ACC101_SINGLE_FEC
+#define RTE_ACC101_SINGLE_FEC 0
+#endif
+
+/* Values used in writing to the registers */
+#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
+
+/* Number of Virtual Functions ACC101 supports */
+#define ACC101_NUM_VFS 16
+#define ACC101_NUM_QGRPS 8
+#define ACC101_NUM_AQS 16
+/* All ACC101 Registers alignment are 32bits = 4B */
+#define ACC101_BYTES_IN_WORD 4
+
+#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
+#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
+#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS Mon */
+#define ACC101_TMPL_PRI_0 0x03020100
+#define ACC101_TMPL_PRI_1 0x07060504
+#define ACC101_TMPL_PRI_2 0x0b0a0908
+#define ACC101_TMPL_PRI_3 0x0f0e0d0c
+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
+
+#define ACC101_NUM_TMPL 32
+/* Mapping of signals for the available engines */
+#define ACC101_SIG_UL_5G 0
+#define ACC101_SIG_UL_5G_LAST 8
+#define ACC101_SIG_DL_5G 13
+#define ACC101_SIG_DL_5G_LAST 15
+#define ACC101_SIG_UL_4G 16
+#define ACC101_SIG_UL_4G_LAST 19
+#define ACC101_SIG_DL_4G 27
+#define ACC101_SIG_DL_4G_LAST 31
+#define ACC101_NUM_ACCS 5
+#define ACC101_PF_VAL 2
+
+/* ACC101 Configuration */
+#define ACC101_CFG_DMA_ERROR 0x3D7
+#define ACC101_CFG_AXI_CACHE 0x11
+#define ACC101_CFG_QMGR_HI_P 0x0F0F
+#define ACC101_CFG_PCI_AXI 0xC003
+#define ACC101_CFG_PCI_BRIDGE 0x40006033
+#define ACC101_ENGINE_OFFSET 0x1000
+#define ACC101_LONG_WAIT 1000
+#define ACC101_GPEX_AXIMAP_NUM 17
+#define ACC101_CLOCK_GATING_EN 0x30000
+#define ACC101_DMA_INBOUND 0x104
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC101_HARQ_DDR (512 * 1)
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v2 2/5] baseband/acc100: modify validation code for ACC101
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-04-27 18:16 ` [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-04-27 18:17 ` Nicolas Chautru
2022-05-08 13:07 ` Tom Rix
2022-04-27 18:17 ` [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
` (5 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-04-27 18:17 UTC (permalink / raw)
To: dev, gakhil
Cc: trix, thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand, Nicolas Chautru
The validation requirement is different for the two
devices.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++----------
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index fca27ef..daf2ce0 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1293,6 +1293,14 @@
return (q->d->device_variant == ACC100_VARIANT);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+static inline bool
+validate_op_required(struct acc100_queue *q)
+{
+ return is_acc100(q);
+}
+#endif
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -2187,8 +2195,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo encoder parameters */
static inline int
-validate_enc_op(struct rte_bbdev_enc_op *op)
+validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
@@ -2325,8 +2335,10 @@ static inline uint32_t hq_index(uint32_t offset)
}
/* Validates LDPC encoder parameters */
static inline int
-validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
+validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
if (op->mempool == NULL) {
@@ -2378,8 +2390,10 @@ static inline uint32_t hq_index(uint32_t offset)
/* Validates LDPC decoder parameters */
static inline int
-validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
+validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
if (op->mempool == NULL) {
@@ -2434,7 +2448,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2488,7 +2502,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(ops[0]) == -1) {
+ if (validate_ldpc_enc_op(ops[0], q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2550,7 +2564,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(op) == -1) {
+ if (validate_ldpc_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2607,7 +2621,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2680,8 +2694,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo decoder parameters */
static inline int
-validate_dec_op(struct rte_bbdev_dec_op *op)
+validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
@@ -2827,7 +2843,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
@@ -3052,7 +3068,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3156,7 +3172,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3246,7 +3262,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-04-27 18:16 ` [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-04-27 18:17 ` [PATCH v2 2/5] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-04-27 18:17 ` Nicolas Chautru
2022-05-08 13:38 ` Tom Rix
2022-04-27 18:17 ` [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD Nicolas Chautru
` (4 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-04-27 18:17 UTC (permalink / raw)
To: dev, gakhil
Cc: trix, thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand, Nicolas Chautru
Adding companion function specific to ACC100 and it
can be called from bbdev-test when running from PF.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 57 ++++++
drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++
drivers/baseband/acc100/version.map | 2 +-
4 files changed, 377 insertions(+), 1 deletion(-)
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 0fa119a..baf5f6d 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -63,6 +63,8 @@
#define ACC100_QMGR_INVALID_IDX -1
#define ACC100_QMGR_RR 1
#define ACC100_QOS_GBR 0
+#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
+#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
#endif
#define OPS_CACHE_SIZE 256U
@@ -765,6 +767,61 @@ typedef int (test_case_function)(struct active_device *ad,
"Failed to configure ACC100 PF for bbdev %s",
info->dev_name);
}
+ if ((get_init_device() == true) &&
+ (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME))) {
+ struct rte_acc100_conf conf;
+ unsigned int i;
+
+ printf("Configure ACC101 FEC Driver %s with default values\n",
+ info->drv.driver_name);
+
+ /* clear default configuration before initialization */
+ memset(&conf, 0, sizeof(struct rte_acc100_conf));
+
+ /* Always set in PF mode for built-in configuration */
+ conf.pf_mode_en = true;
+ for (i = 0; i < RTE_ACC100_NUM_VFS; ++i) {
+ conf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_dl_4g[i].round_robin_weight = ACC100_QMGR_RR;
+ conf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_ul_4g[i].round_robin_weight = ACC100_QMGR_RR;
+ conf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_dl_5g[i].round_robin_weight = ACC100_QMGR_RR;
+ conf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
+ conf.arb_ul_5g[i].round_robin_weight = ACC100_QMGR_RR;
+ }
+
+ conf.input_pos_llr_1_bit = true;
+ conf.output_pos_llr_1_bit = true;
+ conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */
+
+ conf.q_ul_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
+ conf.q_ul_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
+ conf.q_ul_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
+ conf.q_ul_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
+ conf.q_dl_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
+ conf.q_dl_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
+ conf.q_dl_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
+ conf.q_dl_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
+ conf.q_ul_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
+ conf.q_ul_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
+ conf.q_ul_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
+ conf.q_ul_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
+ conf.q_dl_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
+ conf.q_dl_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
+ conf.q_dl_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
+ conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
+
+ /* setup PF with configuration information */
+ ret = rte_acc101_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC101 PF for bbdev %s",
+ info->dev_name);
+ }
#endif
/* Let's refresh this now this is configured */
rte_bbdev_info_get(dev_id, info);
diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
index d233e42..2e3c43f 100644
--- a/drivers/baseband/acc100/rte_acc100_cfg.h
+++ b/drivers/baseband/acc100/rte_acc100_cfg.h
@@ -106,6 +106,23 @@ struct rte_acc100_conf {
int
rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
+/**
+ * Configure a ACC101 device
+ *
+ * @param dev_name
+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ * It can also be retrieved for a bbdev device from the dev_name field in the
+ * rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ * Configuration to apply to ACC101 HW.
+ *
+ * @return
+ * Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index daf2ce0..b03cedc 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
+
+
+/* Initial configuration of a ACC101 device prior to running configure() */
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc101_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc100_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+
+ /* PCIe Bridge configuration */
+ acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
+ for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
+ acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
+
+ /* Prevent blocking AXI read on BRESP for AXI Write */
+ address = HwPfPcieGpexAxiPioControl;
+ value = ACC101_CFG_PCI_AXI;
+ acc100_reg_write(d, address, value);
+
+ /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* Set the default 5GDL DMA configuration */
+ acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
+
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC101_CLOCK_GATING_EN;
+ acc100_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC101_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc100_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC101_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc100_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ address = HWPfDmaConfig1Reg;
+ int alen_r = 0xF;
+ int alen_w = 0x7;
+ value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
+ acc100_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc100_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_1;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_2;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_3;
+ acc100_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC101_CFG_QMGR_HI_P;
+ acc100_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_4G;
+ template_idx <= ACC101_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_5G;
+ template_idx <= ACC101_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg +
+ ACC101_ENGINE_OFFSET * template_idx;
+ status = (acc100_reg_read(d, address) >> 4) & 0xF;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc100_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc100_reg_write(d, address, 0);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ printf("Number of 5GUL engines %d\n", numEngines);
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_4G;
+ template_idx <= ACC101_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_5G;
+ template_idx <= ACC101_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ address = HWPfQmgrGrpFunction0;
+ value = 0;
+ for (qg_idx = 0; qg_idx < 8; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc]<<(qg_idx * 4);
+ }
+ acc100_reg_write(d, address, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC101_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc100_reg_write(d, address, value);
+ }
+ }
+
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC101_BYTES_IN_WORD + qg_idx
+ * ACC101_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc100_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC101_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
+ acc100_reg_write(d, address, value);
+ /* Explicitly releasing AXI after PF Mode and 2 ms */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc100_reg_write(d, address, value);
+
+ /* HARQ DDR Configuration */
+ unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfDmaVfDdrBaseRw + vf_idx
+ * 0x10;
+ value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
+ (ddrSizeInMb - 1);
+ acc100_reg_write(d, address, value);
+ }
+ usleep(ACC101_LONG_WAIT);
+
+ rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
+ return 0;
+}
diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map
index 40604c7..37b850f 100644
--- a/drivers/baseband/acc100/version.map
+++ b/drivers/baseband/acc100/version.map
@@ -6,5 +6,5 @@ EXPERIMENTAL {
global:
rte_acc100_configure;
-
+ rte_acc101_configure;
};
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (2 preceding siblings ...)
2022-04-27 18:17 ` [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-04-27 18:17 ` Nicolas Chautru
2022-05-08 13:44 ` Tom Rix
2022-04-27 18:17 ` [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
` (3 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-04-27 18:17 UTC (permalink / raw)
To: dev, gakhil
Cc: trix, thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand, Nicolas Chautru
Ensure the performance monitor is restarted in case this
is reset after VF FLR.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++
drivers/baseband/acc100/rte_acc100_pmd.h | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index b03cedc..b588f5f 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -263,6 +263,10 @@
& 0xF;
}
+ /* Start Pmon */
+ acc100_reg_write(d, reg_addr->pmon_ctrl_a, 0x2);
+ acc100_reg_write(d, reg_addr->pmon_ctrl_b, 0x2);
+
/* Read PF mode */
if (d->pf_device) {
reg_mode = acc100_reg_read(d, HWPfHiPfMode);
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index 6438031..f126cc0 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -475,6 +475,8 @@ struct acc100_registry_addr {
unsigned int depth_log1_offset;
unsigned int qman_group_func;
unsigned int ddr_range;
+ unsigned int pmon_ctrl_a;
+ unsigned int pmon_ctrl_b;
};
/* Structure holding registry addresses for PF */
@@ -504,6 +506,8 @@ struct acc100_registry_addr {
.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
.qman_group_func = HWPfQmgrGrpFunction0,
.ddr_range = HWPfDmaVfDdrBaseRw,
+ .pmon_ctrl_a = HWPfPermonACntrlRegVf,
+ .pmon_ctrl_b = HWPfPermonBCntrlRegVf,
};
/* Structure holding registry addresses for VF */
@@ -533,6 +537,8 @@ struct acc100_registry_addr {
.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
.qman_group_func = HWVfQmgrGrpFunction0Vf,
.ddr_range = HWVfDmaDdrBaseRangeRoVf,
+ .pmon_ctrl_a = HWVfPmACntrlRegVf,
+ .pmon_ctrl_b = HWVfPmBCntrlRegVf,
};
/* Structure associated with each queue. */
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (3 preceding siblings ...)
2022-04-27 18:17 ` [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD Nicolas Chautru
@ 2022-04-27 18:17 ` Nicolas Chautru
2022-05-08 13:55 ` Tom Rix
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (2 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-04-27 18:17 UTC (permalink / raw)
To: dev, gakhil
Cc: trix, thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand, Nicolas Chautru
Catch exception in PMD in case of invalid input parameter.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index b588f5f..a13966c 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1241,6 +1241,8 @@
return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
}
/* LBRM case - includes a division by N */
+ if (unlikely(z_c == 0))
+ return 0;
if (rv_index == 1)
return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
/ n) * z_c;
@@ -1916,6 +1918,10 @@ static inline uint32_t hq_index(uint32_t offset)
/* Soft output */
if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
+ if (op->turbo_dec.soft_output.data == 0) {
+ rte_bbdev_log(ERR, "Soft output is not defined");
+ return -1;
+ }
if (check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_EQUALIZER))
*s_out_length = e;
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
2022-04-27 18:16 ` [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-08 13:02 ` Tom Rix
2022-05-09 21:23 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Tom Rix @ 2022-05-08 13:02 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand
This is a good start reusing code, but I think it needs to do more reuse.
These cards should be very close and likely represent a family of cards.
On 4/27/22 11:16 AM, Nicolas Chautru wrote:
> Support for ACC101 as a derivative of ACC100.
> Reusing existing code when possible.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> doc/guides/bbdevs/acc101.rst | 237 +++++++++++++++++++++++++++++++
> doc/guides/bbdevs/features/acc101.ini | 13 ++
> doc/guides/bbdevs/index.rst | 1 +
> doc/guides/rel_notes/release_22_07.rst | 4 +
> drivers/baseband/acc100/rte_acc100_pmd.c | 194 ++++++++++++++++++++++++-
> drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
> drivers/baseband/acc100/rte_acc101_pmd.h | 61 ++++++++
> 7 files changed, 511 insertions(+), 5 deletions(-)
> create mode 100644 doc/guides/bbdevs/acc101.rst
> create mode 100644 doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
>
> diff --git a/doc/guides/bbdevs/acc101.rst b/doc/guides/bbdevs/acc101.rst
> new file mode 100644
> index 0000000..46c310b
> --- /dev/null
> +++ b/doc/guides/bbdevs/acc101.rst
> @@ -0,0 +1,237 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> + Copyright(c) 2020 Intel Corporation
> +
> +Intel(R) ACC101 5G/4G FEC Poll Mode Driver
> +==========================================
> +
> +The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an
> +implementation of a VRAN FEC wireless acceleration function.
> +This device is also known as Mount Cirrus.
> +This is a follow-up to Mount Bryce (ACC100) and includes fixes, improved
> +feature set for error scenarios and performance capacity increase.
includes fixes, better error handling and increased performance.
A quick look at acc100.rst and the bulk of acc101.rst looks the same.
Consider a user of the acc100 is upgrading to acc101, they will
want to know what is the same and what has changed and test accordingly.
These two documents should be combined.
> +
> +Features
> +--------
> +
> +ACC101 5G/4G FEC PMD supports the following features:
> +
> +- LDPC Encode in the DL (5GNR)
> +- LDPC Decode in the UL (5GNR)
> +- Turbo Encode in the DL (4G)
> +- Turbo Decode in the UL (4G)
> +- 16 VFs per PF (physical device)
> +- Maximum of 128 queues per VF
> +- PCIe Gen-3 x16 Interface
> +- MSI
> +- SR-IOV
> +
> +ACC101 5G/4G FEC PMD supports the following BBDEV capabilities:
> +
> +* For the LDPC encode operation:
> + - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
> + - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass
> + - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS`` : if set then bypass interleaver
> +
> +* For the LDPC decode operation:
> + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
> + - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination
> + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding
> + - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
> + - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits
> + - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
> + - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION`` : supports compression of the HARQ input/output
> + - ``RTE_BBDEV_LDPC_LLR_COMPRESSION`` : supports LLR input compression
> +
> +* For the turbo encode operation:
> + - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
> + - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass
> + - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts
> + - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` : set to bypass RV index
> + - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` : supports scatter-gather for input/output data
> +
> +* For the turbo decode operation:
> + - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)
> + - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave
> + - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts
> + - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported
> + - ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN`` : set if positive LLR encoder i/p is supported
> + - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding
> + - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP`` : option to drop the code block CRC after decoding
> + - ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` : set early termination feature
> + - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
> + - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity
> +
> +Installation
> +------------
> +
> +Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
> +
> +DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
> +The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
> +hugepage configuration of a server may be examined using:
> +
> +.. code-block:: console
> +
> + grep Huge* /proc/meminfo
> +
> +
> +Initialization
> +--------------
> +
> +When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
> +
> +.. code-block:: console
> +
> + sudo lspci -vd8086:57c4
> +
> +The physical and virtual functions are compatible with Linux UIO drivers:
> +``vfio`` and ``igb_uio``. However, in order to work the ACC101 5G/4G
> +FEC device first needs to be bound to one of these linux drivers through DPDK.
> +
> +
> +Bind PF UIO driver(s)
> +~~~~~~~~~~~~~~~~~~~~~
> +
> +Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
> +``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
> +
> +The igb_uio driver may be bound to the PF PCI device using one of two methods:
> +
> +
> +1. PCI functions (physical or virtual, depending on the use case) can be bound to
> +the UIO driver by repeating this command for every function.
> +
> +.. code-block:: console
> +
> + cd <dpdk-top-level-directory>
> + insmod ./build/kmod/igb_uio.ko
> + echo "8086 57c4" > /sys/bus/pci/drivers/igb_uio/new_id
> + lspci -vd8086:57c4
> +
> +
> +2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
> +
> +.. code-block:: console
> +
> + cd <dpdk-top-level-directory>
> + ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
> +
> +where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:57c4
> +
> +
> +In a similar way the ACC101 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
> +
> +
> +Enable Virtual Functions
> +~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +Now, it should be visible in the printouts that PCI PF is under igb_uio control
> +"``Kernel driver in use: igb_uio``"
> +
> +To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
> +
> +.. code-block:: console
> +
> + cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
> +
> + where 0000\:<b>\:<d>.<f> is the PCI device ID
> +
> +
> +To enable VFs via igb_uio, echo the number of virtual functions intended to
> +enable to ``max_vfs`` file..
> +
> +.. code-block:: console
> +
> + echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
> +
> +
> +Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
> +way it was done with the physical function previously.
> +
> +Enabling SR-IOV via vfio driver is pretty much the same, except that the file
> +name is different:
> +
> +.. code-block:: console
> +
> + echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
> +
> +
> +Configure the VFs through PF
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +The PCI virtual functions must be configured before working or getting assigned
> +to VMs/Containers. The configuration involves allocating the number of hardware
> +queues, priorities, load balance, bandwidth and other settings necessary for the
> +device to perform FEC functions.
> +
> +This configuration needs to be executed at least once after reboot or PCI FLR and can
> +be achieved by using the function ``acc101_configure()``, which sets up the
> +parameters defined in ``acc100_conf`` structure.
> +
> +Test Application
> +----------------
> +
> +BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
> +the functionality of ACC101 5G/4G FEC encode and decode, depending on the device's
> +capabilities. The test application is located under app->test-bbdev folder and has the
> +following options:
> +
> +.. code-block:: console
> +
> + "-p", "--testapp-path": specifies path to the bbdev test app.
> + "-e", "--eal-params" : EAL arguments which are passed to the test app.
> + "-t", "--timeout" : Timeout in seconds (default=300).
> + "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
> + "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
> + "-n", "--num-ops" : Number of operations to process on device (default=32).
> + "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
> + "-s", "--snr" : SNR in dB used when generating LLRs for bler tests.
> + "-s", "--iter_max" : Number of iterations for LDPC decoder.
> + "-l", "--num-lcores" : Number of lcores to run (default=16).
> + "-i", "--init-device" : Initialise PF device with default values.
> +
> +
> +To execute the test application tool using simple decode or encode data,
> +type one of the following:
> +
> +.. code-block:: console
> +
> + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
> + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
> +
> +
> +The test application ``test-bbdev.py``, supports the ability to configure the PF device with
> +a default set of values, if the "-i" or "- -init-device" option is included. The default values
> +are defined in test_bbdev_perf.c.
> +
> +
> +Test Vectors
> +~~~~~~~~~~~~
> +
> +In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
> +a range of additional tests under the test_vectors folder, which may be useful. The results
> +of these tests will depend on the ACC101 5G/4G FEC capabilities which may cause some
> +testcases to be skipped, but no failure should be reported.
> +
> +
> +Alternate Baseband Device configuration tool
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +On top of the embedded configuration feature supported in test-bbdev using "- -init-device"
> +option mentioned above, there is also a tool available to perform that device configuration
> +using a companion application.
> +The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF
> +and not only limited to the PF as captured above.
> +
> +See for more details: https://github.com/intel/pf-bb-config
> +
> +Specifically for the BBDEV ACC101 PMD, the command below can be used:
> +
> +.. code-block:: console
> +
> + ./pf_bb_config ACC101 -c acc101/acc101_config_4vf_4g5g.cfg
> + ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -l 1 -v ./ldpc_dec_default.data
> \ No newline at end of file
> diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
> new file mode 100644
> index 0000000..0e2c21a
> --- /dev/null
> +++ b/doc/guides/bbdevs/features/acc101.ini
> @@ -0,0 +1,13 @@
> +;
> +; Supported features of the 'acc101' bbdev driver.
> +;
> +; Refer to default.ini for the full list of available PMD features.
> +;
> +[Features]
> +Turbo Decoder (4G) = Y
> +Turbo Encoder (4G) = Y
> +LDPC Decoder (5G) = Y
> +LDPC Encoder (5G) = Y
> +LLR/HARQ Compression = Y
> +External DDR Access = Y
> +HW Accelerated = Y
This is the same as acc100.ini, why do we need 2 ?
> diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
> index cedd706..e76883c 100644
> --- a/doc/guides/bbdevs/index.rst
> +++ b/doc/guides/bbdevs/index.rst
> @@ -14,4 +14,5 @@ Baseband Device Drivers
> fpga_lte_fec
> fpga_5gnr_fec
> acc100
> + acc101
> la12xx
> diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
> index 42a5f2d..ef9906b 100644
> --- a/doc/guides/rel_notes/release_22_07.rst
> +++ b/doc/guides/rel_notes/release_22_07.rst
> @@ -55,6 +55,10 @@ New Features
> Also, make sure to start the actual text at the margin.
> =======================================================
>
> +* **Added Intel ACC101 baseband PMD.**
> +
> + * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
> + * See the :doc:`../bbdevs/acc101` for more details.
>
> Removed Items
> -------------
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index de7e4bc..fca27ef 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -22,6 +22,7 @@
> #include <rte_bbdev.h>
> #include <rte_bbdev_pmd.h>
> #include "rte_acc100_pmd.h"
> +#include "rte_acc101_pmd.h"
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
> @@ -1286,6 +1287,12 @@
> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> }
>
> +static inline bool
> +is_acc100(struct acc100_queue *q)
> +{
> + return (q->d->device_variant == ACC100_VARIANT);
> +}
> +
> /* Fill in a frame control word for LDPC decoding. */
> static inline void
> acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> @@ -1412,6 +1419,139 @@
> }
> }
>
> +/* Convert offset to harq index for harq_layout structure */
> +static inline uint32_t hq_index(uint32_t offset)
> +{
> + return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
> +}
> +
> +/* Fill in a frame control word for LDPC decoding for ACC101 */
> +static inline void
> +acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> + union acc100_harq_layout_data *harq_layout)
This looks extremely similar to the acc100*, why isn't this combined ?
> +{
> + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
> + uint32_t harq_index;
> + uint32_t l;
> +
> + fcw->qm = op->ldpc_dec.q_m;
> + fcw->nfiller = op->ldpc_dec.n_filler;
> + fcw->BG = (op->ldpc_dec.basegraph - 1);
> + fcw->Zc = op->ldpc_dec.z_c;
> + fcw->ncb = op->ldpc_dec.n_cb;
> + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
> + op->ldpc_dec.rv_index);
> + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
> + fcw->rm_e = op->ldpc_dec.cb_params.e;
> + else
> + fcw->rm_e = (op->ldpc_dec.tb_params.r <
> + op->ldpc_dec.tb_params.cab) ?
> + op->ldpc_dec.tb_params.ea :
> + op->ldpc_dec.tb_params.eb;
> +
> + if (unlikely(check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
> + (op->ldpc_dec.harq_combined_input.length == 0))) {
> + rte_bbdev_log(WARNING, "Null HARQ input size provided");
> + /* Disable HARQ input in that case to carry forward */
> + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> + }
> +
> + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
> + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
> + fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
> + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_DECODE_BYPASS);
> + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
> + if (op->ldpc_dec.q_m == 1) {
> + fcw->bypass_intlv = 1;
> + fcw->qm = 2;
> + }
> + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_LLR_COMPRESSION);
> + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
> + if (fcw->hcin_en > 0) {
> + harq_in_length = op->ldpc_dec.harq_combined_input.length;
> + if (fcw->hcin_decomp_mode > 0)
> + harq_in_length = harq_in_length * 8 / 6;
> + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
> + - op->ldpc_dec.n_filler);
> + /* Alignment on next 64B - Already enforced from HC output */
> + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> + fcw->hcin_size0 = harq_in_length;
> + fcw->hcin_offset = 0;
> + fcw->hcin_size1 = 0;
> + } else {
> + fcw->hcin_size0 = 0;
> + fcw->hcin_offset = 0;
> + fcw->hcin_size1 = 0;
> + }
> +
> + fcw->itmax = op->ldpc_dec.iter_max;
> + fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
> + fcw->synd_precoder = fcw->itstop;
> + /*
> + * These are all implicitly set
> + * fcw->synd_post = 0;
> + * fcw->so_en = 0;
> + * fcw->so_bypass_rm = 0;
> + * fcw->so_bypass_intlv = 0;
> + * fcw->dec_convllr = 0;
> + * fcw->hcout_convllr = 0;
> + * fcw->hcout_size1 = 0;
> + * fcw->so_it = 0;
> + * fcw->hcout_offset = 0;
> + * fcw->negstop_th = 0;
> + * fcw->negstop_it = 0;
> + * fcw->negstop_en = 0;
> + * fcw->gain_i = 1;
> + * fcw->gain_h = 1;
> + */
> + if (fcw->hcout_en > 0) {
> + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
> + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
> + k0_p = (fcw->k0 > parity_offset) ?
> + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
> + ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
> + harq_out_length = (uint16_t) fcw->hcin_size0;
> + harq_out_length = RTE_MAX(harq_out_length, l);
> + /* Cannot exceed the pruned Ncb circular buffer */
> + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> + /* Alignment on next 64B */
> + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> + fcw->hcout_size0 = harq_out_length;
> + fcw->hcout_size1 = 0;
> + fcw->hcout_offset = 0;
> + harq_layout[harq_index].offset = fcw->hcout_offset;
> + harq_layout[harq_index].size0 = fcw->hcout_size0;
> + } else {
> + fcw->hcout_size0 = 0;
> + fcw->hcout_size1 = 0;
> + fcw->hcout_offset = 0;
> + }
> +}
> +
> +static inline void
> +acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> + union acc100_harq_layout_data *harq_layout, struct acc100_queue *q)
> +{
> + if (is_acc100(q))
consider having a function table in the private data so the call can be
made without this if-check
> + return acc100_fcw_ld_fill(op, fcw, harq_layout);
> + else
> + return acc101_fcw_ld_fill(op, fcw, harq_layout);
> +}
> +
> +
> /**
> * Fills descriptor with data pointers of one block type.
> *
> @@ -2960,7 +3100,7 @@
> struct acc100_fcw_ld *fcw;
> uint32_t seg_total_left;
> fcw = &desc->req.fcw_ld;
> - acc100_fcw_ld_fill(op, fcw, harq_layout);
> + acc10x_fcw_ld_fill(op, fcw, harq_layout, q);
>
> /* Special handling when overusing mbuf */
> if (fcw->rm_e < ACC100_MAX_E_MBUF)
> @@ -3027,7 +3167,7 @@
> desc = q->ring_addr + desc_idx;
> uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
> union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
> - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
> + acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q);
>
> input = op->ldpc_dec.input.data;
> h_output_head = h_output = op->ldpc_dec.hard_output.data;
> @@ -4139,9 +4279,17 @@
> dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
> dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
>
> - ((struct acc100_device *) dev->data->dev_private)->pf_device =
> - !strcmp(drv->driver.name,
> - RTE_STR(ACC100PF_DRIVER_NAME));
> + if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) ||
> + (!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) {
> + ((struct acc100_device *) dev->data->dev_private)->pf_device =
> + !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
> + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
> + } else {
> + ((struct acc100_device *) dev->data->dev_private)->pf_device =
> + !strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME));
> + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
> + }
> +
> ((struct acc100_device *) dev->data->dev_private)->mmio_base =
> pci_dev->mem_resource[0].addr;
>
> @@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
> RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);
> RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);
>
> +/* ACC101 PCI PF address map */
> +static struct rte_pci_id pci_id_acc101_pf_map[] = {
> + {
> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID)
> + },
> + {.device_id = 0},
> +};
> +
> +/* ACC101 PCI VF address map */
> +static struct rte_pci_id pci_id_acc101_vf_map[] = {
> + {
> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID)
> + },
> + {.device_id = 0},
> +};
> +
> +
> +static struct rte_pci_driver acc101_pci_pf_driver = {
> + .probe = acc100_pci_probe,
> + .remove = acc100_pci_remove,
> + .id_table = pci_id_acc101_pf_map,
> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING
> +};
> +
> +static struct rte_pci_driver acc101_pci_vf_driver = {
> + .probe = acc100_pci_probe,
> + .remove = acc100_pci_remove,
> + .id_table = pci_id_acc101_vf_map,
> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING
> +};
> +
> +RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver);
> +RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);
> +RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);
> +RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);
> +
> /*
> * Workaround implementation to fix the power on status of some 5GUL engines
> * This requires DMA permission if ported outside DPDK
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
> index cbcece2..6438031 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> @@ -22,6 +22,9 @@
> #define rte_bbdev_log_debug(fmt, ...)
> #endif
>
> +#define ACC100_VARIANT 0
> +#define ACC101_VARIANT 1
> +
> /* ACC100 PF and VF driver names */
> #define ACC100PF_DRIVER_NAME intel_acc100_pf
> #define ACC100VF_DRIVER_NAME intel_acc100_vf
> @@ -67,6 +70,8 @@
> #define ACC100_HARQ_LAYOUT (64*1024*1024)
> /* Assume offset for HARQ in memory */
> #define ACC100_HARQ_OFFSET (32*1024)
> +#define ACC100_HARQ_OFFSET_SHIFT 15
> +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
> /* Mask used to calculate an index in an Info Ring array (not a byte offset) */
> #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
> /* Number of Virtual Functions ACC100 supports */
> @@ -590,6 +595,7 @@ struct acc100_device {
> uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
> bool pf_device; /**< True if this is a PF ACC100 device */
> bool configured; /**< True if this ACC100 device is configured */
> + uint16_t device_variant; /**< Device variant */
this is not needed, check the pci id
> };
>
> /**
> diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h
> new file mode 100644
> index 0000000..efab400
> --- /dev/null
> +++ b/drivers/baseband/acc100/rte_acc101_pmd.h
New files need license, copyrights.
This file looks very similar to rte_acc100_pmd.h
The common parts should be in only one file, maybe a rte_acc10x_pmd.h
> @@ -0,0 +1,61 @@
> +/* ACC101 PF and VF driver names */
> +#define ACC101PF_DRIVER_NAME intel_acc101_pf
> +#define ACC101VF_DRIVER_NAME intel_acc101_vf
this maybe changes to intel_acc10x_pr/vf ?
Tom
> +
> +/* ACC101 PCI vendor & device IDs */
> +#define RTE_ACC101_VENDOR_ID (0x8086)
> +#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
> +#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
> +
> +/* Define as 1 to use only a single FEC engine */
> +#ifndef RTE_ACC101_SINGLE_FEC
> +#define RTE_ACC101_SINGLE_FEC 0
> +#endif
> +
> +/* Values used in writing to the registers */
> +#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
> +
> +/* Number of Virtual Functions ACC101 supports */
> +#define ACC101_NUM_VFS 16
> +#define ACC101_NUM_QGRPS 8
> +#define ACC101_NUM_AQS 16
> +/* All ACC101 Registers alignment are 32bits = 4B */
> +#define ACC101_BYTES_IN_WORD 4
> +
> +#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
> +#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
> +#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS Mon */
> +#define ACC101_TMPL_PRI_0 0x03020100
> +#define ACC101_TMPL_PRI_1 0x07060504
> +#define ACC101_TMPL_PRI_2 0x0b0a0908
> +#define ACC101_TMPL_PRI_3 0x0f0e0d0c
> +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
> +
> +#define ACC101_NUM_TMPL 32
> +/* Mapping of signals for the available engines */
> +#define ACC101_SIG_UL_5G 0
> +#define ACC101_SIG_UL_5G_LAST 8
> +#define ACC101_SIG_DL_5G 13
> +#define ACC101_SIG_DL_5G_LAST 15
> +#define ACC101_SIG_UL_4G 16
> +#define ACC101_SIG_UL_4G_LAST 19
> +#define ACC101_SIG_DL_4G 27
> +#define ACC101_SIG_DL_4G_LAST 31
> +#define ACC101_NUM_ACCS 5
> +#define ACC101_PF_VAL 2
> +
> +/* ACC101 Configuration */
> +#define ACC101_CFG_DMA_ERROR 0x3D7
> +#define ACC101_CFG_AXI_CACHE 0x11
> +#define ACC101_CFG_QMGR_HI_P 0x0F0F
> +#define ACC101_CFG_PCI_AXI 0xC003
> +#define ACC101_CFG_PCI_BRIDGE 0x40006033
> +#define ACC101_ENGINE_OFFSET 0x1000
> +#define ACC101_LONG_WAIT 1000
> +#define ACC101_GPEX_AXIMAP_NUM 17
> +#define ACC101_CLOCK_GATING_EN 0x30000
> +#define ACC101_DMA_INBOUND 0x104
> +/* DDR Size per VF - 512MB by default
> + * Can be increased up to 4 GB with single PF/VF
> + */
> +#define ACC101_HARQ_DDR (512 * 1)
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 2/5] baseband/acc100: modify validation code for ACC101
2022-04-27 18:17 ` [PATCH v2 2/5] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-08 13:07 ` Tom Rix
2022-05-09 21:27 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Tom Rix @ 2022-05-08 13:07 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand
On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> The validation requirement is different for the two
> devices.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++----------
> 1 file changed, 28 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index fca27ef..daf2ce0 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -1293,6 +1293,14 @@
> return (q->d->device_variant == ACC100_VARIANT);
> }
>
> +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> +static inline bool
> +validate_op_required(struct acc100_queue *q)
There isn't an #else case so this will fail to build.
This i believe could be another function in private data fops i
suggested in the first patch.
Tom
> +{
> + return is_acc100(q);
> +}
> +#endif
> +
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF
2022-04-27 18:17 ` [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-05-08 13:38 ` Tom Rix
2022-05-09 21:36 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Tom Rix @ 2022-05-08 13:38 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand
On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> Adding companion function specific to ACC100 and it
> can be called from bbdev-test when running from PF.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> app/test-bbdev/test_bbdev_perf.c | 57 ++++++
> drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
> drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++
> drivers/baseband/acc100/version.map | 2 +-
> 4 files changed, 377 insertions(+), 1 deletion(-)
>
> diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
> index 0fa119a..baf5f6d 100644
> --- a/app/test-bbdev/test_bbdev_perf.c
> +++ b/app/test-bbdev/test_bbdev_perf.c
> @@ -63,6 +63,8 @@
> #define ACC100_QMGR_INVALID_IDX -1
> #define ACC100_QMGR_RR 1
> #define ACC100_QOS_GBR 0
> +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
> +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
A dup from patch 1
> #endif
>
> #define OPS_CACHE_SIZE 256U
> @@ -765,6 +767,61 @@ typedef int (test_case_function)(struct active_device *ad,
> "Failed to configure ACC100 PF for bbdev %s",
> info->dev_name);
> }
> + if ((get_init_device() == true) &&
> + (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME))) {
> + struct rte_acc100_conf conf;
Mixing up acc100 and acc101 ?
If this actually works, combine the two.
> + unsigned int i;
> +
> + printf("Configure ACC101 FEC Driver %s with default values\n",
> + info->drv.driver_name);
> +
> + /* clear default configuration before initialization */
> + memset(&conf, 0, sizeof(struct rte_acc100_conf));
> +
> + /* Always set in PF mode for built-in configuration */
> + conf.pf_mode_en = true;
> + for (i = 0; i < RTE_ACC100_NUM_VFS; ++i) {
> + conf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_dl_4g[i].round_robin_weight = ACC100_QMGR_RR;
> + conf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_ul_4g[i].round_robin_weight = ACC100_QMGR_RR;
> + conf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_dl_5g[i].round_robin_weight = ACC100_QMGR_RR;
> + conf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR;
> + conf.arb_ul_5g[i].round_robin_weight = ACC100_QMGR_RR;
> + }
> +
> + conf.input_pos_llr_1_bit = true;
> + conf.output_pos_llr_1_bit = true;
> + conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */
> +
> + conf.q_ul_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
> + conf.q_ul_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
> + conf.q_ul_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
> + conf.q_ul_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> + conf.q_dl_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
> + conf.q_dl_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
> + conf.q_dl_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
> + conf.q_dl_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> + conf.q_ul_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
> + conf.q_ul_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
> + conf.q_ul_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
> + conf.q_ul_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> + conf.q_dl_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
> + conf.q_dl_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX;
> + conf.q_dl_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS;
> + conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> +
> + /* setup PF with configuration information */
> + ret = rte_acc101_configure(info->dev_name, &conf);
> + TEST_ASSERT_SUCCESS(ret,
> + "Failed to configure ACC101 PF for bbdev %s",
> + info->dev_name);
> + }
> #endif
> /* Let's refresh this now this is configured */
> rte_bbdev_info_get(dev_id, info);
> diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
> index d233e42..2e3c43f 100644
> --- a/drivers/baseband/acc100/rte_acc100_cfg.h
> +++ b/drivers/baseband/acc100/rte_acc100_cfg.h
This file marks its API as experimental though the acc100 has been used
in production for some time.
It is important that the API be stable.
Is this an oversight ?
Or what is needed to stabilize the API ?
> @@ -106,6 +106,23 @@ struct rte_acc100_conf {
> int
> rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
>
> +/**
> + * Configure a ACC101 device
> + *
> + * @param dev_name
> + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
> + * It can also be retrieved for a bbdev device from the dev_name field in the
> + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> + * @param conf
> + * Configuration to apply to ACC101 HW.
> + *
> + * @return
> + * Zero on success, negative value on failure.
> + */
> +__rte_experimental
> +int
> +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf);
I am finding seeing acc100* structs in acc101 function parameters confusing.
Maybe a general renaming of acc100 -> acc10x for the common parts.
Will we have this problem on acc120 or acc200 ?
Maybe shorten everything now to acc
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index daf2ce0..b03cedc 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
> rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
> return 0;
> }
> +
> +
> +/* Initial configuration of a ACC101 device prior to running configure() */
> +int
> +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
> +{
This is very similar to the acc100 configure function.
It would be good if these could be combined.
Tom
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD
2022-04-27 18:17 ` [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD Nicolas Chautru
@ 2022-05-08 13:44 ` Tom Rix
2022-05-09 22:07 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Tom Rix @ 2022-05-08 13:44 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand
On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> Ensure the performance monitor is restarted in case this
> is reset after VF FLR.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++
> drivers/baseband/acc100/rte_acc100_pmd.h | 6 ++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index b03cedc..b588f5f 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -263,6 +263,10 @@
> & 0xF;
> }
>
> + /* Start Pmon */
> + acc100_reg_write(d, reg_addr->pmon_ctrl_a, 0x2);
> + acc100_reg_write(d, reg_addr->pmon_ctrl_b, 0x2);
This looks like an acc100 bug fix, so it should be split from the acc101
pathset.
Where this code is added is fetch_acc100_config, a function that does reads.
Though convenient, this is likely not the best place to put the writes
Tom
> +
> /* Read PF mode */
> if (d->pf_device) {
> reg_mode = acc100_reg_read(d, HWPfHiPfMode);
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
> index 6438031..f126cc0 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> @@ -475,6 +475,8 @@ struct acc100_registry_addr {
> unsigned int depth_log1_offset;
> unsigned int qman_group_func;
> unsigned int ddr_range;
> + unsigned int pmon_ctrl_a;
> + unsigned int pmon_ctrl_b;
> };
>
> /* Structure holding registry addresses for PF */
> @@ -504,6 +506,8 @@ struct acc100_registry_addr {
> .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
> .qman_group_func = HWPfQmgrGrpFunction0,
> .ddr_range = HWPfDmaVfDdrBaseRw,
> + .pmon_ctrl_a = HWPfPermonACntrlRegVf,
> + .pmon_ctrl_b = HWPfPermonBCntrlRegVf,
> };
>
> /* Structure holding registry addresses for VF */
> @@ -533,6 +537,8 @@ struct acc100_registry_addr {
> .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
> .qman_group_func = HWVfQmgrGrpFunction0Vf,
> .ddr_range = HWVfDmaDdrBaseRangeRoVf,
> + .pmon_ctrl_a = HWVfPmACntrlRegVf,
> + .pmon_ctrl_b = HWVfPmBCntrlRegVf,
> };
>
> /* Structure associated with each queue. */
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario
2022-04-27 18:17 ` [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-05-08 13:55 ` Tom Rix
2022-05-09 21:45 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Tom Rix @ 2022-05-08 13:55 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
mingshan.zhang, david.marchand
On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> Catch exception in PMD in case of invalid input parameter.
It is not clear if this is 1 fix or 2.
But it does look like an acc100 fix so it should be split from the
acc101 patchset.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index b588f5f..a13966c 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -1241,6 +1241,8 @@
> return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
> }
> /* LBRM case - includes a division by N */
> + if (unlikely(z_c == 0))
> + return 0;
This check should be moved to earlier, if 'n' is set to 0 in the
statement above, there is div by 0 later
Tom
> if (rv_index == 1)
> return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
> / n) * z_c;
> @@ -1916,6 +1918,10 @@ static inline uint32_t hq_index(uint32_t offset)
>
> /* Soft output */
> if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
> + if (op->turbo_dec.soft_output.data == 0) {
> + rte_bbdev_log(ERR, "Soft output is not defined");
> + return -1;
> + }
> if (check_bit(op->turbo_dec.op_flags,
> RTE_BBDEV_TURBO_EQUALIZER))
> *s_out_length = e;
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
2022-05-08 13:02 ` Tom Rix
@ 2022-05-09 21:23 ` Chautru, Nicolas
2022-05-10 8:52 ` Thomas Monjalon
2022-05-10 11:55 ` Tom Rix
0 siblings, 2 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-09 21:23 UTC (permalink / raw)
To: Tom Rix, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
Hi Tom,
> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Sunday, May 8, 2022 6:03 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
> Subject: Re: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
>
> This is a good start reusing code, but I think it needs to do more reuse.
>
> These cards should be very close and likely represent a family of cards.
>
> On 4/27/22 11:16 AM, Nicolas Chautru wrote:
> > Support for ACC101 as a derivative of ACC100.
> > Reusing existing code when possible.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > doc/guides/bbdevs/acc101.rst | 237
> +++++++++++++++++++++++++++++++
> > doc/guides/bbdevs/features/acc101.ini | 13 ++
> > doc/guides/bbdevs/index.rst | 1 +
> > doc/guides/rel_notes/release_22_07.rst | 4 +
> > drivers/baseband/acc100/rte_acc100_pmd.c | 194
> ++++++++++++++++++++++++-
> > drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
> > drivers/baseband/acc100/rte_acc101_pmd.h | 61 ++++++++
> > 7 files changed, 511 insertions(+), 5 deletions(-)
> > create mode 100644 doc/guides/bbdevs/acc101.rst
> > create mode 100644 doc/guides/bbdevs/features/acc101.ini
> > create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
> >
> > diff --git a/doc/guides/bbdevs/acc101.rst
> > b/doc/guides/bbdevs/acc101.rst new file mode 100644 index
> > 0000000..46c310b
> > --- /dev/null
> > +++ b/doc/guides/bbdevs/acc101.rst
> > @@ -0,0 +1,237 @@
> > +.. SPDX-License-Identifier: BSD-3-Clause
> > + Copyright(c) 2020 Intel Corporation
> > +
> > +Intel(R) ACC101 5G/4G FEC Poll Mode Driver
> > +==========================================
> > +
> > +The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an
> > +implementation of a VRAN FEC wireless acceleration function.
> > +This device is also known as Mount Cirrus.
> > +This is a follow-up to Mount Bryce (ACC100) and includes fixes,
> > +improved feature set for error scenarios and performance capacity increase.
>
> includes fixes, better error handling and increased performance.
>
> A quick look at acc100.rst and the bulk of acc101.rst looks the same.
>
> Consider a user of the acc100 is upgrading to acc101, they will
>
> want to know what is the same and what has changed and test accordingly.
>
> These two documents should be combined.
>
Well in term of documentation, for the users it helps to be able to follow steps as they are for a given variant.
As opposed to have to have multiple options through the document when using ACC100 vs ACC101.
Except if they are other objections, I would see this more useful for the user as is and less source of errors.
> > +
> > +Features
> > +--------
> > +
> > +ACC101 5G/4G FEC PMD supports the following features:
> > +
> > +- LDPC Encode in the DL (5GNR)
> > +- LDPC Decode in the UL (5GNR)
> > +- Turbo Encode in the DL (4G)
> > +- Turbo Decode in the UL (4G)
> > +- 16 VFs per PF (physical device)
> > +- Maximum of 128 queues per VF
> > +- PCIe Gen-3 x16 Interface
> > +- MSI
> > +- SR-IOV
> > +
> > +ACC101 5G/4G FEC PMD supports the following BBDEV capabilities:
> > +
> > +* For the LDPC encode operation:
> > + - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
> > + - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match
> bypass
> > + - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS`` : if set then bypass
> > +interleaver
> > +
> > +* For the LDPC decode operation:
> > + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
> > + - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early
> termination
> > + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits
> appended while decoding
> > + - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for
> HARQ combining
> > + - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input
> for HARQ combining
> > + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ
> memory input is internal
> > + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ
> memory output is internal
> > + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` :
> loopback data to/from HARQ memory
> > + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ
> memory includes the fillers bits
> > + - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER`` : supports scatter-gather
> for input/output data
> > + - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION`` : supports
> compression of the HARQ input/output
> > + - ``RTE_BBDEV_LDPC_LLR_COMPRESSION`` : supports LLR input
> > +compression
> > +
> > +* For the turbo encode operation:
> > + - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to
> CB(s)
> > + - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match
> bypass
> > + - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue
> interrupts
> > + - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` : set to bypass RV index
> > + - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` : supports
> > +scatter-gather for input/output data
> > +
> > +* For the turbo decode operation:
> > + - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)
> > + - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock
> de-interleave
> > + - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue
> interrupts
> > + - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder
> i/p is supported
> > + - ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN`` : set if positive LLR encoder
> i/p is supported
> > + - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits
> appended while decoding
> > + - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP`` : option to drop the code
> block CRC after decoding
> > + - ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` : set early termination
> feature
> > + - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather
> for input/output data
> > + - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration
> > +granularity
> > +
> > +Installation
> > +------------
> > +
> > +Section 3 of the DPDK manual provides instructions on installing and
> compiling DPDK.
> > +
> > +DPDK requires hugepages to be configured as detailed in section 2 of the
> DPDK manual.
> > +The bbdev test application has been tested with a configuration 40 x
> > +1GB hugepages. The hugepage configuration of a server may be examined
> using:
> > +
> > +.. code-block:: console
> > +
> > + grep Huge* /proc/meminfo
> > +
> > +
> > +Initialization
> > +--------------
> > +
> > +When the device first powers up, its PCI Physical Functions (PF) can be listed
> through this command:
> > +
> > +.. code-block:: console
> > +
> > + sudo lspci -vd8086:57c4
> > +
> > +The physical and virtual functions are compatible with Linux UIO drivers:
> > +``vfio`` and ``igb_uio``. However, in order to work the ACC101 5G/4G
> > +FEC device first needs to be bound to one of these linux drivers through
> DPDK.
> > +
> > +
> > +Bind PF UIO driver(s)
> > +~~~~~~~~~~~~~~~~~~~~~
> > +
> > +Install the DPDK igb_uio driver, bind it with the PF PCI device ID
> > +and use ``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK
> UIO driver.
> > +
> > +The igb_uio driver may be bound to the PF PCI device using one of two
> methods:
> > +
> > +
> > +1. PCI functions (physical or virtual, depending on the use case) can
> > +be bound to the UIO driver by repeating this command for every function.
> > +
> > +.. code-block:: console
> > +
> > + cd <dpdk-top-level-directory>
> > + insmod ./build/kmod/igb_uio.ko
> > + echo "8086 57c4" > /sys/bus/pci/drivers/igb_uio/new_id
> > + lspci -vd8086:57c4
> > +
> > +
> > +2. Another way to bind PF with DPDK UIO driver is by using the
> > +``dpdk-devbind.py`` tool
> > +
> > +.. code-block:: console
> > +
> > + cd <dpdk-top-level-directory>
> > + ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
> > +
> > +where the PCI device ID (example: 0000:06:00.0) is obtained using
> > +lspci -vd8086:57c4
> > +
> > +
> > +In a similar way the ACC101 5G/4G FEC PF may be bound with vfio-pci as any
> PCIe device.
> > +
> > +
> > +Enable Virtual Functions
> > +~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +Now, it should be visible in the printouts that PCI PF is under
> > +igb_uio control "``Kernel driver in use: igb_uio``"
> > +
> > +To show the number of available VFs on the device, read ``sriov_totalvfs``
> file..
> > +
> > +.. code-block:: console
> > +
> > + cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
> > +
> > + where 0000\:<b>\:<d>.<f> is the PCI device ID
> > +
> > +
> > +To enable VFs via igb_uio, echo the number of virtual functions
> > +intended to enable to ``max_vfs`` file..
> > +
> > +.. code-block:: console
> > +
> > + echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
> > +
> > +
> > +Afterwards, all VFs must be bound to appropriate UIO drivers as
> > +required, same way it was done with the physical function previously.
> > +
> > +Enabling SR-IOV via vfio driver is pretty much the same, except that
> > +the file name is different:
> > +
> > +.. code-block:: console
> > +
> > + echo <num-of-vfs> >
> > + /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
> > +
> > +
> > +Configure the VFs through PF
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +The PCI virtual functions must be configured before working or
> > +getting assigned to VMs/Containers. The configuration involves
> > +allocating the number of hardware queues, priorities, load balance,
> > +bandwidth and other settings necessary for the device to perform FEC
> functions.
> > +
> > +This configuration needs to be executed at least once after reboot or
> > +PCI FLR and can be achieved by using the function
> > +``acc101_configure()``, which sets up the parameters defined in
> ``acc100_conf`` structure.
> > +
> > +Test Application
> > +----------------
> > +
> > +BBDEV provides a test application, ``test-bbdev.py`` and range of
> > +test data for testing the functionality of ACC101 5G/4G FEC encode
> > +and decode, depending on the device's capabilities. The test
> > +application is located under app->test-bbdev folder and has the following
> options:
> > +
> > +.. code-block:: console
> > +
> > + "-p", "--testapp-path": specifies path to the bbdev test app.
> > + "-e", "--eal-params" : EAL arguments which are passed to the test app.
> > + "-t", "--timeout" : Timeout in seconds (default=300).
> > + "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
> > + "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-
> bbdev/test_vectors/bbdev_null.data).
> > + "-n", "--num-ops" : Number of operations to process on device
> (default=32).
> > + "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
> > + "-s", "--snr" : SNR in dB used when generating LLRs for bler tests.
> > + "-s", "--iter_max" : Number of iterations for LDPC decoder.
> > + "-l", "--num-lcores" : Number of lcores to run (default=16).
> > + "-i", "--init-device" : Initialise PF device with default values.
> > +
> > +
> > +To execute the test application tool using simple decode or encode
> > +data, type one of the following:
> > +
> > +.. code-block:: console
> > +
> > + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
> > + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
> > +
> > +
> > +The test application ``test-bbdev.py``, supports the ability to
> > +configure the PF device with a default set of values, if the "-i" or
> > +"- -init-device" option is included. The default values are defined in
> test_bbdev_perf.c.
> > +
> > +
> > +Test Vectors
> > +~~~~~~~~~~~~
> > +
> > +In addition to the simple LDPC decoder and LDPC encoder tests, bbdev
> > +also provides a range of additional tests under the test_vectors
> > +folder, which may be useful. The results of these tests will depend
> > +on the ACC101 5G/4G FEC capabilities which may cause some testcases to be
> skipped, but no failure should be reported.
> > +
> > +
> > +Alternate Baseband Device configuration tool
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +On top of the embedded configuration feature supported in test-bbdev using
> "- -init-device"
> > +option mentioned above, there is also a tool available to perform
> > +that device configuration using a companion application.
> > +The ``pf_bb_config`` application notably enables then to run
> > +bbdev-test from the VF and not only limited to the PF as captured above.
> > +
> > +See for more details: https://github.com/intel/pf-bb-config
> > +
> > +Specifically for the BBDEV ACC101 PMD, the command below can be used:
> > +
> > +.. code-block:: console
> > +
> > + ./pf_bb_config ACC101 -c acc101/acc101_config_4vf_4g5g.cfg
> > + ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -l 1 -v
> > + ./ldpc_dec_default.data
> > \ No newline at end of file
> > diff --git a/doc/guides/bbdevs/features/acc101.ini
> > b/doc/guides/bbdevs/features/acc101.ini
> > new file mode 100644
> > index 0000000..0e2c21a
> > --- /dev/null
> > +++ b/doc/guides/bbdevs/features/acc101.ini
> > @@ -0,0 +1,13 @@
> > +;
> > +; Supported features of the 'acc101' bbdev driver.
> > +;
> > +; Refer to default.ini for the full list of available PMD features.
> > +;
> > +[Features]
> > +Turbo Decoder (4G) = Y
> > +Turbo Encoder (4G) = Y
> > +LDPC Decoder (5G) = Y
> > +LDPC Encoder (5G) = Y
> > +LLR/HARQ Compression = Y
> > +External DDR Access = Y
> > +HW Accelerated = Y
> This is the same as acc100.ini, why do we need 2 ?
This is a different product, needs to be consistent.
> > diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
> > index cedd706..e76883c 100644
> > --- a/doc/guides/bbdevs/index.rst
> > +++ b/doc/guides/bbdevs/index.rst
> > @@ -14,4 +14,5 @@ Baseband Device Drivers
> > fpga_lte_fec
> > fpga_5gnr_fec
> > acc100
> > + acc101
> > la12xx
> > diff --git a/doc/guides/rel_notes/release_22_07.rst
> > b/doc/guides/rel_notes/release_22_07.rst
> > index 42a5f2d..ef9906b 100644
> > --- a/doc/guides/rel_notes/release_22_07.rst
> > +++ b/doc/guides/rel_notes/release_22_07.rst
> > @@ -55,6 +55,10 @@ New Features
> > Also, make sure to start the actual text at the margin.
> > =======================================================
> >
> > +* **Added Intel ACC101 baseband PMD.**
> > +
> > + * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
> > + * See the :doc:`../bbdevs/acc101` for more details.
> >
> > Removed Items
> > -------------
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index de7e4bc..fca27ef 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -22,6 +22,7 @@
> > #include <rte_bbdev.h>
> > #include <rte_bbdev_pmd.h>
> > #include "rte_acc100_pmd.h"
> > +#include "rte_acc101_pmd.h"
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); @@ -1286,6
> +1287,12
> > @@
> > RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> > }
> >
> > +static inline bool
> > +is_acc100(struct acc100_queue *q)
> > +{
> > + return (q->d->device_variant == ACC100_VARIANT); }
> > +
> > /* Fill in a frame control word for LDPC decoding. */
> > static inline void
> > acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct
> > acc100_fcw_ld *fcw, @@ -1412,6 +1419,139 @@
> > }
> > }
> >
> > +/* Convert offset to harq index for harq_layout structure */ static
> > +inline uint32_t hq_index(uint32_t offset) {
> > + return (offset >> ACC100_HARQ_OFFSET_SHIFT) &
> > +ACC100_HARQ_OFFSET_MASK; }
> > +
> > +/* Fill in a frame control word for LDPC decoding for ACC101 */
> > +static inline void acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op,
> > +struct acc100_fcw_ld *fcw,
> > + union acc100_harq_layout_data *harq_layout)
> This looks extremely similar to the acc100*, why isn't this combined ?
> > +{
> > + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
> > + uint32_t harq_index;
> > + uint32_t l;
> > +
> > + fcw->qm = op->ldpc_dec.q_m;
> > + fcw->nfiller = op->ldpc_dec.n_filler;
> > + fcw->BG = (op->ldpc_dec.basegraph - 1);
> > + fcw->Zc = op->ldpc_dec.z_c;
> > + fcw->ncb = op->ldpc_dec.n_cb;
> > + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
> > + op->ldpc_dec.rv_index);
> > + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
> > + fcw->rm_e = op->ldpc_dec.cb_params.e;
> > + else
> > + fcw->rm_e = (op->ldpc_dec.tb_params.r <
> > + op->ldpc_dec.tb_params.cab) ?
> > + op->ldpc_dec.tb_params.ea :
> > + op->ldpc_dec.tb_params.eb;
> > +
> > + if (unlikely(check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
> > + (op->ldpc_dec.harq_combined_input.length == 0))) {
> > + rte_bbdev_log(WARNING, "Null HARQ input size provided");
> > + /* Disable HARQ input in that case to carry forward */
> > + op->ldpc_dec.op_flags ^=
> RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> > + }
> > +
> > + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
> > + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
> > + fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
> > + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_DECODE_BYPASS);
> > + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
> > + if (op->ldpc_dec.q_m == 1) {
> > + fcw->bypass_intlv = 1;
> > + fcw->qm = 2;
> > + }
> > + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> > + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> > + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_LLR_COMPRESSION);
> > + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
> > + if (fcw->hcin_en > 0) {
> > + harq_in_length = op->ldpc_dec.harq_combined_input.length;
> > + if (fcw->hcin_decomp_mode > 0)
> > + harq_in_length = harq_in_length * 8 / 6;
> > + harq_in_length = RTE_MIN(harq_in_length, op-
> >ldpc_dec.n_cb
> > + - op->ldpc_dec.n_filler);
> > + /* Alignment on next 64B - Already enforced from HC output */
> > + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> > + fcw->hcin_size0 = harq_in_length;
> > + fcw->hcin_offset = 0;
> > + fcw->hcin_size1 = 0;
> > + } else {
> > + fcw->hcin_size0 = 0;
> > + fcw->hcin_offset = 0;
> > + fcw->hcin_size1 = 0;
> > + }
> > +
> > + fcw->itmax = op->ldpc_dec.iter_max;
> > + fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
> > + fcw->synd_precoder = fcw->itstop;
> > + /*
> > + * These are all implicitly set
> > + * fcw->synd_post = 0;
> > + * fcw->so_en = 0;
> > + * fcw->so_bypass_rm = 0;
> > + * fcw->so_bypass_intlv = 0;
> > + * fcw->dec_convllr = 0;
> > + * fcw->hcout_convllr = 0;
> > + * fcw->hcout_size1 = 0;
> > + * fcw->so_it = 0;
> > + * fcw->hcout_offset = 0;
> > + * fcw->negstop_th = 0;
> > + * fcw->negstop_it = 0;
> > + * fcw->negstop_en = 0;
> > + * fcw->gain_i = 1;
> > + * fcw->gain_h = 1;
> > + */
> > + if (fcw->hcout_en > 0) {
> > + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
> > + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
> > + k0_p = (fcw->k0 > parity_offset) ?
> > + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
> > + ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> > + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
> > + harq_out_length = (uint16_t) fcw->hcin_size0;
> > + harq_out_length = RTE_MAX(harq_out_length, l);
> > + /* Cannot exceed the pruned Ncb circular buffer */
> > + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> > + /* Alignment on next 64B */
> > + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> > + fcw->hcout_size0 = harq_out_length;
> > + fcw->hcout_size1 = 0;
> > + fcw->hcout_offset = 0;
> > + harq_layout[harq_index].offset = fcw->hcout_offset;
> > + harq_layout[harq_index].size0 = fcw->hcout_size0;
> > + } else {
> > + fcw->hcout_size0 = 0;
> > + fcw->hcout_size1 = 0;
> > + fcw->hcout_offset = 0;
> > + }
> > +}
> > +
> > +static inline void
> > +acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld
> *fcw,
> > + union acc100_harq_layout_data *harq_layout, struct
> acc100_queue *q)
> > +{
> > + if (is_acc100(q))
> consider having a function table in the private data so the call can be made
> without this if-check
> > + return acc100_fcw_ld_fill(op, fcw, harq_layout);
> > + else
> > + return acc101_fcw_ld_fill(op, fcw, harq_layout); }
> > +
> > +
> > /**
> > * Fills descriptor with data pointers of one block type.
> > *
> > @@ -2960,7 +3100,7 @@
> > struct acc100_fcw_ld *fcw;
> > uint32_t seg_total_left;
> > fcw = &desc->req.fcw_ld;
> > - acc100_fcw_ld_fill(op, fcw, harq_layout);
> > + acc10x_fcw_ld_fill(op, fcw, harq_layout, q);
> >
> > /* Special handling when overusing mbuf */
> > if (fcw->rm_e < ACC100_MAX_E_MBUF) @@ -3027,7 +3167,7
> @@
> > desc = q->ring_addr + desc_idx;
> > uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
> > union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
> > - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
> > + acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q);
> >
> > input = op->ldpc_dec.input.data;
> > h_output_head = h_output = op->ldpc_dec.hard_output.data; @@
> > -4139,9 +4279,17 @@
> > dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
> > dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
> >
> > - ((struct acc100_device *) dev->data->dev_private)->pf_device =
> > - !strcmp(drv->driver.name,
> > - RTE_STR(ACC100PF_DRIVER_NAME));
> > + if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME)))
> ||
> > + (!strcmp(drv->driver.name,
> RTE_STR(ACC100VF_DRIVER_NAME)))) {
> > + ((struct acc100_device *) dev->data->dev_private)->pf_device
> =
> > + !strcmp(drv->driver.name,
> RTE_STR(ACC100PF_DRIVER_NAME));
> > + ((struct acc100_device *) dev->data->dev_private)-
> >device_variant = ACC100_VARIANT;
> > + } else {
> > + ((struct acc100_device *) dev->data->dev_private)->pf_device
> =
> > + !strcmp(drv->driver.name,
> RTE_STR(ACC101PF_DRIVER_NAME));
> > + ((struct acc100_device *) dev->data->dev_private)-
> >device_variant = ACC101_VARIANT;
> > + }
> > +
> > ((struct acc100_device *) dev->data->dev_private)->mmio_base =
> > pci_dev->mem_resource[0].addr;
> >
> > @@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME,
> acc100_pci_vf_driver);
> > RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME,
> > pci_id_acc100_vf_map);
> >
> > +/* ACC101 PCI PF address map */
> > +static struct rte_pci_id pci_id_acc101_pf_map[] = {
> > + {
> > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> RTE_ACC101_PF_DEVICE_ID)
> > + },
> > + {.device_id = 0},
> > +};
> > +
> > +/* ACC101 PCI VF address map */
> > +static struct rte_pci_id pci_id_acc101_vf_map[] = {
> > + {
> > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> RTE_ACC101_VF_DEVICE_ID)
> > + },
> > + {.device_id = 0},
> > +};
> > +
> > +
> > +static struct rte_pci_driver acc101_pci_pf_driver = {
> > + .probe = acc100_pci_probe,
> > + .remove = acc100_pci_remove,
> > + .id_table = pci_id_acc101_pf_map,
> > + .drv_flags = RTE_PCI_DRV_NEED_MAPPING };
> > +
> > +static struct rte_pci_driver acc101_pci_vf_driver = {
> > + .probe = acc100_pci_probe,
> > + .remove = acc100_pci_remove,
> > + .id_table = pci_id_acc101_vf_map,
> > + .drv_flags = RTE_PCI_DRV_NEED_MAPPING };
> > +
> > +RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME,
> acc101_pci_pf_driver);
> > +RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME,
> > +pci_id_acc101_pf_map);
> RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME,
> > +acc101_pci_vf_driver);
> > +RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME,
> > +pci_id_acc101_vf_map);
> > +
> > /*
> > * Workaround implementation to fix the power on status of some 5GUL
> engines
> > * This requires DMA permission if ported outside DPDK diff --git
> > a/drivers/baseband/acc100/rte_acc100_pmd.h
> > b/drivers/baseband/acc100/rte_acc100_pmd.h
> > index cbcece2..6438031 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> > @@ -22,6 +22,9 @@
> > #define rte_bbdev_log_debug(fmt, ...)
> > #endif
> >
> > +#define ACC100_VARIANT 0
> > +#define ACC101_VARIANT 1
> > +
> > /* ACC100 PF and VF driver names */
> > #define ACC100PF_DRIVER_NAME intel_acc100_pf
> > #define ACC100VF_DRIVER_NAME intel_acc100_vf
> > @@ -67,6 +70,8 @@
> > #define ACC100_HARQ_LAYOUT (64*1024*1024)
> > /* Assume offset for HARQ in memory */
> > #define ACC100_HARQ_OFFSET (32*1024)
> > +#define ACC100_HARQ_OFFSET_SHIFT 15
> > +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
> > /* Mask used to calculate an index in an Info Ring array (not a byte offset) */
> > #define ACC100_INFO_RING_MASK
> (ACC100_INFO_RING_NUM_ENTRIES-1)
> > /* Number of Virtual Functions ACC100 supports */ @@ -590,6 +595,7
> > @@ struct acc100_device {
> > uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
> > bool pf_device; /**< True if this is a PF ACC100 device */
> > bool configured; /**< True if this ACC100 device is configured */
> > + uint16_t device_variant; /**< Device variant */
> this is not needed, check the pci id
That device_variant is sent once during probing then we can reuse that flexibly through the code.
> > };
> >
> > /**
> > diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h
> > b/drivers/baseband/acc100/rte_acc101_pmd.h
> > new file mode 100644
> > index 0000000..efab400
> > --- /dev/null
> > +++ b/drivers/baseband/acc100/rte_acc101_pmd.h
>
> New files need license, copyrights.
Thanks!!
>
> This file looks very similar to rte_acc100_pmd.h
Actually the configuration of the device differs and could diverge further in the future. This is limited to the part that would be specific to the device configuration.
Already kept to extremely reduced set. Doing it more would be artificial and source of possible errors.
>
> The common parts should be in only one file, maybe a rte_acc10x_pmd.h
>
> > @@ -0,0 +1,61 @@
> > +/* ACC101 PF and VF driver names */
> > +#define ACC101PF_DRIVER_NAME intel_acc101_pf
> > +#define ACC101VF_DRIVER_NAME intel_acc101_vf
>
> this maybe changes to intel_acc10x_pr/vf ?
That string would be different from the 2 products on purpose even if under the bonnet we try to reuse code as much as possible.
>
> Tom
>
> > +
> > +/* ACC101 PCI vendor & device IDs */
> > +#define RTE_ACC101_VENDOR_ID (0x8086)
> > +#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
> > +#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
> > +
> > +/* Define as 1 to use only a single FEC engine */ #ifndef
> > +RTE_ACC101_SINGLE_FEC #define RTE_ACC101_SINGLE_FEC 0 #endif
> > +
> > +/* Values used in writing to the registers */
> > +#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts
> */
> > +
> > +/* Number of Virtual Functions ACC101 supports */
> > +#define ACC101_NUM_VFS 16
> > +#define ACC101_NUM_QGRPS 8
> > +#define ACC101_NUM_AQS 16
> > +/* All ACC101 Registers alignment are 32bits = 4B */
> > +#define ACC101_BYTES_IN_WORD 4
> > +
> > +#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
> > +#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
> > +#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS
> Mon */
> > +#define ACC101_TMPL_PRI_0 0x03020100
> > +#define ACC101_TMPL_PRI_1 0x07060504
> > +#define ACC101_TMPL_PRI_2 0x0b0a0908
> > +#define ACC101_TMPL_PRI_3 0x0f0e0d0c
> > +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
> > +
> > +#define ACC101_NUM_TMPL 32
> > +/* Mapping of signals for the available engines */
> > +#define ACC101_SIG_UL_5G 0
> > +#define ACC101_SIG_UL_5G_LAST 8
> > +#define ACC101_SIG_DL_5G 13
> > +#define ACC101_SIG_DL_5G_LAST 15
> > +#define ACC101_SIG_UL_4G 16
> > +#define ACC101_SIG_UL_4G_LAST 19
> > +#define ACC101_SIG_DL_4G 27
> > +#define ACC101_SIG_DL_4G_LAST 31
> > +#define ACC101_NUM_ACCS 5
> > +#define ACC101_PF_VAL 2
> > +
> > +/* ACC101 Configuration */
> > +#define ACC101_CFG_DMA_ERROR 0x3D7
> > +#define ACC101_CFG_AXI_CACHE 0x11
> > +#define ACC101_CFG_QMGR_HI_P 0x0F0F
> > +#define ACC101_CFG_PCI_AXI 0xC003
> > +#define ACC101_CFG_PCI_BRIDGE 0x40006033
> > +#define ACC101_ENGINE_OFFSET 0x1000
> > +#define ACC101_LONG_WAIT 1000
> > +#define ACC101_GPEX_AXIMAP_NUM 17
> > +#define ACC101_CLOCK_GATING_EN 0x30000
> > +#define ACC101_DMA_INBOUND 0x104
> > +/* DDR Size per VF - 512MB by default
> > + * Can be increased up to 4 GB with single PF/VF */
> > +#define ACC101_HARQ_DDR (512 * 1)
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v2 2/5] baseband/acc100: modify validation code for ACC101
2022-05-08 13:07 ` Tom Rix
@ 2022-05-09 21:27 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-09 21:27 UTC (permalink / raw)
To: Tom Rix, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
Hi Tom,
> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Sunday, May 8, 2022 6:07 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
> Subject: Re: [PATCH v2 2/5] baseband/acc100: modify validation code for
> ACC101
>
>
> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> > The validation requirement is different for the two devices.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > drivers/baseband/acc100/rte_acc100_pmd.c | 40
> ++++++++++++++++++++++----------
> > 1 file changed, 28 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index fca27ef..daf2ce0 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -1293,6 +1293,14 @@
> > return (q->d->device_variant == ACC100_VARIANT);
> > }
> >
> > +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> > +static inline bool
> > +validate_op_required(struct acc100_queue *q)
>
> There isn't an #else case so this will fail to build.
There is no else required I believe, since that function is not used when the RTE_LIBRTE_BBDEV_DEBUG is not set. It should build on both (I believe this is tested by CICD).
>
> This i believe could be another function in private data fops i suggested in the
> first patch.
In that case we do not expect to validate the input on ACC100, there is not such function.
>
> Tom
>
> > +{
> > + return is_acc100(q);
> > +}
> > +#endif
> > +
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF
2022-05-08 13:38 ` Tom Rix
@ 2022-05-09 21:36 ` Chautru, Nicolas
2022-05-10 12:02 ` Tom Rix
0 siblings, 1 reply; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-09 21:36 UTC (permalink / raw)
To: Tom Rix, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Sunday, May 8, 2022 6:38 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
> Subject: Re: [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from
> PF
>
>
> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> > Adding companion function specific to ACC100 and it can be called from
> > bbdev-test when running from PF.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > app/test-bbdev/test_bbdev_perf.c | 57 ++++++
> > drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
> > drivers/baseband/acc100/rte_acc100_pmd.c | 302
> +++++++++++++++++++++++++++++++
> > drivers/baseband/acc100/version.map | 2 +-
> > 4 files changed, 377 insertions(+), 1 deletion(-)
> >
> > diff --git a/app/test-bbdev/test_bbdev_perf.c
> > b/app/test-bbdev/test_bbdev_perf.c
> > index 0fa119a..baf5f6d 100644
> > --- a/app/test-bbdev/test_bbdev_perf.c
> > +++ b/app/test-bbdev/test_bbdev_perf.c
> > @@ -63,6 +63,8 @@
> > #define ACC100_QMGR_INVALID_IDX -1
> > #define ACC100_QMGR_RR 1
> > #define ACC100_QOS_GBR 0
> > +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
> > +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
> A dup from patch 1
> > #endif
> >
> > #define OPS_CACHE_SIZE 256U
> > @@ -765,6 +767,61 @@ typedef int (test_case_function)(struct
> active_device *ad,
> > "Failed to configure ACC100 PF for bbdev %s",
> > info->dev_name);
> > }
> > + if ((get_init_device() == true) &&
> > + (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))
> {
> > + struct rte_acc100_conf conf;
>
> Mixing up acc100 and acc101 ?
>
> If this actually works, combine the two.
The configuration file template is the same but not the configuration file. I can combine a bit more that part.
>
> > + unsigned int i;
> > +
> > + printf("Configure ACC101 FEC Driver %s with default values\n",
> > + info->drv.driver_name);
> > +
> > + /* clear default configuration before initialization */
> > + memset(&conf, 0, sizeof(struct rte_acc100_conf));
> > +
> > + /* Always set in PF mode for built-in configuration */
> > + conf.pf_mode_en = true;
> > + for (i = 0; i < RTE_ACC100_NUM_VFS; ++i) {
> > + conf.arb_dl_4g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_dl_4g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_dl_4g[i].round_robin_weight =
> ACC100_QMGR_RR;
> > + conf.arb_ul_4g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_ul_4g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_ul_4g[i].round_robin_weight =
> ACC100_QMGR_RR;
> > + conf.arb_dl_5g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_dl_5g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_dl_5g[i].round_robin_weight =
> ACC100_QMGR_RR;
> > + conf.arb_ul_5g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_ul_5g[i].gbr_threshold1 =
> ACC100_QOS_GBR;
> > + conf.arb_ul_5g[i].round_robin_weight =
> ACC100_QMGR_RR;
> > + }
> > +
> > + conf.input_pos_llr_1_bit = true;
> > + conf.output_pos_llr_1_bit = true;
> > + conf.num_vf_bundles = 1; /**< Number of VF bundles to setup
> */
> > +
> > + conf.q_ul_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
> > + conf.q_ul_4g.first_qgroup_index =
> ACC100_QMGR_INVALID_IDX;
> > + conf.q_ul_4g.num_aqs_per_groups =
> ACC100_QMGR_NUM_AQS;
> > + conf.q_ul_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> > + conf.q_dl_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
> > + conf.q_dl_4g.first_qgroup_index =
> ACC100_QMGR_INVALID_IDX;
> > + conf.q_dl_4g.num_aqs_per_groups =
> ACC100_QMGR_NUM_AQS;
> > + conf.q_dl_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> > + conf.q_ul_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
> > + conf.q_ul_5g.first_qgroup_index =
> ACC100_QMGR_INVALID_IDX;
> > + conf.q_ul_5g.num_aqs_per_groups =
> ACC100_QMGR_NUM_AQS;
> > + conf.q_ul_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> > + conf.q_dl_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
> > + conf.q_dl_5g.first_qgroup_index =
> ACC100_QMGR_INVALID_IDX;
> > + conf.q_dl_5g.num_aqs_per_groups =
> ACC100_QMGR_NUM_AQS;
> > + conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> > +
> > + /* setup PF with configuration information */
> > + ret = rte_acc101_configure(info->dev_name, &conf);
> > + TEST_ASSERT_SUCCESS(ret,
> > + "Failed to configure ACC101 PF for bbdev %s",
> > + info->dev_name);
> > + }
> > #endif
> > /* Let's refresh this now this is configured */
> > rte_bbdev_info_get(dev_id, info);
> > diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h
> > b/drivers/baseband/acc100/rte_acc100_cfg.h
> > index d233e42..2e3c43f 100644
> > --- a/drivers/baseband/acc100/rte_acc100_cfg.h
> > +++ b/drivers/baseband/acc100/rte_acc100_cfg.h
>
> This file marks its API as experimental though the acc100 has been used in
> production for some time.
>
> It is important that the API be stable.
>
> Is this an oversight ?
>
> Or what is needed to stabilize the API ?
This is not part of the BBDEV-API, this is companion function to configure the device notably for bbdev-test. ie. would not be used in live production (ie. we would not run from the PF).
It could be made non experimental through another patch if desired.
With regards to the ACC101, this is the new function hence starting as experimental.
>
> > @@ -106,6 +106,23 @@ struct rte_acc100_conf {
> > int
> > rte_acc100_configure(const char *dev_name, struct rte_acc100_conf
> > *conf);
> >
> > +/**
> > + * Configure a ACC101 device
> > + *
> > + * @param dev_name
> > + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
> > + * It can also be retrieved for a bbdev device from the dev_name field in the
> > + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> > + * @param conf
> > + * Configuration to apply to ACC101 HW.
> > + *
> > + * @return
> > + * Zero on success, negative value on failure.
> > + */
> > +__rte_experimental
> > +int
> > +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf
> > +*conf);
>
> I am finding seeing acc100* structs in acc101 function parameters confusing.
>
> Maybe a general renaming of acc100 -> acc10x for the common parts.
Again this is just a companion function to configure the device.
>
> Will we have this problem on acc120 or acc200 ?
There is a plan for ACC200 but that is a complete different product and distinct PMD.
>
> Maybe shorten everything now to acc
>
> > +
> > #ifdef __cplusplus
> > }
> > #endif
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index daf2ce0..b03cedc 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > rte_bbdev_log_debug("PF Tip configuration complete for %s",
> dev_name);
> > return 0;
> > }
> > +
> > +
> > +/* Initial configuration of a ACC101 device prior to running
> > +configure() */ int rte_acc101_configure(const char *dev_name, struct
> > +rte_acc100_conf *conf) {
>
> This is very similar to the acc100 configure function.
>
> It would be good if these could be combined.
These should not be combined. The device configuration is distinct and would be artificial to make that function support non compatible register interface.
Note that this functional is again is not part of PMD.
>
> Tom
>
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario
2022-05-08 13:55 ` Tom Rix
@ 2022-05-09 21:45 ` Chautru, Nicolas
2022-05-10 12:11 ` Tom Rix
0 siblings, 1 reply; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-09 21:45 UTC (permalink / raw)
To: Tom Rix, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
Hi Tom,
> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Sunday, May 8, 2022 6:56 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
> Subject: Re: [PATCH v2 5/5] baseband/acc100: add protection for some
> negative scenario
>
>
> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> > Catch exception in PMD in case of invalid input parameter.
>
> It is not clear if this is 1 fix or 2.
>
> But it does look like an acc100 fix so it should be split from the
> acc101 patchset.
>
What is the concern? This is a different commit related to acc100.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index b588f5f..a13966c 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -1241,6 +1241,8 @@
> > return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2)
> * z_c;
> > }
> > /* LBRM case - includes a division by N */
> > + if (unlikely(z_c == 0))
> > + return 0;
>
> This check should be moved to earlier, if 'n' is set to 0 in the statement above,
> there is div by 0 later
N is purely a factor of z_c, I don’t see the concern is order.
>
> Tom
>
> > if (rv_index == 1)
> > return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) *
> n_cb)
> > / n) * z_c;
> > @@ -1916,6 +1918,10 @@ static inline uint32_t hq_index(uint32_t
> > offset)
> >
> > /* Soft output */
> > if (check_bit(op->turbo_dec.op_flags,
> RTE_BBDEV_TURBO_SOFT_OUTPUT))
> > {
> > + if (op->turbo_dec.soft_output.data == 0) {
> > + rte_bbdev_log(ERR, "Soft output is not defined");
> > + return -1;
> > + }
> > if (check_bit(op->turbo_dec.op_flags,
> > RTE_BBDEV_TURBO_EQUALIZER))
> > *s_out_length = e;
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD
2022-05-08 13:44 ` Tom Rix
@ 2022-05-09 22:07 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-09 22:07 UTC (permalink / raw)
To: Tom Rix, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
Hi Tom,
> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Sunday, May 8, 2022 6:45 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
> Subject: Re: [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from
> PMD
>
>
> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> > Ensure the performance monitor is restarted in case this is reset
> > after VF FLR.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++
> > drivers/baseband/acc100/rte_acc100_pmd.h | 6 ++++++
> > 2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index b03cedc..b588f5f 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -263,6 +263,10 @@
> > & 0xF;
> > }
> >
> > + /* Start Pmon */
> > + acc100_reg_write(d, reg_addr->pmon_ctrl_a, 0x2);
> > + acc100_reg_write(d, reg_addr->pmon_ctrl_b, 0x2);
>
> This looks like an acc100 bug fix, so it should be split from the acc101 pathset.
>
> Where this code is added is fetch_acc100_config, a function that does reads.
>
> Though convenient, this is likely not the best place to put the writes
>
OK fair enough It could be part of setup_queues(), Thanks.
> Tom
>
> > +
> > /* Read PF mode */
> > if (d->pf_device) {
> > reg_mode = acc100_reg_read(d, HWPfHiPfMode); diff --git
> > a/drivers/baseband/acc100/rte_acc100_pmd.h
> > b/drivers/baseband/acc100/rte_acc100_pmd.h
> > index 6438031..f126cc0 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> > @@ -475,6 +475,8 @@ struct acc100_registry_addr {
> > unsigned int depth_log1_offset;
> > unsigned int qman_group_func;
> > unsigned int ddr_range;
> > + unsigned int pmon_ctrl_a;
> > + unsigned int pmon_ctrl_b;
> > };
> >
> > /* Structure holding registry addresses for PF */ @@ -504,6 +506,8
> > @@ struct acc100_registry_addr {
> > .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
> > .qman_group_func = HWPfQmgrGrpFunction0,
> > .ddr_range = HWPfDmaVfDdrBaseRw,
> > + .pmon_ctrl_a = HWPfPermonACntrlRegVf,
> > + .pmon_ctrl_b = HWPfPermonBCntrlRegVf,
> > };
> >
> > /* Structure holding registry addresses for VF */ @@ -533,6 +537,8
> > @@ struct acc100_registry_addr {
> > .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
> > .qman_group_func = HWVfQmgrGrpFunction0Vf,
> > .ddr_range = HWVfDmaDdrBaseRangeRoVf,
> > + .pmon_ctrl_a = HWVfPmACntrlRegVf,
> > + .pmon_ctrl_b = HWVfPmBCntrlRegVf,
> > };
> >
> > /* Structure associated with each queue. */
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
2022-05-09 21:23 ` Chautru, Nicolas
@ 2022-05-10 8:52 ` Thomas Monjalon
2022-05-10 11:55 ` Tom Rix
1 sibling, 0 replies; 84+ messages in thread
From: Thomas Monjalon @ 2022-05-10 8:52 UTC (permalink / raw)
To: Tom Rix, gakhil, Chautru, Nicolas
Cc: dev, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
09/05/2022 23:23, Chautru, Nicolas:
> From: Tom Rix <trix@redhat.com>
> > A quick look at acc100.rst and the bulk of acc101.rst looks the same.
> > Consider a user of the acc100 is upgrading to acc101, they will
> > want to know what is the same and what has changed and test accordingly.
> > These two documents should be combined.
>
> Well in term of documentation, for the users it helps to be able to follow steps as they are for a given variant.
> As opposed to have to have multiple options through the document when using ACC100 vs ACC101.
> Except if they are other objections, I would see this more useful for the user as is and less source of errors.
I agree with Tom, it is more useful to highlight the differences
with some notes and keep a common tutorial.
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
2022-05-09 21:23 ` Chautru, Nicolas
2022-05-10 8:52 ` Thomas Monjalon
@ 2022-05-10 11:55 ` Tom Rix
2022-05-23 17:53 ` Chautru, Nicolas
1 sibling, 1 reply; 84+ messages in thread
From: Tom Rix @ 2022-05-10 11:55 UTC (permalink / raw)
To: Chautru, Nicolas, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
On 5/9/22 2:23 PM, Chautru, Nicolas wrote:
> Hi Tom,
>
>> -----Original Message-----
>> From: Tom Rix <trix@redhat.com>
>> Sent: Sunday, May 8, 2022 6:03 AM
>> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
>> gakhil@marvell.com
>> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
>> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
>> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
>> Subject: Re: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
>>
>> This is a good start reusing code, but I think it needs to do more reuse.
>>
>> These cards should be very close and likely represent a family of cards.
>>
>> On 4/27/22 11:16 AM, Nicolas Chautru wrote:
>>> Support for ACC101 as a derivative of ACC100.
>>> Reusing existing code when possible.
>>>
>>> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
>>> ---
>>> doc/guides/bbdevs/acc101.rst | 237
>> +++++++++++++++++++++++++++++++
>>> doc/guides/bbdevs/features/acc101.ini | 13 ++
>>> doc/guides/bbdevs/index.rst | 1 +
>>> doc/guides/rel_notes/release_22_07.rst | 4 +
>>> drivers/baseband/acc100/rte_acc100_pmd.c | 194
>> ++++++++++++++++++++++++-
>>> drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
>>> drivers/baseband/acc100/rte_acc101_pmd.h | 61 ++++++++
>>> 7 files changed, 511 insertions(+), 5 deletions(-)
>>> create mode 100644 doc/guides/bbdevs/acc101.rst
>>> create mode 100644 doc/guides/bbdevs/features/acc101.ini
>>> create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
>>>
>>> diff --git a/doc/guides/bbdevs/acc101.rst
>>> b/doc/guides/bbdevs/acc101.rst new file mode 100644 index
>>> 0000000..46c310b
>>> --- /dev/null
>>> +++ b/doc/guides/bbdevs/acc101.rst
>>> @@ -0,0 +1,237 @@
>>> +.. SPDX-License-Identifier: BSD-3-Clause
>>> + Copyright(c) 2020 Intel Corporation
>>> +
>>> +Intel(R) ACC101 5G/4G FEC Poll Mode Driver
>>> +==========================================
>>> +
>>> +The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an
>>> +implementation of a VRAN FEC wireless acceleration function.
>>> +This device is also known as Mount Cirrus.
>>> +This is a follow-up to Mount Bryce (ACC100) and includes fixes,
>>> +improved feature set for error scenarios and performance capacity increase.
>> includes fixes, better error handling and increased performance.
>>
>> A quick look at acc100.rst and the bulk of acc101.rst looks the same.
>>
>> Consider a user of the acc100 is upgrading to acc101, they will
>>
>> want to know what is the same and what has changed and test accordingly.
>>
>> These two documents should be combined.
>>
> Well in term of documentation, for the users it helps to be able to follow steps as they are for a given variant.
> As opposed to have to have multiple options through the document when using ACC100 vs ACC101.
> Except if they are other objections, I would see this more useful for the user as is and less source of errors.
>
My perspective is having existing acc100 users that are upgrading and/or
having to support both acc100 and acc101
for a very long time. In the first case users of existing acc100 users
will want to know only the parts that have changed.
In the second, later changes that are common to both acc100 and acc101
and later accXXX will be have to fixed in
multiple places. As myself or someone at Red Hat will be on the hook
for both, I would prefer if the refactoring
of the common parts acc100,acc101 were in good shape over the expediency
of having acc101 sooner.
>>> +
>>> +Features
>>> +--------
>>> +
>>> index 0000000..0e2c21a
>>> --- /dev/null
>>> +++ b/doc/guides/bbdevs/features/acc101.ini
>>> @@ -0,0 +1,13 @@
>>> +;
>>> +; Supported features of the 'acc101' bbdev driver.
>>> +;
>>> +; Refer to default.ini for the full list of available PMD features.
>>> +;
>>> +[Features]
>>> +Turbo Decoder (4G) = Y
>>> +Turbo Encoder (4G) = Y
>>> +LDPC Decoder (5G) = Y
>>> +LDPC Encoder (5G) = Y
>>> +LLR/HARQ Compression = Y
>>> +External DDR Access = Y
>>> +HW Accelerated = Y
>> This is the same as acc100.ini, why do we need 2 ?
> This is a different product, needs to be consistent.
ok
>
>>> diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
>>> index cedd706..e76883c 100644
>>> --- a/doc/guides/bbdevs/index.rst
>>> +++ b/doc/guides/bbdevs/index.rst
>>> @@ -14,4 +14,5 @@ Baseband Device Drivers
>>> fpga_lte_fec
>>> fpga_5gnr_fec
>>> acc100
>>> + acc101
>>> la12xx
>>> diff --git a/doc/guides/rel_notes/release_22_07.rst
>>> b/doc/guides/rel_notes/release_22_07.rst
>>> index 42a5f2d..ef9906b 100644
>>> --- a/doc/guides/rel_notes/release_22_07.rst
>>> +++ b/doc/guides/rel_notes/release_22_07.rst
>>> @@ -55,6 +55,10 @@ New Features
>>> Also, make sure to start the actual text at the margin.
>>> =======================================================
>>>
>>> +* **Added Intel ACC101 baseband PMD.**
>>> +
>>> + * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
>>> + * See the :doc:`../bbdevs/acc101` for more details.
>>>
>>> Removed Items
>>> -------------
>>> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> index de7e4bc..fca27ef 100644
>>> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> @@ -22,6 +22,7 @@
>>> #include <rte_bbdev.h>
>>> #include <rte_bbdev_pmd.h>
>>> #include "rte_acc100_pmd.h"
>>> +#include "rte_acc101_pmd.h"
>>>
>>> #ifdef RTE_LIBRTE_BBDEV_DEBUG
>>> RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); @@ -1286,6
>> +1287,12
>>> @@
>>> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
>>> }
>>>
>>> +static inline bool
>>> +is_acc100(struct acc100_queue *q)
>>> +{
>>> + return (q->d->device_variant == ACC100_VARIANT); }
>>> +
>>> /* Fill in a frame control word for LDPC decoding. */
>>> static inline void
>>> acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct
>>> acc100_fcw_ld *fcw, @@ -1412,6 +1419,139 @@
>>> }
>>> }
>>>
>>> +/* Convert offset to harq index for harq_layout structure */ static
>>> +inline uint32_t hq_index(uint32_t offset) {
>>> + return (offset >> ACC100_HARQ_OFFSET_SHIFT) &
>>> +ACC100_HARQ_OFFSET_MASK; }
>>> +
>>> +/* Fill in a frame control word for LDPC decoding for ACC101 */
>>> +static inline void acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op,
>>> +struct acc100_fcw_ld *fcw,
>>> + union acc100_harq_layout_data *harq_layout)
>> This looks extremely similar to the acc100*, why isn't this combined ?
Please answer.
Functions that look similar should be combined.
This gets to doing more to refactor the parts that are common between
acc100 and acc101.
>>> +{
>>> + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
>>> + uint32_t harq_index;
>>> + uint32_t l;
>>> +
>>> + fcw->qm = op->ldpc_dec.q_m;
>>> + fcw->nfiller = op->ldpc_dec.n_filler;
>>> + fcw->BG = (op->ldpc_dec.basegraph - 1);
>>> + fcw->Zc = op->ldpc_dec.z_c;
>>> + fcw->ncb = op->ldpc_dec.n_cb;
>>> + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
>>> + op->ldpc_dec.rv_index);
>>> + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
>>> + fcw->rm_e = op->ldpc_dec.cb_params.e;
>>> + else
>>> + fcw->rm_e = (op->ldpc_dec.tb_params.r <
>>> + op->ldpc_dec.tb_params.cab) ?
>>> + op->ldpc_dec.tb_params.ea :
>>> + op->ldpc_dec.tb_params.eb;
>>> +
>>> + if (unlikely(check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
>>> + (op->ldpc_dec.harq_combined_input.length == 0))) {
>>> + rte_bbdev_log(WARNING, "Null HARQ input size provided");
>>> + /* Disable HARQ input in that case to carry forward */
>>> + op->ldpc_dec.op_flags ^=
>> RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
>>> + }
>>> +
>>> + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
>>> + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
>>> + fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
>>> + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_DECODE_BYPASS);
>>> + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
>>> + if (op->ldpc_dec.q_m == 1) {
>>> + fcw->bypass_intlv = 1;
>>> + fcw->qm = 2;
>>> + }
>>> + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
>>> + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
>>> + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_LLR_COMPRESSION);
>>> + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
>>> + if (fcw->hcin_en > 0) {
>>> + harq_in_length = op->ldpc_dec.harq_combined_input.length;
>>> + if (fcw->hcin_decomp_mode > 0)
>>> + harq_in_length = harq_in_length * 8 / 6;
>>> + harq_in_length = RTE_MIN(harq_in_length, op-
>>> ldpc_dec.n_cb
>>> + - op->ldpc_dec.n_filler);
>>> + /* Alignment on next 64B - Already enforced from HC output */
>>> + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
>>> + fcw->hcin_size0 = harq_in_length;
>>> + fcw->hcin_offset = 0;
>>> + fcw->hcin_size1 = 0;
>>> + } else {
>>> + fcw->hcin_size0 = 0;
>>> + fcw->hcin_offset = 0;
>>> + fcw->hcin_size1 = 0;
>>> + }
>>> +
>>> + fcw->itmax = op->ldpc_dec.iter_max;
>>> + fcw->itstop = check_bit(op->ldpc_dec.op_flags,
>>> + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
>>> + fcw->synd_precoder = fcw->itstop;
>>> + /*
>>> + * These are all implicitly set
>>> + * fcw->synd_post = 0;
>>> + * fcw->so_en = 0;
>>> + * fcw->so_bypass_rm = 0;
>>> + * fcw->so_bypass_intlv = 0;
>>> + * fcw->dec_convllr = 0;
>>> + * fcw->hcout_convllr = 0;
>>> + * fcw->hcout_size1 = 0;
>>> + * fcw->so_it = 0;
>>> + * fcw->hcout_offset = 0;
>>> + * fcw->negstop_th = 0;
>>> + * fcw->negstop_it = 0;
>>> + * fcw->negstop_en = 0;
>>> + * fcw->gain_i = 1;
>>> + * fcw->gain_h = 1;
>>> + */
>>> + if (fcw->hcout_en > 0) {
>>> + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
>>> + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
>>> + k0_p = (fcw->k0 > parity_offset) ?
>>> + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
>>> + ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
>>> + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
>>> + harq_out_length = (uint16_t) fcw->hcin_size0;
>>> + harq_out_length = RTE_MAX(harq_out_length, l);
>>> + /* Cannot exceed the pruned Ncb circular buffer */
>>> + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
>>> + /* Alignment on next 64B */
>>> + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
>>> + fcw->hcout_size0 = harq_out_length;
>>> + fcw->hcout_size1 = 0;
>>> + fcw->hcout_offset = 0;
>>> + harq_layout[harq_index].offset = fcw->hcout_offset;
>>> + harq_layout[harq_index].size0 = fcw->hcout_size0;
>>> + } else {
>>> + fcw->hcout_size0 = 0;
>>> + fcw->hcout_size1 = 0;
>>> + fcw->hcout_offset = 0;
>>> + }
>>> +}
>>> +
>>> +static inline void
>>> +acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld
>> *fcw,
>>> + union acc100_harq_layout_data *harq_layout, struct
>> acc100_queue *q)
>>> +{
>>> + if (is_acc100(q))
>> consider having a function table in the private data so the call can be made
>> without this if-check
Please answer.
>>> + return acc100_fcw_ld_fill(op, fcw, harq_layout);
>>> + else
>>> + return acc101_fcw_ld_fill(op, fcw, harq_layout); }
>>> +
>>> +
>>> /**
>>> * Fills descriptor with data pointers of one block type.
>>> *
>>> @@ -2960,7 +3100,7 @@
>>> struct acc100_fcw_ld *fcw;
>>> uint32_t seg_total_left;
>>> fcw = &desc->req.fcw_ld;
>>> - acc100_fcw_ld_fill(op, fcw, harq_layout);
>>> + acc10x_fcw_ld_fill(op, fcw, harq_layout, q);
>>>
>>> /* Special handling when overusing mbuf */
>>> if (fcw->rm_e < ACC100_MAX_E_MBUF) @@ -3027,7 +3167,7
>> @@
>>> desc = q->ring_addr + desc_idx;
>>> uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
>>> union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
>>> - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
>>> + acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q);
>>>
>>> input = op->ldpc_dec.input.data;
>>> h_output_head = h_output = op->ldpc_dec.hard_output.data; @@
>>> -4139,9 +4279,17 @@
>>> dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
>>> dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
>>>
>>> - ((struct acc100_device *) dev->data->dev_private)->pf_device =
>>> - !strcmp(drv->driver.name,
>>> - RTE_STR(ACC100PF_DRIVER_NAME));
>>> + if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME)))
>> ||
>>> + (!strcmp(drv->driver.name,
>> RTE_STR(ACC100VF_DRIVER_NAME)))) {
>>> + ((struct acc100_device *) dev->data->dev_private)->pf_device
>> =
>>> + !strcmp(drv->driver.name,
>> RTE_STR(ACC100PF_DRIVER_NAME));
>>> + ((struct acc100_device *) dev->data->dev_private)-
>>> device_variant = ACC100_VARIANT;
>>> + } else {
>>> + ((struct acc100_device *) dev->data->dev_private)->pf_device
>> =
>>> + !strcmp(drv->driver.name,
>> RTE_STR(ACC101PF_DRIVER_NAME));
>>> + ((struct acc100_device *) dev->data->dev_private)-
>>> device_variant = ACC101_VARIANT;
>>> + }
>>> +
>>> ((struct acc100_device *) dev->data->dev_private)->mmio_base =
>>> pci_dev->mem_resource[0].addr;
>>>
>>> @@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct
>> rte_pci_device *pci_dev)
>>> RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME,
>> acc100_pci_vf_driver);
>>> RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME,
>>> pci_id_acc100_vf_map);
>>>
>>> +/* ACC101 PCI PF address map */
>>> +static struct rte_pci_id pci_id_acc101_pf_map[] = {
>>> + {
>>> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
>> RTE_ACC101_PF_DEVICE_ID)
>>> + },
>>> + {.device_id = 0},
>>> +};
>>> +
>>> +/* ACC101 PCI VF address map */
>>> +static struct rte_pci_id pci_id_acc101_vf_map[] = {
>>> + {
>>> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
>> RTE_ACC101_VF_DEVICE_ID)
>>> + },
>>> + {.device_id = 0},
>>> +};
>>> +
>>> +
>>> +static struct rte_pci_driver acc101_pci_pf_driver = {
>>> + .probe = acc100_pci_probe,
>>> + .remove = acc100_pci_remove,
>>> + .id_table = pci_id_acc101_pf_map,
>>> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING };
>>> +
>>> +static struct rte_pci_driver acc101_pci_vf_driver = {
>>> + .probe = acc100_pci_probe,
>>> + .remove = acc100_pci_remove,
>>> + .id_table = pci_id_acc101_vf_map,
>>> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING };
>>> +
>>> +RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME,
>> acc101_pci_pf_driver);
>>> +RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME,
>>> +pci_id_acc101_pf_map);
>> RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME,
>>> +acc101_pci_vf_driver);
>>> +RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME,
>>> +pci_id_acc101_vf_map);
>>> +
>>> /*
>>> * Workaround implementation to fix the power on status of some 5GUL
>> engines
>>> * This requires DMA permission if ported outside DPDK diff --git
>>> a/drivers/baseband/acc100/rte_acc100_pmd.h
>>> b/drivers/baseband/acc100/rte_acc100_pmd.h
>>> index cbcece2..6438031 100644
>>> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
>>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
>>> @@ -22,6 +22,9 @@
>>> #define rte_bbdev_log_debug(fmt, ...)
>>> #endif
>>>
>>> +#define ACC100_VARIANT 0
>>> +#define ACC101_VARIANT 1
>>> +
>>> /* ACC100 PF and VF driver names */
>>> #define ACC100PF_DRIVER_NAME intel_acc100_pf
>>> #define ACC100VF_DRIVER_NAME intel_acc100_vf
>>> @@ -67,6 +70,8 @@
>>> #define ACC100_HARQ_LAYOUT (64*1024*1024)
>>> /* Assume offset for HARQ in memory */
>>> #define ACC100_HARQ_OFFSET (32*1024)
>>> +#define ACC100_HARQ_OFFSET_SHIFT 15
>>> +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
>>> /* Mask used to calculate an index in an Info Ring array (not a byte offset) */
>>> #define ACC100_INFO_RING_MASK
>> (ACC100_INFO_RING_NUM_ENTRIES-1)
>>> /* Number of Virtual Functions ACC100 supports */ @@ -590,6 +595,7
>>> @@ struct acc100_device {
>>> uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
>>> bool pf_device; /**< True if this is a PF ACC100 device */
>>> bool configured; /**< True if this ACC100 device is configured */
>>> + uint16_t device_variant; /**< Device variant */
>> this is not needed, check the pci id
> That device_variant is sent once during probing then we can reuse that flexibly through the code.
In the same way the pci id is set once.
Generally if there is a way to use existing data to figure something
out, then use the existing data.
Special purpose data increases the size and complexity as well as
destabilizing the api
>
>
>>> };
>>>
>>> /**
>>> diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h
>>> b/drivers/baseband/acc100/rte_acc101_pmd.h
>>> new file mode 100644
>>> index 0000000..efab400
>>> --- /dev/null
>>> +++ b/drivers/baseband/acc100/rte_acc101_pmd.h
>> New files need license, copyrights.
> Thanks!!
>
>> This file looks very similar to rte_acc100_pmd.h
> Actually the configuration of the device differs and could diverge further in the future. This is limited to the part that would be specific to the device configuration.
> Already kept to extremely reduced set. Doing it more would be artificial and source of possible errors.
>
>> The common parts should be in only one file, maybe a rte_acc10x_pmd.h
>>
>>> @@ -0,0 +1,61 @@
>>> +/* ACC101 PF and VF driver names */
>>> +#define ACC101PF_DRIVER_NAME intel_acc101_pf
>>> +#define ACC101VF_DRIVER_NAME intel_acc101_vf
>> this maybe changes to intel_acc10x_pr/vf ?
> That string would be different from the 2 products on purpose even if under the bonnet we try to reuse code as much as possible.
These two devices could be run from the same driver.
I am used to linux kernel drivers that handle multiple devices with the
same driver.
The reuse in the linux kernel is about 95%.
The reuse here is about 30%, it should be at least 80%
Tom
>
>> Tom
>>
>>> +
>>> +/* ACC101 PCI vendor & device IDs */
>>> +#define RTE_ACC101_VENDOR_ID (0x8086)
>>> +#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
>>> +#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
>>> +
>>> +/* Define as 1 to use only a single FEC engine */ #ifndef
>>> +RTE_ACC101_SINGLE_FEC #define RTE_ACC101_SINGLE_FEC 0 #endif
>>> +
>>> +/* Values used in writing to the registers */
>>> +#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts
>> */
>>> +
>>> +/* Number of Virtual Functions ACC101 supports */
>>> +#define ACC101_NUM_VFS 16
>>> +#define ACC101_NUM_QGRPS 8
>>> +#define ACC101_NUM_AQS 16
>>> +/* All ACC101 Registers alignment are 32bits = 4B */
>>> +#define ACC101_BYTES_IN_WORD 4
>>> +
>>> +#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
>>> +#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
>>> +#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS
>> Mon */
>>> +#define ACC101_TMPL_PRI_0 0x03020100
>>> +#define ACC101_TMPL_PRI_1 0x07060504
>>> +#define ACC101_TMPL_PRI_2 0x0b0a0908
>>> +#define ACC101_TMPL_PRI_3 0x0f0e0d0c
>>> +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
>>> +
>>> +#define ACC101_NUM_TMPL 32
>>> +/* Mapping of signals for the available engines */
>>> +#define ACC101_SIG_UL_5G 0
>>> +#define ACC101_SIG_UL_5G_LAST 8
>>> +#define ACC101_SIG_DL_5G 13
>>> +#define ACC101_SIG_DL_5G_LAST 15
>>> +#define ACC101_SIG_UL_4G 16
>>> +#define ACC101_SIG_UL_4G_LAST 19
>>> +#define ACC101_SIG_DL_4G 27
>>> +#define ACC101_SIG_DL_4G_LAST 31
>>> +#define ACC101_NUM_ACCS 5
>>> +#define ACC101_PF_VAL 2
>>> +
>>> +/* ACC101 Configuration */
>>> +#define ACC101_CFG_DMA_ERROR 0x3D7
>>> +#define ACC101_CFG_AXI_CACHE 0x11
>>> +#define ACC101_CFG_QMGR_HI_P 0x0F0F
>>> +#define ACC101_CFG_PCI_AXI 0xC003
>>> +#define ACC101_CFG_PCI_BRIDGE 0x40006033
>>> +#define ACC101_ENGINE_OFFSET 0x1000
>>> +#define ACC101_LONG_WAIT 1000
>>> +#define ACC101_GPEX_AXIMAP_NUM 17
>>> +#define ACC101_CLOCK_GATING_EN 0x30000
>>> +#define ACC101_DMA_INBOUND 0x104
>>> +/* DDR Size per VF - 512MB by default
>>> + * Can be increased up to 4 GB with single PF/VF */
>>> +#define ACC101_HARQ_DDR (512 * 1)
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF
2022-05-09 21:36 ` Chautru, Nicolas
@ 2022-05-10 12:02 ` Tom Rix
0 siblings, 0 replies; 84+ messages in thread
From: Tom Rix @ 2022-05-10 12:02 UTC (permalink / raw)
To: Chautru, Nicolas, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
On 5/9/22 2:36 PM, Chautru, Nicolas wrote:
>
>> -----Original Message-----
>> From: Tom Rix <trix@redhat.com>
>> Sent: Sunday, May 8, 2022 6:38 AM
>> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
>> gakhil@marvell.com
>> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
>> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
>> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
>> Subject: Re: [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from
>> PF
>>
>>
>> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
>>> Adding companion function specific to ACC100 and it can be called from
>>> bbdev-test when running from PF.
>>>
>>> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
>>> ---
>>> app/test-bbdev/test_bbdev_perf.c | 57 ++++++
>>> drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
>>> drivers/baseband/acc100/rte_acc100_pmd.c | 302
>> +++++++++++++++++++++++++++++++
>>> drivers/baseband/acc100/version.map | 2 +-
>>> 4 files changed, 377 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/app/test-bbdev/test_bbdev_perf.c
>>> b/app/test-bbdev/test_bbdev_perf.c
>>> index 0fa119a..baf5f6d 100644
>>> --- a/app/test-bbdev/test_bbdev_perf.c
>>> +++ b/app/test-bbdev/test_bbdev_perf.c
>>> @@ -63,6 +63,8 @@
>>> #define ACC100_QMGR_INVALID_IDX -1
>>> #define ACC100_QMGR_RR 1
>>> #define ACC100_QOS_GBR 0
>>> +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
>>> +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
>> A dup from patch 1
>>> #endif
>>>
>>> #define OPS_CACHE_SIZE 256U
>>> @@ -765,6 +767,61 @@ typedef int (test_case_function)(struct
>> active_device *ad,
>>> "Failed to configure ACC100 PF for bbdev %s",
>>> info->dev_name);
>>> }
>>> + if ((get_init_device() == true) &&
>>> + (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))
>> {
>>> + struct rte_acc100_conf conf;
>> Mixing up acc100 and acc101 ?
>>
>> If this actually works, combine the two.
> The configuration file template is the same but not the configuration file. I can combine a bit more that part.
>
>>> + unsigned int i;
>>> +
>>> + printf("Configure ACC101 FEC Driver %s with default values\n",
>>> + info->drv.driver_name);
>>> +
>>> + /* clear default configuration before initialization */
>>> + memset(&conf, 0, sizeof(struct rte_acc100_conf));
>>> +
>>> + /* Always set in PF mode for built-in configuration */
>>> + conf.pf_mode_en = true;
>>> + for (i = 0; i < RTE_ACC100_NUM_VFS; ++i) {
>>> + conf.arb_dl_4g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_dl_4g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_dl_4g[i].round_robin_weight =
>> ACC100_QMGR_RR;
>>> + conf.arb_ul_4g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_ul_4g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_ul_4g[i].round_robin_weight =
>> ACC100_QMGR_RR;
>>> + conf.arb_dl_5g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_dl_5g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_dl_5g[i].round_robin_weight =
>> ACC100_QMGR_RR;
>>> + conf.arb_ul_5g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_ul_5g[i].gbr_threshold1 =
>> ACC100_QOS_GBR;
>>> + conf.arb_ul_5g[i].round_robin_weight =
>> ACC100_QMGR_RR;
>>> + }
>>> +
>>> + conf.input_pos_llr_1_bit = true;
>>> + conf.output_pos_llr_1_bit = true;
>>> + conf.num_vf_bundles = 1; /**< Number of VF bundles to setup
>> */
>>> +
>>> + conf.q_ul_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
>>> + conf.q_ul_4g.first_qgroup_index =
>> ACC100_QMGR_INVALID_IDX;
>>> + conf.q_ul_4g.num_aqs_per_groups =
>> ACC100_QMGR_NUM_AQS;
>>> + conf.q_ul_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
>>> + conf.q_dl_4g.num_qgroups = ACC100_QMGR_NUM_QGS;
>>> + conf.q_dl_4g.first_qgroup_index =
>> ACC100_QMGR_INVALID_IDX;
>>> + conf.q_dl_4g.num_aqs_per_groups =
>> ACC100_QMGR_NUM_AQS;
>>> + conf.q_dl_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
>>> + conf.q_ul_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
>>> + conf.q_ul_5g.first_qgroup_index =
>> ACC100_QMGR_INVALID_IDX;
>>> + conf.q_ul_5g.num_aqs_per_groups =
>> ACC100_QMGR_NUM_AQS;
>>> + conf.q_ul_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
>>> + conf.q_dl_5g.num_qgroups = ACC100_QMGR_NUM_QGS;
>>> + conf.q_dl_5g.first_qgroup_index =
>> ACC100_QMGR_INVALID_IDX;
>>> + conf.q_dl_5g.num_aqs_per_groups =
>> ACC100_QMGR_NUM_AQS;
>>> + conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
>>> +
>>> + /* setup PF with configuration information */
>>> + ret = rte_acc101_configure(info->dev_name, &conf);
>>> + TEST_ASSERT_SUCCESS(ret,
>>> + "Failed to configure ACC101 PF for bbdev %s",
>>> + info->dev_name);
>>> + }
>>> #endif
>>> /* Let's refresh this now this is configured */
>>> rte_bbdev_info_get(dev_id, info);
>>> diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h
>>> b/drivers/baseband/acc100/rte_acc100_cfg.h
>>> index d233e42..2e3c43f 100644
>>> --- a/drivers/baseband/acc100/rte_acc100_cfg.h
>>> +++ b/drivers/baseband/acc100/rte_acc100_cfg.h
>> This file marks its API as experimental though the acc100 has been used in
>> production for some time.
>>
>> It is important that the API be stable.
>>
>> Is this an oversight ?
>>
>> Or what is needed to stabilize the API ?
> This is not part of the BBDEV-API, this is companion function to configure the device notably for bbdev-test. ie. would not be used in live production (ie. we would not run from the PF).
> It could be made non experimental through another patch if desired.
> With regards to the ACC101, this is the new function hence starting as experimental.
If this is not part of the bbdev-api at all and is just test code,
please remove all of the experimental tags.
Such tags are reviewed and would be misinterpreted that the source is
not production ready.
>
>>> @@ -106,6 +106,23 @@ struct rte_acc100_conf {
>>> int
>>> rte_acc100_configure(const char *dev_name, struct rte_acc100_conf
>>> *conf);
>>>
>>> +/**
>>> + * Configure a ACC101 device
>>> + *
>>> + * @param dev_name
>>> + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
>>> + * It can also be retrieved for a bbdev device from the dev_name field in the
>>> + * rte_bbdev_info structure returned by rte_bbdev_info_get().
>>> + * @param conf
>>> + * Configuration to apply to ACC101 HW.
>>> + *
>>> + * @return
>>> + * Zero on success, negative value on failure.
>>> + */
>>> +__rte_experimental
>>> +int
>>> +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf
>>> +*conf);
>> I am finding seeing acc100* structs in acc101 function parameters confusing.
>>
>> Maybe a general renaming of acc100 -> acc10x for the common parts.
> Again this is just a companion function to configure the device.
>
>> Will we have this problem on acc120 or acc200 ?
> There is a plan for ACC200 but that is a complete different product and distinct PMD.
>
>> Maybe shorten everything now to acc
>>
>>> +
>>> #ifdef __cplusplus
>>> }
>>> #endif
>>> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> index daf2ce0..b03cedc 100644
>>> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> @@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct
>> rte_pci_device *pci_dev)
>>> rte_bbdev_log_debug("PF Tip configuration complete for %s",
>> dev_name);
>>> return 0;
>>> }
>>> +
>>> +
>>> +/* Initial configuration of a ACC101 device prior to running
>>> +configure() */ int rte_acc101_configure(const char *dev_name, struct
>>> +rte_acc100_conf *conf) {
>> This is very similar to the acc100 configure function.
>>
>> It would be good if these could be combined.
> These should not be combined. The device configuration is distinct and would be artificial to make that function support non compatible register interface.
> Note that this functional is again is not part of PMD.
ok
Tom
>
>> Tom
>>
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario
2022-05-09 21:45 ` Chautru, Nicolas
@ 2022-05-10 12:11 ` Tom Rix
2022-05-10 14:44 ` Thomas Monjalon
0 siblings, 1 reply; 84+ messages in thread
From: Tom Rix @ 2022-05-10 12:11 UTC (permalink / raw)
To: Chautru, Nicolas, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
On 5/9/22 2:45 PM, Chautru, Nicolas wrote:
> Hi Tom,
>
>> -----Original Message-----
>> From: Tom Rix <trix@redhat.com>
>> Sent: Sunday, May 8, 2022 6:56 AM
>> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
>> gakhil@marvell.com
>> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson,
>> Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Zhang,
>> Mingshan <mingshan.zhang@intel.com>; david.marchand@redhat.com
>> Subject: Re: [PATCH v2 5/5] baseband/acc100: add protection for some
>> negative scenario
>>
>>
>> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
>>> Catch exception in PMD in case of invalid input parameter.
>> It is not clear if this is 1 fix or 2.
>>
>> But it does look like an acc100 fix so it should be split from the
>> acc101 patchset.
>>
> What is the concern? This is a different commit related to acc100.
Bisecting patchsets.
A patchset like this that enables a new device should just enable the
new device.
Not enable a new device and random other stuff.
If the patchset had to be reverted, the revert would wipe out the fixes.
That work is done by someone else without deep knowledge or time to
analyze every patchset for misc parts.
The fixes are more important than the new device, so they should be
submitted first.
Tom
>
>>> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
>>> ---
>>> drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
>>> 1 file changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> index b588f5f..a13966c 100644
>>> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> @@ -1241,6 +1241,8 @@
>>> return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2)
>> * z_c;
>>> }
>>> /* LBRM case - includes a division by N */
>>> + if (unlikely(z_c == 0))
>>> + return 0;
>> This check should be moved to earlier, if 'n' is set to 0 in the statement above,
>> there is div by 0 later
> N is purely a factor of z_c, I don’t see the concern is order.
>
>> Tom
>>
>>> if (rv_index == 1)
>>> return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) *
>> n_cb)
>>> / n) * z_c;
>>> @@ -1916,6 +1918,10 @@ static inline uint32_t hq_index(uint32_t
>>> offset)
>>>
>>> /* Soft output */
>>> if (check_bit(op->turbo_dec.op_flags,
>> RTE_BBDEV_TURBO_SOFT_OUTPUT))
>>> {
>>> + if (op->turbo_dec.soft_output.data == 0) {
>>> + rte_bbdev_log(ERR, "Soft output is not defined");
>>> + return -1;
>>> + }
>>> if (check_bit(op->turbo_dec.op_flags,
>>> RTE_BBDEV_TURBO_EQUALIZER))
>>> *s_out_length = e;
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario
2022-05-10 12:11 ` Tom Rix
@ 2022-05-10 14:44 ` Thomas Monjalon
0 siblings, 0 replies; 84+ messages in thread
From: Thomas Monjalon @ 2022-05-10 14:44 UTC (permalink / raw)
To: Chautru, Nicolas, Tom Rix
Cc: dev, gakhil, Kinsella, Ray, Richardson, Bruce, hemant.agrawal,
Zhang, Mingshan, david.marchand
10/05/2022 14:11, Tom Rix:
> On 5/9/22 2:45 PM, Chautru, Nicolas wrote:
> > From: Tom Rix <trix@redhat.com>
> >> On 4/27/22 11:17 AM, Nicolas Chautru wrote:
> >>> Catch exception in PMD in case of invalid input parameter.
> >> It is not clear if this is 1 fix or 2.
> >>
> >> But it does look like an acc100 fix so it should be split from the
> >> acc101 patchset.
> >>
> > What is the concern? This is a different commit related to acc100.
>
> Bisecting patchsets.
>
> A patchset like this that enables a new device should just enable the
> new device.
>
> Not enable a new device and random other stuff.
>
> If the patchset had to be reverted, the revert would wipe out the fixes.
>
> That work is done by someone else without deep knowledge or time to
> analyze every patchset for misc parts.
>
> The fixes are more important than the new device, so they should be
> submitted first.
Well explained, and I agree with Tom.
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (4 preceding siblings ...)
2022-04-27 18:17 ` [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-05-16 20:48 ` Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
` (4 more replies)
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
7 siblings, 5 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-16 20:48 UTC (permalink / raw)
To: dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section calling
the configure companion function for ACC100/101, taking the Pmon commit out
which is not directly required.
v2: Based on good feedback from Thomas and David,
now implementing the ACC101 PMD as a close derivative from
existing ACC100 PMD with hooks to have different behaviour based on variant.
This prevents code duplication and only rely on different functions and behaviour
when hardware requires or support differences.
Note that these are pending changes for ACC100 which would be specific to
that device and not ACC101 but these can be managed based on the new
implementation, ie. is_acc100() etc... (such incremental changes for ACC100
trending 22.11 but confirming this is future proof).
The serie also includes commits which were meant for ACC101 but are also
valuable for ACC100.
v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
This is a derivative from previous Mount Bryce ACC100 which includes silicon
improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
Nicolas Chautru (4):
baseband/acc100: introduce PMD for ACC101
baseband/acc100: modify validation code for ACC101
baseband/acc100: configuration of ACC101 from PF
baseband/acc100: add protection for some negative scenario
app/test-bbdev/test_bbdev_perf.c | 22 +-
doc/guides/bbdevs/acc101.rst | 237 ++++++++++++++
doc/guides/bbdevs/features/acc101.ini | 13 +
doc/guides/bbdevs/index.rst | 1 +
doc/guides/rel_notes/release_22_07.rst | 4 +
drivers/baseband/acc100/rte_acc100_cfg.h | 17 +
drivers/baseband/acc100/rte_acc100_pmd.c | 542 ++++++++++++++++++++++++++++++-
drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
drivers/baseband/acc100/rte_acc101_pmd.h | 65 ++++
drivers/baseband/acc100/version.map | 2 +-
10 files changed, 885 insertions(+), 24 deletions(-)
create mode 100644 doc/guides/bbdevs/acc101.rst
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
@ 2022-05-16 20:48 ` Nicolas Chautru
2022-05-19 19:55 ` Maxime Coquelin
2022-05-16 20:48 ` [PATCH v3 2/4] baseband/acc100: modify validation code " Nicolas Chautru
` (3 subsequent siblings)
4 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-16 20:48 UTC (permalink / raw)
To: dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Support for ACC101 as a derivative of ACC100.
Reusing existing code when possible.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
doc/guides/bbdevs/acc101.rst | 237 +++++++++++++++++++++++++++++++
doc/guides/bbdevs/features/acc101.ini | 13 ++
doc/guides/bbdevs/index.rst | 1 +
doc/guides/rel_notes/release_22_07.rst | 4 +
drivers/baseband/acc100/rte_acc100_pmd.c | 194 ++++++++++++++++++++++++-
drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
drivers/baseband/acc100/rte_acc101_pmd.h | 65 +++++++++
7 files changed, 515 insertions(+), 5 deletions(-)
create mode 100644 doc/guides/bbdevs/acc101.rst
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
diff --git a/doc/guides/bbdevs/acc101.rst b/doc/guides/bbdevs/acc101.rst
new file mode 100644
index 0000000..46c310b
--- /dev/null
+++ b/doc/guides/bbdevs/acc101.rst
@@ -0,0 +1,237 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2020 Intel Corporation
+
+Intel(R) ACC101 5G/4G FEC Poll Mode Driver
+==========================================
+
+The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an
+implementation of a VRAN FEC wireless acceleration function.
+This device is also known as Mount Cirrus.
+This is a follow-up to Mount Bryce (ACC100) and includes fixes, improved
+feature set for error scenarios and performance capacity increase.
+
+Features
+--------
+
+ACC101 5G/4G FEC PMD supports the following features:
+
+- LDPC Encode in the DL (5GNR)
+- LDPC Decode in the UL (5GNR)
+- Turbo Encode in the DL (4G)
+- Turbo Decode in the UL (4G)
+- 16 VFs per PF (physical device)
+- Maximum of 128 queues per VF
+- PCIe Gen-3 x16 Interface
+- MSI
+- SR-IOV
+
+ACC101 5G/4G FEC PMD supports the following BBDEV capabilities:
+
+* For the LDPC encode operation:
+ - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
+ - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass
+ - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS`` : if set then bypass interleaver
+
+* For the LDPC decode operation:
+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
+ - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination
+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding
+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory
+ - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits
+ - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
+ - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION`` : supports compression of the HARQ input/output
+ - ``RTE_BBDEV_LDPC_LLR_COMPRESSION`` : supports LLR input compression
+
+* For the turbo encode operation:
+ - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
+ - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass
+ - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts
+ - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` : set to bypass RV index
+ - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` : supports scatter-gather for input/output data
+
+* For the turbo decode operation:
+ - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)
+ - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave
+ - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts
+ - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported
+ - ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN`` : set if positive LLR encoder i/p is supported
+ - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding
+ - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP`` : option to drop the code block CRC after decoding
+ - ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` : set early termination feature
+ - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
+ - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity
+
+Installation
+------------
+
+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
+
+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
+The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
+hugepage configuration of a server may be examined using:
+
+.. code-block:: console
+
+ grep Huge* /proc/meminfo
+
+
+Initialization
+--------------
+
+When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+
+.. code-block:: console
+
+ sudo lspci -vd8086:57c4
+
+The physical and virtual functions are compatible with Linux UIO drivers:
+``vfio`` and ``igb_uio``. However, in order to work the ACC101 5G/4G
+FEC device first needs to be bound to one of these linux drivers through DPDK.
+
+
+Bind PF UIO driver(s)
+~~~~~~~~~~~~~~~~~~~~~
+
+Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
+``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
+
+The igb_uio driver may be bound to the PF PCI device using one of two methods:
+
+
+1. PCI functions (physical or virtual, depending on the use case) can be bound to
+the UIO driver by repeating this command for every function.
+
+.. code-block:: console
+
+ cd <dpdk-top-level-directory>
+ insmod ./build/kmod/igb_uio.ko
+ echo "8086 57c4" > /sys/bus/pci/drivers/igb_uio/new_id
+ lspci -vd8086:57c4
+
+
+2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
+
+.. code-block:: console
+
+ cd <dpdk-top-level-directory>
+ ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
+
+where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:57c4
+
+
+In a similar way the ACC101 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
+
+
+Enable Virtual Functions
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Now, it should be visible in the printouts that PCI PF is under igb_uio control
+"``Kernel driver in use: igb_uio``"
+
+To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
+
+.. code-block:: console
+
+ cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
+
+ where 0000\:<b>\:<d>.<f> is the PCI device ID
+
+
+To enable VFs via igb_uio, echo the number of virtual functions intended to
+enable to ``max_vfs`` file..
+
+.. code-block:: console
+
+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
+
+
+Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
+way it was done with the physical function previously.
+
+Enabling SR-IOV via vfio driver is pretty much the same, except that the file
+name is different:
+
+.. code-block:: console
+
+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
+
+
+Configure the VFs through PF
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The PCI virtual functions must be configured before working or getting assigned
+to VMs/Containers. The configuration involves allocating the number of hardware
+queues, priorities, load balance, bandwidth and other settings necessary for the
+device to perform FEC functions.
+
+This configuration needs to be executed at least once after reboot or PCI FLR and can
+be achieved by using the function ``acc101_configure()``, which sets up the
+parameters defined in ``acc100_conf`` structure.
+
+Test Application
+----------------
+
+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
+the functionality of ACC101 5G/4G FEC encode and decode, depending on the device's
+capabilities. The test application is located under app->test-bbdev folder and has the
+following options:
+
+.. code-block:: console
+
+ "-p", "--testapp-path": specifies path to the bbdev test app.
+ "-e", "--eal-params" : EAL arguments which are passed to the test app.
+ "-t", "--timeout" : Timeout in seconds (default=300).
+ "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
+ "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
+ "-n", "--num-ops" : Number of operations to process on device (default=32).
+ "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
+ "-s", "--snr" : SNR in dB used when generating LLRs for bler tests.
+ "-s", "--iter_max" : Number of iterations for LDPC decoder.
+ "-l", "--num-lcores" : Number of lcores to run (default=16).
+ "-i", "--init-device" : Initialise PF device with default values.
+
+
+To execute the test application tool using simple decode or encode data,
+type one of the following:
+
+.. code-block:: console
+
+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
+
+
+The test application ``test-bbdev.py``, supports the ability to configure the PF device with
+a default set of values, if the "-i" or "- -init-device" option is included. The default values
+are defined in test_bbdev_perf.c.
+
+
+Test Vectors
+~~~~~~~~~~~~
+
+In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
+a range of additional tests under the test_vectors folder, which may be useful. The results
+of these tests will depend on the ACC101 5G/4G FEC capabilities which may cause some
+testcases to be skipped, but no failure should be reported.
+
+
+Alternate Baseband Device configuration tool
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+On top of the embedded configuration feature supported in test-bbdev using "- -init-device"
+option mentioned above, there is also a tool available to perform that device configuration
+using a companion application.
+The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF
+and not only limited to the PF as captured above.
+
+See for more details: https://github.com/intel/pf-bb-config
+
+Specifically for the BBDEV ACC101 PMD, the command below can be used:
+
+.. code-block:: console
+
+ ./pf_bb_config ACC101 -c acc101/acc101_config_4vf_4g5g.cfg
+ ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -l 1 -v ./ldpc_dec_default.data
\ No newline at end of file
diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
new file mode 100644
index 0000000..0e2c21a
--- /dev/null
+++ b/doc/guides/bbdevs/features/acc101.ini
@@ -0,0 +1,13 @@
+;
+; Supported features of the 'acc101' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G) = Y
+Turbo Encoder (4G) = Y
+LDPC Decoder (5G) = Y
+LDPC Encoder (5G) = Y
+LLR/HARQ Compression = Y
+External DDR Access = Y
+HW Accelerated = Y
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index cedd706..e76883c 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -14,4 +14,5 @@ Baseband Device Drivers
fpga_lte_fec
fpga_5gnr_fec
acc100
+ acc101
la12xx
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 42a5f2d..ef9906b 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -55,6 +55,10 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Added Intel ACC101 baseband PMD.**
+
+ * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
+ * See the :doc:`../bbdevs/acc101` for more details.
Removed Items
-------------
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index de7e4bc..fca27ef 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -22,6 +22,7 @@
#include <rte_bbdev.h>
#include <rte_bbdev_pmd.h>
#include "rte_acc100_pmd.h"
+#include "rte_acc101_pmd.h"
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
@@ -1286,6 +1287,12 @@
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
}
+static inline bool
+is_acc100(struct acc100_queue *q)
+{
+ return (q->d->device_variant == ACC100_VARIANT);
+}
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -1412,6 +1419,139 @@
}
}
+/* Convert offset to harq index for harq_layout structure */
+static inline uint32_t hq_index(uint32_t offset)
+{
+ return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
+}
+
+/* Fill in a frame control word for LDPC decoding for ACC101 */
+static inline void
+acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout)
+{
+ uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
+ uint32_t harq_index;
+ uint32_t l;
+
+ fcw->qm = op->ldpc_dec.q_m;
+ fcw->nfiller = op->ldpc_dec.n_filler;
+ fcw->BG = (op->ldpc_dec.basegraph - 1);
+ fcw->Zc = op->ldpc_dec.z_c;
+ fcw->ncb = op->ldpc_dec.n_cb;
+ fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
+ op->ldpc_dec.rv_index);
+ if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
+ fcw->rm_e = op->ldpc_dec.cb_params.e;
+ else
+ fcw->rm_e = (op->ldpc_dec.tb_params.r <
+ op->ldpc_dec.tb_params.cab) ?
+ op->ldpc_dec.tb_params.ea :
+ op->ldpc_dec.tb_params.eb;
+
+ if (unlikely(check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
+ (op->ldpc_dec.harq_combined_input.length == 0))) {
+ rte_bbdev_log(WARNING, "Null HARQ input size provided");
+ /* Disable HARQ input in that case to carry forward */
+ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+ }
+
+ fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+ fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+ fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+ fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DECODE_BYPASS);
+ fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
+ if (op->ldpc_dec.q_m == 1) {
+ fcw->bypass_intlv = 1;
+ fcw->qm = 2;
+ }
+ fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_LLR_COMPRESSION);
+ harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
+ if (fcw->hcin_en > 0) {
+ harq_in_length = op->ldpc_dec.harq_combined_input.length;
+ if (fcw->hcin_decomp_mode > 0)
+ harq_in_length = harq_in_length * 8 / 6;
+ harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
+ - op->ldpc_dec.n_filler);
+ /* Alignment on next 64B - Already enforced from HC output */
+ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
+ fcw->hcin_size0 = harq_in_length;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ } else {
+ fcw->hcin_size0 = 0;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ }
+
+ fcw->itmax = op->ldpc_dec.iter_max;
+ fcw->itstop = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+ fcw->synd_precoder = fcw->itstop;
+ /*
+ * These are all implicitly set
+ * fcw->synd_post = 0;
+ * fcw->so_en = 0;
+ * fcw->so_bypass_rm = 0;
+ * fcw->so_bypass_intlv = 0;
+ * fcw->dec_convllr = 0;
+ * fcw->hcout_convllr = 0;
+ * fcw->hcout_size1 = 0;
+ * fcw->so_it = 0;
+ * fcw->hcout_offset = 0;
+ * fcw->negstop_th = 0;
+ * fcw->negstop_it = 0;
+ * fcw->negstop_en = 0;
+ * fcw->gain_i = 1;
+ * fcw->gain_h = 1;
+ */
+ if (fcw->hcout_en > 0) {
+ parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
+ * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
+ k0_p = (fcw->k0 > parity_offset) ?
+ fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
+ ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
+ l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
+ harq_out_length = (uint16_t) fcw->hcin_size0;
+ harq_out_length = RTE_MAX(harq_out_length, l);
+ /* Cannot exceed the pruned Ncb circular buffer */
+ harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+ /* Alignment on next 64B */
+ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
+ fcw->hcout_size0 = harq_out_length;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ harq_layout[harq_index].offset = fcw->hcout_offset;
+ harq_layout[harq_index].size0 = fcw->hcout_size0;
+ } else {
+ fcw->hcout_size0 = 0;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ }
+}
+
+static inline void
+acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout, struct acc100_queue *q)
+{
+ if (is_acc100(q))
+ return acc100_fcw_ld_fill(op, fcw, harq_layout);
+ else
+ return acc101_fcw_ld_fill(op, fcw, harq_layout);
+}
+
+
/**
* Fills descriptor with data pointers of one block type.
*
@@ -2960,7 +3100,7 @@
struct acc100_fcw_ld *fcw;
uint32_t seg_total_left;
fcw = &desc->req.fcw_ld;
- acc100_fcw_ld_fill(op, fcw, harq_layout);
+ acc10x_fcw_ld_fill(op, fcw, harq_layout, q);
/* Special handling when overusing mbuf */
if (fcw->rm_e < ACC100_MAX_E_MBUF)
@@ -3027,7 +3167,7 @@
desc = q->ring_addr + desc_idx;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
- acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
+ acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q);
input = op->ldpc_dec.input.data;
h_output_head = h_output = op->ldpc_dec.hard_output.data;
@@ -4139,9 +4279,17 @@
dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
- ((struct acc100_device *) dev->data->dev_private)->pf_device =
- !strcmp(drv->driver.name,
- RTE_STR(ACC100PF_DRIVER_NAME));
+ if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) ||
+ (!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
+ } else {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
+ }
+
((struct acc100_device *) dev->data->dev_private)->mmio_base =
pci_dev->mem_resource[0].addr;
@@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);
RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);
+/* ACC101 PCI PF address map */
+static struct rte_pci_id pci_id_acc101_pf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+/* ACC101 PCI VF address map */
+static struct rte_pci_id pci_id_acc101_vf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+
+static struct rte_pci_driver acc101_pci_pf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_pf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+static struct rte_pci_driver acc101_pci_vf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_vf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);
+RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);
+
/*
* Workaround implementation to fix the power on status of some 5GUL engines
* This requires DMA permission if ported outside DPDK
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index cbcece2..6438031 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -22,6 +22,9 @@
#define rte_bbdev_log_debug(fmt, ...)
#endif
+#define ACC100_VARIANT 0
+#define ACC101_VARIANT 1
+
/* ACC100 PF and VF driver names */
#define ACC100PF_DRIVER_NAME intel_acc100_pf
#define ACC100VF_DRIVER_NAME intel_acc100_vf
@@ -67,6 +70,8 @@
#define ACC100_HARQ_LAYOUT (64*1024*1024)
/* Assume offset for HARQ in memory */
#define ACC100_HARQ_OFFSET (32*1024)
+#define ACC100_HARQ_OFFSET_SHIFT 15
+#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
#define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
/* Number of Virtual Functions ACC100 supports */
@@ -590,6 +595,7 @@ struct acc100_device {
uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
bool pf_device; /**< True if this is a PF ACC100 device */
bool configured; /**< True if this ACC100 device is configured */
+ uint16_t device_variant; /**< Device variant */
};
/**
diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h
new file mode 100644
index 0000000..1c57f63
--- /dev/null
+++ b/drivers/baseband/acc100/rte_acc101_pmd.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+/* ACC101 PF and VF driver names */
+#define ACC101PF_DRIVER_NAME intel_acc101_pf
+#define ACC101VF_DRIVER_NAME intel_acc101_vf
+
+/* ACC101 PCI vendor & device IDs */
+#define RTE_ACC101_VENDOR_ID (0x8086)
+#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
+#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
+
+/* Define as 1 to use only a single FEC engine */
+#ifndef RTE_ACC101_SINGLE_FEC
+#define RTE_ACC101_SINGLE_FEC 0
+#endif
+
+/* Values used in writing to the registers */
+#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
+
+/* Number of Virtual Functions ACC101 supports */
+#define ACC101_NUM_VFS 16
+#define ACC101_NUM_QGRPS 8
+#define ACC101_NUM_AQS 16
+/* All ACC101 Registers alignment are 32bits = 4B */
+#define ACC101_BYTES_IN_WORD 4
+
+#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
+#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
+#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS Mon */
+#define ACC101_TMPL_PRI_0 0x03020100
+#define ACC101_TMPL_PRI_1 0x07060504
+#define ACC101_TMPL_PRI_2 0x0b0a0908
+#define ACC101_TMPL_PRI_3 0x0f0e0d0c
+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
+
+#define ACC101_NUM_TMPL 32
+/* Mapping of signals for the available engines */
+#define ACC101_SIG_UL_5G 0
+#define ACC101_SIG_UL_5G_LAST 8
+#define ACC101_SIG_DL_5G 13
+#define ACC101_SIG_DL_5G_LAST 15
+#define ACC101_SIG_UL_4G 16
+#define ACC101_SIG_UL_4G_LAST 19
+#define ACC101_SIG_DL_4G 27
+#define ACC101_SIG_DL_4G_LAST 31
+#define ACC101_NUM_ACCS 5
+#define ACC101_PF_VAL 2
+
+/* ACC101 Configuration */
+#define ACC101_CFG_DMA_ERROR 0x3D7
+#define ACC101_CFG_AXI_CACHE 0x11
+#define ACC101_CFG_QMGR_HI_P 0x0F0F
+#define ACC101_CFG_PCI_AXI 0xC003
+#define ACC101_CFG_PCI_BRIDGE 0x40006033
+#define ACC101_ENGINE_OFFSET 0x1000
+#define ACC101_LONG_WAIT 1000
+#define ACC101_GPEX_AXIMAP_NUM 17
+#define ACC101_CLOCK_GATING_EN 0x30000
+#define ACC101_DMA_INBOUND 0x104
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC101_HARQ_DDR (512 * 1)
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v3 2/4] baseband/acc100: modify validation code for ACC101
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-16 20:48 ` Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
` (2 subsequent siblings)
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-16 20:48 UTC (permalink / raw)
To: dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
The validation requirement is different for the two
devices.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++----------
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index fca27ef..daf2ce0 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1293,6 +1293,14 @@
return (q->d->device_variant == ACC100_VARIANT);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+static inline bool
+validate_op_required(struct acc100_queue *q)
+{
+ return is_acc100(q);
+}
+#endif
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -2187,8 +2195,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo encoder parameters */
static inline int
-validate_enc_op(struct rte_bbdev_enc_op *op)
+validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
@@ -2325,8 +2335,10 @@ static inline uint32_t hq_index(uint32_t offset)
}
/* Validates LDPC encoder parameters */
static inline int
-validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
+validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
if (op->mempool == NULL) {
@@ -2378,8 +2390,10 @@ static inline uint32_t hq_index(uint32_t offset)
/* Validates LDPC decoder parameters */
static inline int
-validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
+validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
if (op->mempool == NULL) {
@@ -2434,7 +2448,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2488,7 +2502,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(ops[0]) == -1) {
+ if (validate_ldpc_enc_op(ops[0], q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2550,7 +2564,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(op) == -1) {
+ if (validate_ldpc_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2607,7 +2621,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2680,8 +2694,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo decoder parameters */
static inline int
-validate_dec_op(struct rte_bbdev_dec_op *op)
+validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
@@ -2827,7 +2843,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
@@ -3052,7 +3068,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3156,7 +3172,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3246,7 +3262,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 2/4] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-16 20:48 ` Nicolas Chautru
2022-05-19 20:13 ` Maxime Coquelin
2022-05-16 20:48 ` [PATCH v3 4/4] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-19 19:51 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Tom Rix
4 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-16 20:48 UTC (permalink / raw)
To: dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Adding companion function specific to ACC100 and it
can be called from bbdev-test when running from PF.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 22 ++-
drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++
drivers/baseband/acc100/version.map | 2 +-
4 files changed, 336 insertions(+), 7 deletions(-)
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 0fa119a..b10b93d 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -63,6 +63,8 @@
#define ACC100_QMGR_INVALID_IDX -1
#define ACC100_QMGR_RR 1
#define ACC100_QOS_GBR 0
+#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
+#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
#endif
#define OPS_CACHE_SIZE 256U
@@ -711,11 +713,12 @@ typedef int (test_case_function)(struct active_device *ad,
#endif
#ifdef RTE_BASEBAND_ACC100
if ((get_init_device() == true) &&
- (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
+ ((!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) ||
+ (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))) {
struct rte_acc100_conf conf;
unsigned int i;
- printf("Configure ACC100 FEC Driver %s with default values\n",
+ printf("Configure ACC10X FEC Driver %s with default values\n",
info->drv.driver_name);
/* clear default configuration before initialization */
@@ -760,10 +763,17 @@ typedef int (test_case_function)(struct active_device *ad,
conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
/* setup PF with configuration information */
- ret = rte_acc100_configure(info->dev_name, &conf);
- TEST_ASSERT_SUCCESS(ret,
- "Failed to configure ACC100 PF for bbdev %s",
- info->dev_name);
+ if (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) {
+ ret = rte_acc100_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC100 PF for bbdev %s",
+ info->dev_name);
+ } else {
+ ret = rte_acc101_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC101 PF for bbdev %s",
+ info->dev_name);
+ }
}
#endif
/* Let's refresh this now this is configured */
diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
index d233e42..2e3c43f 100644
--- a/drivers/baseband/acc100/rte_acc100_cfg.h
+++ b/drivers/baseband/acc100/rte_acc100_cfg.h
@@ -106,6 +106,23 @@ struct rte_acc100_conf {
int
rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
+/**
+ * Configure a ACC101 device
+ *
+ * @param dev_name
+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ * It can also be retrieved for a bbdev device from the dev_name field in the
+ * rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ * Configuration to apply to ACC101 HW.
+ *
+ * @return
+ * Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index daf2ce0..b03cedc 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
+
+
+/* Initial configuration of a ACC101 device prior to running configure() */
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc101_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc100_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+
+ /* PCIe Bridge configuration */
+ acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
+ for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
+ acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
+
+ /* Prevent blocking AXI read on BRESP for AXI Write */
+ address = HwPfPcieGpexAxiPioControl;
+ value = ACC101_CFG_PCI_AXI;
+ acc100_reg_write(d, address, value);
+
+ /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* Set the default 5GDL DMA configuration */
+ acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
+
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC101_CLOCK_GATING_EN;
+ acc100_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC101_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc100_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC101_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc100_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ address = HWPfDmaConfig1Reg;
+ int alen_r = 0xF;
+ int alen_w = 0x7;
+ value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
+ acc100_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc100_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_1;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_2;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_3;
+ acc100_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC101_CFG_QMGR_HI_P;
+ acc100_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_4G;
+ template_idx <= ACC101_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_5G;
+ template_idx <= ACC101_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg +
+ ACC101_ENGINE_OFFSET * template_idx;
+ status = (acc100_reg_read(d, address) >> 4) & 0xF;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc100_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc100_reg_write(d, address, 0);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ printf("Number of 5GUL engines %d\n", numEngines);
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_4G;
+ template_idx <= ACC101_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_5G;
+ template_idx <= ACC101_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ address = HWPfQmgrGrpFunction0;
+ value = 0;
+ for (qg_idx = 0; qg_idx < 8; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc]<<(qg_idx * 4);
+ }
+ acc100_reg_write(d, address, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC101_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc100_reg_write(d, address, value);
+ }
+ }
+
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC101_BYTES_IN_WORD + qg_idx
+ * ACC101_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc100_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC101_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
+ acc100_reg_write(d, address, value);
+ /* Explicitly releasing AXI after PF Mode and 2 ms */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc100_reg_write(d, address, value);
+
+ /* HARQ DDR Configuration */
+ unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfDmaVfDdrBaseRw + vf_idx
+ * 0x10;
+ value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
+ (ddrSizeInMb - 1);
+ acc100_reg_write(d, address, value);
+ }
+ usleep(ACC101_LONG_WAIT);
+
+ rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
+ return 0;
+}
diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map
index 40604c7..37b850f 100644
--- a/drivers/baseband/acc100/version.map
+++ b/drivers/baseband/acc100/version.map
@@ -6,5 +6,5 @@ EXPERIMENTAL {
global:
rte_acc100_configure;
-
+ rte_acc101_configure;
};
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v3 4/4] baseband/acc100: add protection for some negative scenario
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (2 preceding siblings ...)
2022-05-16 20:48 ` [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-05-16 20:48 ` Nicolas Chautru
2022-05-19 19:51 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Tom Rix
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-16 20:48 UTC (permalink / raw)
To: dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Catch exception in PMD in case of invalid input parameter.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index b03cedc..b59c9d7 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1237,6 +1237,8 @@
return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
}
/* LBRM case - includes a division by N */
+ if (unlikely(z_c == 0))
+ return 0;
if (rv_index == 1)
return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
/ n) * z_c;
@@ -1912,6 +1914,10 @@ static inline uint32_t hq_index(uint32_t offset)
/* Soft output */
if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
+ if (op->turbo_dec.soft_output.data == 0) {
+ rte_bbdev_log(ERR, "Soft output is not defined");
+ return -1;
+ }
if (check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_EQUALIZER))
*s_out_length = e;
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (3 preceding siblings ...)
2022-05-16 20:48 ` [PATCH v3 4/4] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-05-19 19:51 ` Tom Rix
4 siblings, 0 replies; 84+ messages in thread
From: Tom Rix @ 2022-05-19 19:51 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
On 5/16/22 1:48 PM, Nicolas Chautru wrote:
> v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section calling
> the configure companion function for ACC100/101, taking the Pmon commit out
> which is not directly required.
These address some of my comments.
The others, mostly around the treating accXXX as a family of devices and
refactoring the common parts out have not been.
Tom
>
> v2: Based on good feedback from Thomas and David,
> now implementing the ACC101 PMD as a close derivative from
> existing ACC100 PMD with hooks to have different behaviour based on variant.
> This prevents code duplication and only rely on different functions and behaviour
> when hardware requires or support differences.
> Note that these are pending changes for ACC100 which would be specific to
> that device and not ACC101 but these can be managed based on the new
> implementation, ie. is_acc100() etc... (such incremental changes for ACC100
> trending 22.11 but confirming this is future proof).
> The serie also includes commits which were meant for ACC101 but are also
> valuable for ACC100.
>
> v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
> This is a derivative from previous Mount Bryce ACC100 which includes silicon
> improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
>
> Nicolas Chautru (4):
> baseband/acc100: introduce PMD for ACC101
> baseband/acc100: modify validation code for ACC101
> baseband/acc100: configuration of ACC101 from PF
> baseband/acc100: add protection for some negative scenario
>
> app/test-bbdev/test_bbdev_perf.c | 22 +-
> doc/guides/bbdevs/acc101.rst | 237 ++++++++++++++
> doc/guides/bbdevs/features/acc101.ini | 13 +
> doc/guides/bbdevs/index.rst | 1 +
> doc/guides/rel_notes/release_22_07.rst | 4 +
> drivers/baseband/acc100/rte_acc100_cfg.h | 17 +
> drivers/baseband/acc100/rte_acc100_pmd.c | 542 ++++++++++++++++++++++++++++++-
> drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
> drivers/baseband/acc100/rte_acc101_pmd.h | 65 ++++
> drivers/baseband/acc100/version.map | 2 +-
> 10 files changed, 885 insertions(+), 24 deletions(-)
> create mode 100644 doc/guides/bbdevs/acc101.rst
> create mode 100644 doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
>
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101
2022-05-16 20:48 ` [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-19 19:55 ` Maxime Coquelin
0 siblings, 0 replies; 84+ messages in thread
From: Maxime Coquelin @ 2022-05-19 19:55 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
Hi Nicolas,
On 5/16/22 22:48, Nicolas Chautru wrote:
> Support for ACC101 as a derivative of ACC100.
> Reusing existing code when possible.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> doc/guides/bbdevs/acc101.rst | 237 +++++++++++++++++++++++++++++++
> doc/guides/bbdevs/features/acc101.ini | 13 ++
> doc/guides/bbdevs/index.rst | 1 +
> doc/guides/rel_notes/release_22_07.rst | 4 +
> drivers/baseband/acc100/rte_acc100_pmd.c | 194 ++++++++++++++++++++++++-
> drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
> drivers/baseband/acc100/rte_acc101_pmd.h | 65 +++++++++
> 7 files changed, 515 insertions(+), 5 deletions(-)
> create mode 100644 doc/guides/bbdevs/acc101.rst
> create mode 100644 doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
>
It seems most of Tom's comments on v2 have not been addressed.
Overall, ACC100 & ACC101 are very similar, I think it does not make
sense in to have two drivers being declared and two documentation files.
> diff --git a/doc/guides/bbdevs/acc101.rst b/doc/guides/bbdevs/acc101.rst
> new file mode 100644
> index 0000000..46c310b
> --- /dev/null
> +++ b/doc/guides/bbdevs/acc101.rst
> @@ -0,0 +1,237 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> + Copyright(c) 2020 Intel Corporation
> +
> +Intel(R) ACC101 5G/4G FEC Poll Mode Driver
> +==========================================
> +
> +The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an
> +implementation of a VRAN FEC wireless acceleration function.
> +This device is also known as Mount Cirrus.
> +This is a follow-up to Mount Bryce (ACC100) and includes fixes, improved
> +feature set for error scenarios and performance capacity increase.
> +
> +Features
> +--------
> +
> +ACC101 5G/4G FEC PMD supports the following features:
> +
> +- LDPC Encode in the DL (5GNR)
> +- LDPC Decode in the UL (5GNR)
> +- Turbo Encode in the DL (4G)
> +- Turbo Decode in the UL (4G)
> +- 16 VFs per PF (physical device)
> +- Maximum of 128 queues per VF
> +- PCIe Gen-3 x16 Interface
> +- MSI
> +- SR-IOV
> +
> +ACC101 5G/4G FEC PMD supports the following BBDEV capabilities:
> +
> +* For the LDPC encode operation:
> + - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
> + - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass
> + - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS`` : if set then bypass interleaver
> +
> +* For the LDPC decode operation:
> + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
> + - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination
> + - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding
> + - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
> + - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory
> + - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits
> + - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
> + - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION`` : supports compression of the HARQ input/output
> + - ``RTE_BBDEV_LDPC_LLR_COMPRESSION`` : supports LLR input compression
> +
> +* For the turbo encode operation:
> + - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
> + - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass
> + - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts
> + - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` : set to bypass RV index
> + - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` : supports scatter-gather for input/output data
> +
> +* For the turbo decode operation:
> + - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)
> + - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave
> + - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts
> + - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported
> + - ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN`` : set if positive LLR encoder i/p is supported
> + - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding
> + - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP`` : option to drop the code block CRC after decoding
> + - ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` : set early termination feature
> + - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data
> + - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity
> +
> +Installation
> +------------
> +
> +Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
> +
> +DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
> +The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
> +hugepage configuration of a server may be examined using:
> +
> +.. code-block:: console
> +
> + grep Huge* /proc/meminfo
> +
> +
> +Initialization
> +--------------
> +
> +When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
> +
> +.. code-block:: console
> +
> + sudo lspci -vd8086:57c4
> +
> +The physical and virtual functions are compatible with Linux UIO drivers:
> +``vfio`` and ``igb_uio``. However, in order to work the ACC101 5G/4G
> +FEC device first needs to be bound to one of these linux drivers through DPDK.
> +
> +
> +Bind PF UIO driver(s)
> +~~~~~~~~~~~~~~~~~~~~~
> +
> +Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
> +``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
> +
> +The igb_uio driver may be bound to the PF PCI device using one of two methods:
> +
> +
> +1. PCI functions (physical or virtual, depending on the use case) can be bound to
> +the UIO driver by repeating this command for every function.
> +
> +.. code-block:: console
> +
> + cd <dpdk-top-level-directory>
> + insmod ./build/kmod/igb_uio.ko
> + echo "8086 57c4" > /sys/bus/pci/drivers/igb_uio/new_id
> + lspci -vd8086:57c4
> +
> +
> +2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
> +
> +.. code-block:: console
> +
> + cd <dpdk-top-level-directory>
> + ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
> +
> +where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:57c4
> +
> +
> +In a similar way the ACC101 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
> +
> +
> +Enable Virtual Functions
> +~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +Now, it should be visible in the printouts that PCI PF is under igb_uio control
> +"``Kernel driver in use: igb_uio``"
> +
> +To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
> +
> +.. code-block:: console
> +
> + cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
> +
> + where 0000\:<b>\:<d>.<f> is the PCI device ID
> +
> +
> +To enable VFs via igb_uio, echo the number of virtual functions intended to
> +enable to ``max_vfs`` file..
> +
> +.. code-block:: console
> +
> + echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
> +
> +
> +Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
> +way it was done with the physical function previously.
> +
> +Enabling SR-IOV via vfio driver is pretty much the same, except that the file
> +name is different:
> +
> +.. code-block:: console
> +
> + echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
> +
> +
> +Configure the VFs through PF
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +The PCI virtual functions must be configured before working or getting assigned
> +to VMs/Containers. The configuration involves allocating the number of hardware
> +queues, priorities, load balance, bandwidth and other settings necessary for the
> +device to perform FEC functions.
> +
> +This configuration needs to be executed at least once after reboot or PCI FLR and can
> +be achieved by using the function ``acc101_configure()``, which sets up the
> +parameters defined in ``acc100_conf`` structure.
> +
> +Test Application
> +----------------
> +
> +BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
> +the functionality of ACC101 5G/4G FEC encode and decode, depending on the device's
> +capabilities. The test application is located under app->test-bbdev folder and has the
> +following options:
> +
> +.. code-block:: console
> +
> + "-p", "--testapp-path": specifies path to the bbdev test app.
> + "-e", "--eal-params" : EAL arguments which are passed to the test app.
> + "-t", "--timeout" : Timeout in seconds (default=300).
> + "-c", "--test-cases" : Defines test cases to run. Run all if not specified.
> + "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
> + "-n", "--num-ops" : Number of operations to process on device (default=32).
> + "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32).
> + "-s", "--snr" : SNR in dB used when generating LLRs for bler tests.
> + "-s", "--iter_max" : Number of iterations for LDPC decoder.
> + "-l", "--num-lcores" : Number of lcores to run (default=16).
> + "-i", "--init-device" : Initialise PF device with default values.
> +
> +
> +To execute the test application tool using simple decode or encode data,
> +type one of the following:
> +
> +.. code-block:: console
> +
> + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
> + ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
> +
> +
> +The test application ``test-bbdev.py``, supports the ability to configure the PF device with
> +a default set of values, if the "-i" or "- -init-device" option is included. The default values
> +are defined in test_bbdev_perf.c.
> +
> +
> +Test Vectors
> +~~~~~~~~~~~~
> +
> +In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
> +a range of additional tests under the test_vectors folder, which may be useful. The results
> +of these tests will depend on the ACC101 5G/4G FEC capabilities which may cause some
> +testcases to be skipped, but no failure should be reported.
> +
> +
> +Alternate Baseband Device configuration tool
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +On top of the embedded configuration feature supported in test-bbdev using "- -init-device"
> +option mentioned above, there is also a tool available to perform that device configuration
> +using a companion application.
> +The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF
> +and not only limited to the PF as captured above.
> +
> +See for more details: https://github.com/intel/pf-bb-config
> +
> +Specifically for the BBDEV ACC101 PMD, the command below can be used:
> +
> +.. code-block:: console
> +
> + ./pf_bb_config ACC101 -c acc101/acc101_config_4vf_4g5g.cfg
> + ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -l 1 -v ./ldpc_dec_default.data
> \ No newline at end of file
> diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
> new file mode 100644
> index 0000000..0e2c21a
> --- /dev/null
> +++ b/doc/guides/bbdevs/features/acc101.ini
> @@ -0,0 +1,13 @@
> +;
> +; Supported features of the 'acc101' bbdev driver.
> +;
> +; Refer to default.ini for the full list of available PMD features.
> +;
> +[Features]
> +Turbo Decoder (4G) = Y
> +Turbo Encoder (4G) = Y
> +LDPC Decoder (5G) = Y
> +LDPC Encoder (5G) = Y
> +LLR/HARQ Compression = Y
> +External DDR Access = Y
> +HW Accelerated = Y
> diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
> index cedd706..e76883c 100644
> --- a/doc/guides/bbdevs/index.rst
> +++ b/doc/guides/bbdevs/index.rst
> @@ -14,4 +14,5 @@ Baseband Device Drivers
> fpga_lte_fec
> fpga_5gnr_fec
> acc100
> + acc101
> la12xx
> diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
> index 42a5f2d..ef9906b 100644
> --- a/doc/guides/rel_notes/release_22_07.rst
> +++ b/doc/guides/rel_notes/release_22_07.rst
> @@ -55,6 +55,10 @@ New Features
> Also, make sure to start the actual text at the margin.
> =======================================================
>
> +* **Added Intel ACC101 baseband PMD.**
> +
> + * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
> + * See the :doc:`../bbdevs/acc101` for more details.
>
> Removed Items
> -------------
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index de7e4bc..fca27ef 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -22,6 +22,7 @@
> #include <rte_bbdev.h>
> #include <rte_bbdev_pmd.h>
> #include "rte_acc100_pmd.h"
> +#include "rte_acc101_pmd.h"
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
> @@ -1286,6 +1287,12 @@
> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> }
>
> +static inline bool
> +is_acc100(struct acc100_queue *q)
> +{
> + return (q->d->device_variant == ACC100_VARIANT);
> +}
You should rely on the PCI ID to differentiate IMHO
> +
> /* Fill in a frame control word for LDPC decoding. */
> static inline void
> acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> @@ -1412,6 +1419,139 @@
> }
> }
>
> +/* Convert offset to harq index for harq_layout structure */
> +static inline uint32_t hq_index(uint32_t offset)
> +{
> + return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
> +}
> +
> +/* Fill in a frame control word for LDPC decoding for ACC101 */
> +static inline void
> +acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> + union acc100_harq_layout_data *harq_layout)
> +{
This function is quite similar to the acc100 one, it should be possible
to do it in a single function to avoid duplication and rely on the
device ID when something specific is to be done.
> + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
> + uint32_t harq_index;
> + uint32_t l;
> +
> + fcw->qm = op->ldpc_dec.q_m;
> + fcw->nfiller = op->ldpc_dec.n_filler;
> + fcw->BG = (op->ldpc_dec.basegraph - 1);
> + fcw->Zc = op->ldpc_dec.z_c;
> + fcw->ncb = op->ldpc_dec.n_cb;
> + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
> + op->ldpc_dec.rv_index);
> + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
> + fcw->rm_e = op->ldpc_dec.cb_params.e;
> + else
> + fcw->rm_e = (op->ldpc_dec.tb_params.r <
> + op->ldpc_dec.tb_params.cab) ?
> + op->ldpc_dec.tb_params.ea :
> + op->ldpc_dec.tb_params.eb;
> +
> + if (unlikely(check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
> + (op->ldpc_dec.harq_combined_input.length == 0))) {
> + rte_bbdev_log(WARNING, "Null HARQ input size provided");
> + /* Disable HARQ input in that case to carry forward */
> + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> + }
> +
> + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
> + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
> + fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
> + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_DECODE_BYPASS);
> + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
> + if (op->ldpc_dec.q_m == 1) {
> + fcw->bypass_intlv = 1;
> + fcw->qm = 2;
> + }
> + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_LLR_COMPRESSION);
> + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
> + if (fcw->hcin_en > 0) {
> + harq_in_length = op->ldpc_dec.harq_combined_input.length;
> + if (fcw->hcin_decomp_mode > 0)
> + harq_in_length = harq_in_length * 8 / 6;
> + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
> + - op->ldpc_dec.n_filler);
> + /* Alignment on next 64B - Already enforced from HC output */
> + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> + fcw->hcin_size0 = harq_in_length;
> + fcw->hcin_offset = 0;
> + fcw->hcin_size1 = 0;
> + } else {
> + fcw->hcin_size0 = 0;
> + fcw->hcin_offset = 0;
> + fcw->hcin_size1 = 0;
> + }
> +
> + fcw->itmax = op->ldpc_dec.iter_max;
> + fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
> + fcw->synd_precoder = fcw->itstop;
> + /*
> + * These are all implicitly set
> + * fcw->synd_post = 0;
> + * fcw->so_en = 0;
> + * fcw->so_bypass_rm = 0;
> + * fcw->so_bypass_intlv = 0;
> + * fcw->dec_convllr = 0;
> + * fcw->hcout_convllr = 0;
> + * fcw->hcout_size1 = 0;
> + * fcw->so_it = 0;
> + * fcw->hcout_offset = 0;
> + * fcw->negstop_th = 0;
> + * fcw->negstop_it = 0;
> + * fcw->negstop_en = 0;
> + * fcw->gain_i = 1;
> + * fcw->gain_h = 1;
> + */
> + if (fcw->hcout_en > 0) {
> + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
> + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
> + k0_p = (fcw->k0 > parity_offset) ?
> + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
> + ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
> + harq_out_length = (uint16_t) fcw->hcin_size0;
> + harq_out_length = RTE_MAX(harq_out_length, l);
> + /* Cannot exceed the pruned Ncb circular buffer */
> + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> + /* Alignment on next 64B */
> + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> + fcw->hcout_size0 = harq_out_length;
> + fcw->hcout_size1 = 0;
> + fcw->hcout_offset = 0;
> + harq_layout[harq_index].offset = fcw->hcout_offset;
> + harq_layout[harq_index].size0 = fcw->hcout_size0;
> + } else {
> + fcw->hcout_size0 = 0;
> + fcw->hcout_size1 = 0;
> + fcw->hcout_offset = 0;
> + }
> +}
> +
> +static inline void
> +acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> + union acc100_harq_layout_data *harq_layout, struct acc100_queue *q)
> +{
> + if (is_acc100(q))
> + return acc100_fcw_ld_fill(op, fcw, harq_layout);
> + else
> + return acc101_fcw_ld_fill(op, fcw, harq_layout);
> +}
> +
> +
> /**
> * Fills descriptor with data pointers of one block type.
> *
> @@ -2960,7 +3100,7 @@
> struct acc100_fcw_ld *fcw;
> uint32_t seg_total_left;
> fcw = &desc->req.fcw_ld;
> - acc100_fcw_ld_fill(op, fcw, harq_layout);
> + acc10x_fcw_ld_fill(op, fcw, harq_layout, q);
>
> /* Special handling when overusing mbuf */
> if (fcw->rm_e < ACC100_MAX_E_MBUF)
> @@ -3027,7 +3167,7 @@
> desc = q->ring_addr + desc_idx;
> uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
> union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
> - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
> + acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q);
>
> input = op->ldpc_dec.input.data;
> h_output_head = h_output = op->ldpc_dec.hard_output.data;
> @@ -4139,9 +4279,17 @@
> dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
> dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
>
> - ((struct acc100_device *) dev->data->dev_private)->pf_device =
> - !strcmp(drv->driver.name,
> - RTE_STR(ACC100PF_DRIVER_NAME));
> + if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) ||
> + (!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) {
> + ((struct acc100_device *) dev->data->dev_private)->pf_device =
> + !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
> + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
> + } else {
> + ((struct acc100_device *) dev->data->dev_private)->pf_device =
> + !strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME));
> + ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
Better to rely on the PCI device ID than introducing a new field.
> + }
> +
> ((struct acc100_device *) dev->data->dev_private)->mmio_base =
> pci_dev->mem_resource[0].addr;
>
> @@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
> RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);
> RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);
>
> +/* ACC101 PCI PF address map */
> +static struct rte_pci_id pci_id_acc101_pf_map[] = {
> + {
> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID)
> + },
> + {.device_id = 0},
> +};
> +
> +/* ACC101 PCI VF address map */
> +static struct rte_pci_id pci_id_acc101_vf_map[] = {
> + {
> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID)
> + },
> + {.device_id = 0},
> +};
> +
> +
> +static struct rte_pci_driver acc101_pci_pf_driver = {
> + .probe = acc100_pci_probe,
> + .remove = acc100_pci_remove,
> + .id_table = pci_id_acc101_pf_map,
> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING
> +};
> +
> +static struct rte_pci_driver acc101_pci_vf_driver = {
> + .probe = acc100_pci_probe,
> + .remove = acc100_pci_remove,
> + .id_table = pci_id_acc101_vf_map,
> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING
> +};
> +
> +RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver);
> +RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);
> +RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);
> +RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);
> +
> /*
> * Workaround implementation to fix the power on status of some 5GUL engines
> * This requires DMA permission if ported outside DPDK
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
> index cbcece2..6438031 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> @@ -22,6 +22,9 @@
> #define rte_bbdev_log_debug(fmt, ...)
> #endif
>
> +#define ACC100_VARIANT 0
> +#define ACC101_VARIANT 1
> +
> /* ACC100 PF and VF driver names */
> #define ACC100PF_DRIVER_NAME intel_acc100_pf
> #define ACC100VF_DRIVER_NAME intel_acc100_vf
> @@ -67,6 +70,8 @@
> #define ACC100_HARQ_LAYOUT (64*1024*1024)
> /* Assume offset for HARQ in memory */
> #define ACC100_HARQ_OFFSET (32*1024)
> +#define ACC100_HARQ_OFFSET_SHIFT 15
> +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
> /* Mask used to calculate an index in an Info Ring array (not a byte offset) */
> #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
> /* Number of Virtual Functions ACC100 supports */
> @@ -590,6 +595,7 @@ struct acc100_device {
> uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
> bool pf_device; /**< True if this is a PF ACC100 device */
> bool configured; /**< True if this ACC100 device is configured */
> + uint16_t device_variant; /**< Device variant */
> };
>
> /**
> diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h
> new file mode 100644
> index 0000000..1c57f63
> --- /dev/null
> +++ b/drivers/baseband/acc100/rte_acc101_pmd.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +/* ACC101 PF and VF driver names */
> +#define ACC101PF_DRIVER_NAME intel_acc101_pf
> +#define ACC101VF_DRIVER_NAME intel_acc101_vf
> +
> +/* ACC101 PCI vendor & device IDs */
> +#define RTE_ACC101_VENDOR_ID (0x8086)
> +#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
> +#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
> +
> +/* Define as 1 to use only a single FEC engine */
> +#ifndef RTE_ACC101_SINGLE_FEC
> +#define RTE_ACC101_SINGLE_FEC 0
> +#endif
It should be configurable via a dedicated devarg or via the struct
rte_acc100_conf struct, we shouldn't have to recompile to change the
device configuration.
> +
> +/* Values used in writing to the registers */
> +#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
This define is never used AFAICS, is that expected?
./drivers/baseband/acc100/rte_acc100_pmd.h:63:#define
ACC100_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
./drivers/baseband/acc100/rte_acc101_pmd.h:20:#define
ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
./drivers/baseband/acc100/rte_acc100_pmd.c:590: acc100_reg_write(d,
reg_addr->info_ring_en, ACC100_REG_IRQ_EN_ALL);
> +
> +/* Number of Virtual Functions ACC101 supports */
> +#define ACC101_NUM_VFS 16
> +#define ACC101_NUM_QGRPS 8
> +#define ACC101_NUM_AQS 16
> +/* All ACC101 Registers alignment are 32bits = 4B */
> +#define ACC101_BYTES_IN_WORD 4
> +
> +#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
> +#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
> +#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to QoS Mon */
> +#define ACC101_TMPL_PRI_0 0x03020100
> +#define ACC101_TMPL_PRI_1 0x07060504
> +#define ACC101_TMPL_PRI_2 0x0b0a0908
> +#define ACC101_TMPL_PRI_3 0x0f0e0d0c
> +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
> +
> +#define ACC101_NUM_TMPL 32
> +/* Mapping of signals for the available engines */
> +#define ACC101_SIG_UL_5G 0
> +#define ACC101_SIG_UL_5G_LAST 8
> +#define ACC101_SIG_DL_5G 13
> +#define ACC101_SIG_DL_5G_LAST 15
> +#define ACC101_SIG_UL_4G 16
> +#define ACC101_SIG_UL_4G_LAST 19
> +#define ACC101_SIG_DL_4G 27
> +#define ACC101_SIG_DL_4G_LAST 31
> +#define ACC101_NUM_ACCS 5
> +#define ACC101_PF_VAL 2
> +
> +/* ACC101 Configuration */
> +#define ACC101_CFG_DMA_ERROR 0x3D7
> +#define ACC101_CFG_AXI_CACHE 0x11
> +#define ACC101_CFG_QMGR_HI_P 0x0F0F
> +#define ACC101_CFG_PCI_AXI 0xC003
> +#define ACC101_CFG_PCI_BRIDGE 0x40006033
> +#define ACC101_ENGINE_OFFSET 0x1000
> +#define ACC101_LONG_WAIT 1000
> +#define ACC101_GPEX_AXIMAP_NUM 17
> +#define ACC101_CLOCK_GATING_EN 0x30000
> +#define ACC101_DMA_INBOUND 0x104
> +/* DDR Size per VF - 512MB by default
> + * Can be increased up to 4 GB with single PF/VF
> + */
> +#define ACC101_HARQ_DDR (512 * 1)
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF
2022-05-16 20:48 ` [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-05-19 20:13 ` Maxime Coquelin
2022-05-23 17:06 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Maxime Coquelin @ 2022-05-19 20:13 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
Hi Nicolas,
On 5/16/22 22:48, Nicolas Chautru wrote:
> Adding companion function specific to ACC100 and it
> can be called from bbdev-test when running from PF.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> app/test-bbdev/test_bbdev_perf.c | 22 ++-
> drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
> drivers/baseband/acc100/rte_acc100_pmd.c | 302
+++++++++++++++++++++++++++++++
> drivers/baseband/acc100/version.map | 2 +-
> 4 files changed, 336 insertions(+), 7 deletions(-)
>
> diff --git a/app/test-bbdev/test_bbdev_perf.c
b/app/test-bbdev/test_bbdev_perf.c
> index 0fa119a..b10b93d 100644
> --- a/app/test-bbdev/test_bbdev_perf.c
> +++ b/app/test-bbdev/test_bbdev_perf.c
> @@ -63,6 +63,8 @@
> #define ACC100_QMGR_INVALID_IDX -1
> #define ACC100_QMGR_RR 1
> #define ACC100_QOS_GBR 0
> +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
> +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
> #endif
>
> #define OPS_CACHE_SIZE 256U
> @@ -711,11 +713,12 @@ typedef int (test_case_function)(struct
active_device *ad,
> #endif
> #ifdef RTE_BASEBAND_ACC100
> if ((get_init_device() == true) &&
> - (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
> + ((!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) ||
> + (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))) {
> struct rte_acc100_conf conf;
> unsigned int i;
>
> - printf("Configure ACC100 FEC Driver %s with default values\n",
> + printf("Configure ACC10X FEC Driver %s with default values\n",
> info->drv.driver_name);
>
> /* clear default configuration before initialization */
> @@ -760,10 +763,17 @@ typedef int (test_case_function)(struct
active_device *ad,
> conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
>
> /* setup PF with configuration information */
> - ret = rte_acc100_configure(info->dev_name, &conf);
> - TEST_ASSERT_SUCCESS(ret,
> - "Failed to configure ACC100 PF for bbdev %s",
> - info->dev_name);
> + if (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) {
> + ret = rte_acc100_configure(info->dev_name, &conf);
> + TEST_ASSERT_SUCCESS(ret,
> + "Failed to configure ACC100 PF for bbdev %s",
> + info->dev_name);
> + } else {
> + ret = rte_acc101_configure(info->dev_name, &conf);
> + TEST_ASSERT_SUCCESS(ret,
> + "Failed to configure ACC101 PF for bbdev %s",
> + info->dev_name);
> + }
> }
> #endif
> /* Let's refresh this now this is configured */
> diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h
b/drivers/baseband/acc100/rte_acc100_cfg.h
> index d233e42..2e3c43f 100644
> --- a/drivers/baseband/acc100/rte_acc100_cfg.h
> +++ b/drivers/baseband/acc100/rte_acc100_cfg.h
> @@ -106,6 +106,23 @@ struct rte_acc100_conf {
> int
> rte_acc100_configure(const char *dev_name, struct rte_acc100_conf
*conf);
>
> +/**
> + * Configure a ACC101 device
> + *
> + * @param dev_name
> + * The name of the device. This is the short form of PCI BDF, e.g.
00:01.0.
> + * It can also be retrieved for a bbdev device from the dev_name
field in the
> + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> + * @param conf
> + * Configuration to apply to ACC101 HW.
> + *
> + * @return
> + * Zero on success, negative value on failure.
> + */
> +__rte_experimental
> +int
> +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf
*conf);
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
b/drivers/baseband/acc100/rte_acc100_pmd.c
> index daf2ce0..b03cedc 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct
rte_pci_device *pci_dev)
> rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
> return 0;
> }
> +
> +
> +/* Initial configuration of a ACC101 device prior to running
configure() */
> +int
> +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
> +{
Please don't introduce new API for every new variant.
You should have a single API, and within it call specific configuration
function based on the device ID.
It will be easier for the application which calls it not to have to know
which variant it is for.
> + rte_bbdev_log(INFO, "rte_acc101_configure");
> + uint32_t value, address, status;
> + int qg_idx, template_idx, vf_idx, acc, i;
> + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> +
> + /* Compile time checks */
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
> +
> + if (bbdev == NULL) {
> + rte_bbdev_log(ERR,
> + "Invalid dev_name (%s), or device is not yet initialised",
> + dev_name);
> + return -ENODEV;
> + }
> + struct acc100_device *d = bbdev->data->dev_private;
> +
> + /* Store configuration */
> + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
> +
> + /* PCIe Bridge configuration */
> + acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
> + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
> + acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh +
i * 16, 0);
> +
> + /* Prevent blocking AXI read on BRESP for AXI Write */
> + address = HwPfPcieGpexAxiPioControl;
> + value = ACC101_CFG_PCI_AXI;
> + acc100_reg_write(d, address, value);
> +
> + /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
> + usleep(2000);
This sleep looks weird, especially when ACC100 does not require it.
Isn't there a way to know it is ready to release the AXI? Or at least
document why it is necessary.
> + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> +
> + /* Set the default 5GDL DMA configuration */
> + acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
> +
> + /* Enable granular dynamic clock gating */
> + address = HWPfHiClkGateHystReg;
> + value = ACC101_CLOCK_GATING_EN;
> + acc100_reg_write(d, address, value);
> +
> + /* Set default descriptor signature */
> + address = HWPfDmaDescriptorSignatuture;
> + value = 0;
> + acc100_reg_write(d, address, value);
> +
> + /* Enable the Error Detection in DMA */
> + value = ACC101_CFG_DMA_ERROR;
> + address = HWPfDmaErrorDetectionEn;
> + acc100_reg_write(d, address, value);
> +
> + /* AXI Cache configuration */
> + value = ACC101_CFG_AXI_CACHE;
> + address = HWPfDmaAxcacheReg;
> + acc100_reg_write(d, address, value);
> +
> + /* Default DMA Configuration (Qmgr Enabled) */
> + address = HWPfDmaConfig0Reg;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + address = HWPfDmaQmanen;
> + value = 0;
> + acc100_reg_write(d, address, value);
> +
> + /* Default RLIM/ALEN configuration */
> + address = HWPfDmaConfig1Reg;
> + int alen_r = 0xF;
> + int alen_w = 0x7;
> + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
> + acc100_reg_write(d, address, value);
> +
> + /* Configure DMA Qmanager addresses */
> + address = HWPfDmaQmgrAddrReg;
> + value = HWPfQmgrEgressQueuesTemplate;
> + acc100_reg_write(d, address, value);
> +
> + /* ===== Qmgr Configuration ===== */
> + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
> + int totalQgs = conf->q_ul_4g.num_qgroups +
> + conf->q_ul_5g.num_qgroups +
> + conf->q_dl_4g.num_qgroups +
> + conf->q_dl_5g.num_qgroups;
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + address = HWPfQmgrDepthLog2Grp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = aqDepth(qg_idx, conf);
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrTholdGrp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> + acc100_reg_write(d, address, value);
> + }
> +
> + /* Template Priority in incremental order */
> + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD *
template_idx;
> + value = ACC101_TMPL_PRI_0;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD *
template_idx;
> + value = ACC101_TMPL_PRI_1;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD *
template_idx;
> + value = ACC101_TMPL_PRI_2;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD *
template_idx;
> + value = ACC101_TMPL_PRI_3;
> + acc100_reg_write(d, address, value);
For both ACC100 and ACC101, ACC10x_NUM_TMPL is 32.
Isn't there a bug here or in ACC100?
ACC100 performs a modulo 8 on template_idx, but ACC101 does not. But the
registers mapping is the same, so I guess this is the same HW block.
I think ACC100 is the buggy one, because it seems weird to write the
same register with the same value multiple times.
In case it is ACC100 that is buggy, it needs to be fixed in a dedicated
patch, with proper fixes tag so that it is backported.
> + }
> +
> + address = HWPfQmgrGrpPriority;
> + value = ACC101_CFG_QMGR_HI_P;
> + acc100_reg_write(d, address, value);
> +
> + /* Template Configuration */
> + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> + template_idx++) {
> + value = 0;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> + }
> + /* 4GUL */
> + int numQgs = conf->q_ul_4g.num_qgroups;
> + int numQqsAcc = 0;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_UL_4G;
> + template_idx <= ACC101_SIG_UL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> + }
> + /* 5GUL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_ul_5g.num_qgroups;
> + value = 0;
> + int numEngines = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_UL_5G;
> + template_idx <= ACC101_SIG_UL_5G_LAST;
> + template_idx++) {
> + /* Check engine power-on status */
> + address = HwPfFecUl5gIbDebugReg +
> + ACC101_ENGINE_OFFSET * template_idx;
> + status = (acc100_reg_read(d, address) >> 4) & 0xF;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + if (status == 1) {
> + acc100_reg_write(d, address, value);
> + numEngines++;
> + } else
> + acc100_reg_write(d, address, 0);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> + printf("Number of 5GUL engines %d\n", numEngines);
> + /* 4GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_4g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_DL_4G;
> + template_idx <= ACC101_SIG_DL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> + /* 5GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_5g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_DL_5G;
> + template_idx <= ACC101_SIG_DL_5G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> +
> + /* Queue Group Function mapping */
> + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> + address = HWPfQmgrGrpFunction0;
> + value = 0;
> + for (qg_idx = 0; qg_idx < 8; qg_idx++) {
> + acc = accFromQgid(qg_idx, conf);
> + value |= qman_func_id[acc]<<(qg_idx * 4);
> + }
> + acc100_reg_write(d, address, value);
> +
> + /* Configuration of the Arbitration QGroup depth to 1 */
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + address = HWPfQmgrArbQDepthGrp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + }
> +
> + /* Enabling AQueues through the Queue hierarchy*/
> + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
> + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
> + value = 0;
> + if (vf_idx < conf->num_vf_bundles &&
> + qg_idx < totalQgs)
> + value = (1 << aqNum(qg_idx, conf)) - 1;
> + address = HWPfQmgrAqEnableVf
> + + vf_idx * ACC101_BYTES_IN_WORD;
> + value += (qg_idx << 16);
> + acc100_reg_write(d, address, value);
> + }
> + }
> +
> + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
> + uint32_t aram_address = 0;
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> + address = HWPfQmgrVfBaseAddr + vf_idx
> + * ACC101_BYTES_IN_WORD + qg_idx
> + * ACC101_BYTES_IN_WORD * 64;
> + value = aram_address;
> + acc100_reg_write(d, address, value);
> + /* Offset ARAM Address for next memory bank
> + * - increment of 4B
> + */
> + aram_address += aqNum(qg_idx, conf) *
> + (1 << aqDepth(qg_idx, conf));
> + }
> + }
> +
> + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
> + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
> + aram_address, ACC101_WORDS_IN_ARAM_SIZE);
> + return -EINVAL;
> + }
> +
> + /* ==== HI Configuration ==== */
> +
> + /* No Info Ring/MSI by default */
> + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
> + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
> + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
> + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
> + /* Prevent Block on Transmit Error */
> + address = HWPfHiBlockTransmitOnErrorEn;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + /* Prevents to drop MSI */
> + address = HWPfHiMsiDropEnableReg;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + /* Set the PF Mode register */
> + address = HWPfHiPfMode;
> + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
> + acc100_reg_write(d, address, value);
> + /* Explicitly releasing AXI after PF Mode and 2 ms */
> + usleep(2000);
> + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> +
> + /* QoS overflow init */
> + value = 1;
> + address = HWPfQosmonAEvalOverflow0;
> + acc100_reg_write(d, address, value);
> + address = HWPfQosmonBEvalOverflow0;
> + acc100_reg_write(d, address, value);
> +
> + /* HARQ DDR Configuration */
> + unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
> + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> + address = HWPfDmaVfDdrBaseRw + vf_idx
> + * 0x10;
> + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
> + (ddrSizeInMb - 1);
> + acc100_reg_write(d, address, value);
> + }
> + usleep(ACC101_LONG_WAIT);
> +
> + rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
> + return 0;
> +}
> diff --git a/drivers/baseband/acc100/version.map
b/drivers/baseband/acc100/version.map
> index 40604c7..37b850f 100644
> --- a/drivers/baseband/acc100/version.map
> +++ b/drivers/baseband/acc100/version.map
> @@ -6,5 +6,5 @@ EXPERIMENTAL {
> global:
>
> rte_acc100_configure;
> -
> + rte_acc101_configure;
> };
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF
2022-05-19 20:13 ` Maxime Coquelin
@ 2022-05-23 17:06 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-23 17:06 UTC (permalink / raw)
To: Maxime Coquelin, dev, gakhil, trix
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Maxime,
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Thursday, May 19, 2022 1:14 PM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from
> PF
>
> Hi Nicolas,
>
> On 5/16/22 22:48, Nicolas Chautru wrote:
> > Adding companion function specific to ACC100 and it > can be called from
> bbdev-test when running from PF.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> > ---
> > app/test-bbdev/test_bbdev_perf.c | 22 ++-
> > drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
> > drivers/baseband/acc100/rte_acc100_pmd.c | 302
> +++++++++++++++++++++++++++++++
> > drivers/baseband/acc100/version.map | 2 +-
> > 4 files changed, 336 insertions(+), 7 deletions(-)
> >
> > diff --git a/app/test-bbdev/test_bbdev_perf.c
> b/app/test-bbdev/test_bbdev_perf.c
> > index 0fa119a..b10b93d 100644
> > --- a/app/test-bbdev/test_bbdev_perf.c
> > +++ b/app/test-bbdev/test_bbdev_perf.c
> > @@ -63,6 +63,8 @@
> > #define ACC100_QMGR_INVALID_IDX -1
> > #define ACC100_QMGR_RR 1
> > #define ACC100_QOS_GBR 0
> > +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
> > +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
> > #endif
> >
> > #define OPS_CACHE_SIZE 256U
> > @@ -711,11 +713,12 @@ typedef int (test_case_function)(struct
> active_device *ad,
> > #endif
> > #ifdef RTE_BASEBAND_ACC100
> > if ((get_init_device() == true) &&
> > - (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)))
> {
> > + ((!strcmp(info->drv.driver_name,
> ACC100PF_DRIVER_NAME)) ||
> > + (!strcmp(info->drv.driver_name,
> ACC101PF_DRIVER_NAME)))) {
> > struct rte_acc100_conf conf;
> > unsigned int i;
> >
> > - printf("Configure ACC100 FEC Driver %s with default
> values\n",
> > + printf("Configure ACC10X FEC Driver %s with default
> values\n",
> > info->drv.driver_name);
> >
> > /* clear default configuration before initialization */
> > @@ -760,10 +763,17 @@ typedef int (test_case_function)(struct
> active_device *ad,
> > conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> >
> > /* setup PF with configuration information */
> > - ret = rte_acc100_configure(info->dev_name, &conf);
> > - TEST_ASSERT_SUCCESS(ret,
> > - "Failed to configure ACC100 PF for bbdev
> %s",
> > - info->dev_name);
> > + if (!strcmp(info->drv.driver_name,
> ACC100PF_DRIVER_NAME)) {
> > + ret = rte_acc100_configure(info->dev_name, &conf);
> > + TEST_ASSERT_SUCCESS(ret,
> > + "Failed to configure ACC100 PF for
> bbdev %s",
> > + info->dev_name);
> > + } else {
> > + ret = rte_acc101_configure(info->dev_name, &conf);
> > + TEST_ASSERT_SUCCESS(ret,
> > + "Failed to configure ACC101 PF for
> bbdev %s",
> > + info->dev_name);
> > + }
> > }
> > #endif
> > /* Let's refresh this now this is configured */
> > diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h
> b/drivers/baseband/acc100/rte_acc100_cfg.h
> > index d233e42..2e3c43f 100644
> > --- a/drivers/baseband/acc100/rte_acc100_cfg.h
> > +++ b/drivers/baseband/acc100/rte_acc100_cfg.h
> > @@ -106,6 +106,23 @@ struct rte_acc100_conf {
> > int
> > rte_acc100_configure(const char *dev_name, struct rte_acc100_conf
> *conf);
> >
> > +/**
> > + * Configure a ACC101 device
> > + *
> > + * @param dev_name
> > + * The name of the device. This is the short form of PCI BDF, e.g.
> 00:01.0.
> > + * It can also be retrieved for a bbdev device from the dev_name
> field in the
> > + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> > + * @param conf
> > + * Configuration to apply to ACC101 HW.
> > + *
> > + * @return
> > + * Zero on success, negative value on failure.
> > + */
> > +__rte_experimental
> > +int
> > +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf
> *conf); > +
> > #ifdef __cplusplus
> > }
> > #endif
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index daf2ce0..b03cedc 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -4921,3 +4921,305 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > rte_bbdev_log_debug("PF Tip configuration complete for %s",
> dev_name);
> > return 0;
> > }
> > +
> > +
> > +/* Initial configuration of a ACC101 device prior to running
> configure() */
> > +int
> > +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf
> *conf) > +{ Please don't introduce new API for every new variant.
> You should have a single API, and within it call specific configuration function
> based on the device ID.
>
> It will be easier for the application which calls it not to have to know which
> variant it is for.
Note that this is not being used by user application, this is a companion function used as part of bbdev-test
so that the device configuration can be done without relying on other ingredients outside of DPDK (pf_bb_config).
>
> > + rte_bbdev_log(INFO, "rte_acc101_configure");
> > + uint32_t value, address, status;
> > + int qg_idx, template_idx, vf_idx, acc, i;
> > + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> > +
> > + /* Compile time checks */
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
> > +
> > + if (bbdev == NULL) {
> > + rte_bbdev_log(ERR,
> > + "Invalid dev_name (%s), or device is not yet initialised",
> > + dev_name);
> > + return -ENODEV;
> > + }
> > + struct acc100_device *d = bbdev->data->dev_private;
> > +
> > + /* Store configuration */
> > + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
> > +
> > + /* PCIe Bridge configuration */
> > + acc100_reg_write(d, HwPfPcieGpexBridgeControl,
> ACC101_CFG_PCI_BRIDGE);
> > + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
> > + acc100_reg_write(d,
> HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh +
> i * 16, 0);
> > +
> > + /* Prevent blocking AXI read on BRESP for AXI Write */
> > + address = HwPfPcieGpexAxiPioControl;
> > + value = ACC101_CFG_PCI_AXI;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
> > + usleep(2000);
> This sleep looks weird, especially when ACC100 does not require it.
> Isn't there a way to know it is ready to release the AXI? Or at least document
> why it is necessary.
This is intentional and HW specific for ACC101. There would be no public documentation
for this, but I can add a comment.
>
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* Set the default 5GDL DMA configuration */
> > + acc100_reg_write(d, HWPfDmaInboundDrainDataSize,
> ACC101_DMA_INBOUND);
> > +
> > + /* Enable granular dynamic clock gating */
> > + address = HWPfHiClkGateHystReg;
> > + value = ACC101_CLOCK_GATING_EN;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Set default descriptor signature */
> > + address = HWPfDmaDescriptorSignatuture;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Enable the Error Detection in DMA */
> > + value = ACC101_CFG_DMA_ERROR;
> > + address = HWPfDmaErrorDetectionEn;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* AXI Cache configuration */
> > + value = ACC101_CFG_AXI_CACHE;
> > + address = HWPfDmaAxcacheReg;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default DMA Configuration (Qmgr Enabled) */
> > + address = HWPfDmaConfig0Reg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfDmaQmanen;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default RLIM/ALEN configuration */
> > + address = HWPfDmaConfig1Reg;
> > + int alen_r = 0xF;
> > + int alen_w = 0x7;
> > + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configure DMA Qmanager addresses */
> > + address = HWPfDmaQmgrAddrReg;
> > + value = HWPfQmgrEgressQueuesTemplate;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* ===== Qmgr Configuration ===== */
> > + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2
> for UL */
> > + int totalQgs = conf->q_ul_4g.num_qgroups +
> > + conf->q_ul_5g.num_qgroups +
> > + conf->q_dl_4g.num_qgroups +
> > + conf->q_dl_5g.num_qgroups;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrDepthLog2Grp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = aqDepth(qg_idx, conf);
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrTholdGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Template Priority in incremental order */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg0Indx +
> ACC101_BYTES_IN_WORD *
> template_idx;
> > + value = ACC101_TMPL_PRI_0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg1Indx +
> ACC101_BYTES_IN_WORD *
> template_idx;
> > + value = ACC101_TMPL_PRI_1;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg2indx +
> ACC101_BYTES_IN_WORD *
> template_idx;
> > + value = ACC101_TMPL_PRI_2;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg3Indx +
> ACC101_BYTES_IN_WORD *
> template_idx;
> > + value = ACC101_TMPL_PRI_3;
> > + acc100_reg_write(d, address, value);
> For both ACC100 and ACC101, ACC10x_NUM_TMPL is 32.
> Isn't there a bug here or in ACC100?
>
> ACC100 performs a modulo 8 on template_idx, but ACC101 does not. But the
> registers mapping is the same, so I guess this is the same HW block.
>
> I think ACC100 is the buggy one, because it seems weird to write the same
> register with the same value multiple times.
>
> In case it is ACC100 that is buggy, it needs to be fixed in a dedicated patch,
> with proper fixes tag so that it is backported.
Yes there a number of patches pending for ACC100, this can be done through other serie.
>
> > + }
> > +
> > + address = HWPfQmgrGrpPriority;
> > + value = ACC101_CFG_QMGR_HI_P;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Template Configuration */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + value = 0;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 4GUL */
> > + int numQgs = conf->q_ul_4g.num_qgroups;
> > + int numQqsAcc = 0;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_4G;
> > + template_idx <= ACC101_SIG_UL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 5GUL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_ul_5g.num_qgroups;
> > + value = 0;
> > + int numEngines = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_5G;
> > + template_idx <= ACC101_SIG_UL_5G_LAST;
> > + template_idx++) {
> > + /* Check engine power-on status */
> > + address = HwPfFecUl5gIbDebugReg +
> > + ACC101_ENGINE_OFFSET * template_idx;
> > + status = (acc100_reg_read(d, address) >> 4) & 0xF;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + if (status == 1) {
> > + acc100_reg_write(d, address, value);
> > + numEngines++;
> > + } else
> > + acc100_reg_write(d, address, 0);
> > +#if RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > + printf("Number of 5GUL engines %d\n", numEngines);
> > + /* 4GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_4g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_4G;
> > + template_idx <= ACC101_SIG_DL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > +#if RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > + /* 5GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_5g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_5G;
> > + template_idx <= ACC101_SIG_DL_5G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > +#if RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > +
> > + /* Queue Group Function mapping */
> > + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> > + address = HWPfQmgrGrpFunction0;
> > + value = 0;
> > + for (qg_idx = 0; qg_idx < 8; qg_idx++) {
> > + acc = accFromQgid(qg_idx, conf);
> > + value |= qman_func_id[acc]<<(qg_idx * 4);
> > + }
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configuration of the Arbitration QGroup depth to 1 */
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrArbQDepthGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Enabling AQueues through the Queue hierarchy*/
> > + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
> > + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
> > + value = 0;
> > + if (vf_idx < conf->num_vf_bundles &&
> > + qg_idx < totalQgs)
> > + value = (1 << aqNum(qg_idx, conf)) - 1;
> > + address = HWPfQmgrAqEnableVf
> > + + vf_idx * ACC101_BYTES_IN_WORD;
> > + value += (qg_idx << 16);
> > + acc100_reg_write(d, address, value);
> > + }
> > + }
> > +
> > + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
> > + uint32_t aram_address = 0;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfQmgrVfBaseAddr + vf_idx
> > + * ACC101_BYTES_IN_WORD + qg_idx
> > + * ACC101_BYTES_IN_WORD * 64;
> > + value = aram_address;
> > + acc100_reg_write(d, address, value);
> > + /* Offset ARAM Address for next memory bank
> > + * - increment of 4B
> > + */
> > + aram_address += aqNum(qg_idx, conf) *
> > + (1 << aqDepth(qg_idx, conf));
> > + }
> > + }
> > +
> > + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
> > + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d
> %d\n",
> > + aram_address,
> ACC101_WORDS_IN_ARAM_SIZE);
> > + return -EINVAL;
> > + }
> > +
> > + /* ==== HI Configuration ==== */
> > +
> > + /* No Info Ring/MSI by default */
> > + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
> > + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
> > + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
> > + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
> > + /* Prevent Block on Transmit Error */
> > + address = HWPfHiBlockTransmitOnErrorEn;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Prevents to drop MSI */
> > + address = HWPfHiMsiDropEnableReg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Set the PF Mode register */
> > + address = HWPfHiPfMode;
> > + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
> > + acc100_reg_write(d, address, value);
> > + /* Explicitly releasing AXI after PF Mode and 2 ms */
> > + usleep(2000);
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* QoS overflow init */
> > + value = 1;
> > + address = HWPfQosmonAEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQosmonBEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* HARQ DDR Configuration */
> > + unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfDmaVfDdrBaseRw + vf_idx
> > + * 0x10;
> > + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
> > + (ddrSizeInMb - 1);
> > + acc100_reg_write(d, address, value);
> > + }
> > + usleep(ACC101_LONG_WAIT);
> > +
> > + rte_bbdev_log_debug("PF TIP configuration complete for %s",
> dev_name);
> > + return 0;
> > +}
> > diff --git a/drivers/baseband/acc100/version.map
> b/drivers/baseband/acc100/version.map
> > index 40604c7..37b850f 100644
> > --- a/drivers/baseband/acc100/version.map
> > +++ b/drivers/baseband/acc100/version.map
> > @@ -6,5 +6,5 @@ EXPERIMENTAL {
> > global:
> >
> > rte_acc100_configure;
> > -
> > + rte_acc101_configure;
> > };
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
2022-05-10 11:55 ` Tom Rix
@ 2022-05-23 17:53 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-23 17:53 UTC (permalink / raw)
To: Tom Rix, dev, gakhil
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Zhang,
Mingshan, david.marchand
Hi Tom,
I realize I had not replied to that one
> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Tuesday, May 10, 2022 4:56 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Zhang, Mingshan <mingshan.zhang@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
>
>
> On 5/9/22 2:23 PM, Chautru, Nicolas wrote:
> > Hi Tom,
> >
> >> -----Original Message-----
> >> From: Tom Rix <trix@redhat.com>
> >> Sent: Sunday, May 8, 2022 6:03 AM
> >> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> >> gakhil@marvell.com
> >> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> >> Richardson, Bruce <bruce.richardson@intel.com>;
> >> hemant.agrawal@nxp.com; Zhang, Mingshan
> <mingshan.zhang@intel.com>;
> >> david.marchand@redhat.com
> >> Subject: Re: [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101
> >>
> >> This is a good start reusing code, but I think it needs to do more reuse.
> >>
> >> These cards should be very close and likely represent a family of cards.
> >>
> >> On 4/27/22 11:16 AM, Nicolas Chautru wrote:
> >>> Support for ACC101 as a derivative of ACC100.
> >>> Reusing existing code when possible.
> >>>
> >>> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> >>> ---
> >>> doc/guides/bbdevs/acc101.rst | 237
> >> +++++++++++++++++++++++++++++++
> >>> doc/guides/bbdevs/features/acc101.ini | 13 ++
> >>> doc/guides/bbdevs/index.rst | 1 +
> >>> doc/guides/rel_notes/release_22_07.rst | 4 +
> >>> drivers/baseband/acc100/rte_acc100_pmd.c | 194
> >> ++++++++++++++++++++++++-
> >>> drivers/baseband/acc100/rte_acc100_pmd.h | 6 +
> >>> drivers/baseband/acc100/rte_acc101_pmd.h | 61 ++++++++
> >>> 7 files changed, 511 insertions(+), 5 deletions(-)
> >>> create mode 100644 doc/guides/bbdevs/acc101.rst
> >>> create mode 100644 doc/guides/bbdevs/features/acc101.ini
> >>> create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
> >>>
> >>> diff --git a/doc/guides/bbdevs/acc101.rst
> >>> b/doc/guides/bbdevs/acc101.rst new file mode 100644 index
> >>> 0000000..46c310b
> >>> --- /dev/null
> >>> +++ b/doc/guides/bbdevs/acc101.rst
> >>> @@ -0,0 +1,237 @@
> >>> +.. SPDX-License-Identifier: BSD-3-Clause
> >>> + Copyright(c) 2020 Intel Corporation
> >>> +
> >>> +Intel(R) ACC101 5G/4G FEC Poll Mode Driver
> >>> +==========================================
> >>> +
> >>> +The BBDEV ACC101 5G/4G FEC poll mode driver (PMD) supports an
> >>> +implementation of a VRAN FEC wireless acceleration function.
> >>> +This device is also known as Mount Cirrus.
> >>> +This is a follow-up to Mount Bryce (ACC100) and includes fixes,
> >>> +improved feature set for error scenarios and performance capacity
> increase.
> >> includes fixes, better error handling and increased performance.
> >>
> >> A quick look at acc100.rst and the bulk of acc101.rst looks the same.
> >>
> >> Consider a user of the acc100 is upgrading to acc101, they will
> >>
> >> want to know what is the same and what has changed and test
> accordingly.
> >>
> >> These two documents should be combined.
> >>
> > Well in term of documentation, for the users it helps to be able to follow
> steps as they are for a given variant.
> > As opposed to have to have multiple options through the document when
> using ACC100 vs ACC101.
> > Except if they are other objections, I would see this more useful for the
> user as is and less source of errors.
> >
> My perspective is having existing acc100 users that are upgrading and/or
> having to support both acc100 and acc101
>
> for a very long time. In the first case users of existing acc100 users will want
> to know only the parts that have changed.
>
> In the second, later changes that are common to both acc100 and acc101 and
> later accXXX will be have to fixed in
>
> multiple places. As myself or someone at Red Hat will be on the hook for
> both, I would prefer if the refactoring
>
> of the common parts acc100,acc101 were in good shape over the expediency
> of having acc101 sooner.
Will merge documentation
>
> >>> +
> >>> +Features
> >>> +--------
> >>> +
>
> >>> index 0000000..0e2c21a
> >>> --- /dev/null
> >>> +++ b/doc/guides/bbdevs/features/acc101.ini
> >>> @@ -0,0 +1,13 @@
> >>> +;
> >>> +; Supported features of the 'acc101' bbdev driver.
> >>> +;
> >>> +; Refer to default.ini for the full list of available PMD features.
> >>> +;
> >>> +[Features]
> >>> +Turbo Decoder (4G) = Y
> >>> +Turbo Encoder (4G) = Y
> >>> +LDPC Decoder (5G) = Y
> >>> +LDPC Encoder (5G) = Y
> >>> +LLR/HARQ Compression = Y
> >>> +External DDR Access = Y
> >>> +HW Accelerated = Y
> >> This is the same as acc100.ini, why do we need 2 ?
> > This is a different product, needs to be consistent.
> ok
> >
> >>> diff --git a/doc/guides/bbdevs/index.rst
> >>> b/doc/guides/bbdevs/index.rst index cedd706..e76883c 100644
> >>> --- a/doc/guides/bbdevs/index.rst
> >>> +++ b/doc/guides/bbdevs/index.rst
> >>> @@ -14,4 +14,5 @@ Baseband Device Drivers
> >>> fpga_lte_fec
> >>> fpga_5gnr_fec
> >>> acc100
> >>> + acc101
> >>> la12xx
> >>> diff --git a/doc/guides/rel_notes/release_22_07.rst
> >>> b/doc/guides/rel_notes/release_22_07.rst
> >>> index 42a5f2d..ef9906b 100644
> >>> --- a/doc/guides/rel_notes/release_22_07.rst
> >>> +++ b/doc/guides/rel_notes/release_22_07.rst
> >>> @@ -55,6 +55,10 @@ New Features
> >>> Also, make sure to start the actual text at the margin.
> >>> =======================================================
> >>>
> >>> +* **Added Intel ACC101 baseband PMD.**
> >>> +
> >>> + * Added a new baseband PMD for Intel ACC101 device (Mount Cirrus).
> >>> + * See the :doc:`../bbdevs/acc101` for more details.
> >>>
> >>> Removed Items
> >>> -------------
> >>> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> b/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> index de7e4bc..fca27ef 100644
> >>> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> @@ -22,6 +22,7 @@
> >>> #include <rte_bbdev.h>
> >>> #include <rte_bbdev_pmd.h>
> >>> #include "rte_acc100_pmd.h"
> >>> +#include "rte_acc101_pmd.h"
> >>>
> >>> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> >>> RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); @@ -1286,6
> >> +1287,12
> >>> @@
> >>> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> >>> }
> >>>
> >>> +static inline bool
> >>> +is_acc100(struct acc100_queue *q)
> >>> +{
> >>> + return (q->d->device_variant == ACC100_VARIANT); }
> >>> +
> >>> /* Fill in a frame control word for LDPC decoding. */
> >>> static inline void
> >>> acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct
> >>> acc100_fcw_ld *fcw, @@ -1412,6 +1419,139 @@
> >>> }
> >>> }
> >>>
> >>> +/* Convert offset to harq index for harq_layout structure */ static
> >>> +inline uint32_t hq_index(uint32_t offset) {
> >>> + return (offset >> ACC100_HARQ_OFFSET_SHIFT) &
> >>> +ACC100_HARQ_OFFSET_MASK; }
> >>> +
> >>> +/* Fill in a frame control word for LDPC decoding for ACC101 */
> >>> +static inline void acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op,
> >>> +struct acc100_fcw_ld *fcw,
> >>> + union acc100_harq_layout_data *harq_layout)
> >> This looks extremely similar to the acc100*, why isn't this combined ?
>
> Please answer.
>
> Functions that look similar should be combined.
Most of the code is common except that very function since they are HW differences which would need to be managed differently including through future patches and/or maintenance.
Hopefully you would agree that this difference is kept very small (one function).
>
> This gets to doing more to refactor the parts that are common between
> acc100 and acc101.
>
> >>> +{
> >>> + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p,
> parity_offset;
> >>> + uint32_t harq_index;
> >>> + uint32_t l;
> >>> +
> >>> + fcw->qm = op->ldpc_dec.q_m;
> >>> + fcw->nfiller = op->ldpc_dec.n_filler;
> >>> + fcw->BG = (op->ldpc_dec.basegraph - 1);
> >>> + fcw->Zc = op->ldpc_dec.z_c;
> >>> + fcw->ncb = op->ldpc_dec.n_cb;
> >>> + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
> >>> + op->ldpc_dec.rv_index);
> >>> + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
> >>> + fcw->rm_e = op->ldpc_dec.cb_params.e;
> >>> + else
> >>> + fcw->rm_e = (op->ldpc_dec.tb_params.r <
> >>> + op->ldpc_dec.tb_params.cab) ?
> >>> + op->ldpc_dec.tb_params.ea :
> >>> + op->ldpc_dec.tb_params.eb;
> >>> +
> >>> + if (unlikely(check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
> >>> + (op->ldpc_dec.harq_combined_input.length == 0))) {
> >>> + rte_bbdev_log(WARNING, "Null HARQ input size provided");
> >>> + /* Disable HARQ input in that case to carry forward */
> >>> + op->ldpc_dec.op_flags ^=
> >> RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> >>> + }
> >>> +
> >>> + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
> >>> + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
> >>> + fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
> >>> + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_DECODE_BYPASS);
> >>> + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
> >>> + if (op->ldpc_dec.q_m == 1) {
> >>> + fcw->bypass_intlv = 1;
> >>> + fcw->qm = 2;
> >>> + }
> >>> + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> >>> + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> >>> + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_LLR_COMPRESSION);
> >>> + harq_index = hq_index(op-
> >ldpc_dec.harq_combined_output.offset);
> >>> + if (fcw->hcin_en > 0) {
> >>> + harq_in_length = op-
> >ldpc_dec.harq_combined_input.length;
> >>> + if (fcw->hcin_decomp_mode > 0)
> >>> + harq_in_length = harq_in_length * 8 / 6;
> >>> + harq_in_length = RTE_MIN(harq_in_length, op-
> >>> ldpc_dec.n_cb
> >>> + - op->ldpc_dec.n_filler);
> >>> + /* Alignment on next 64B - Already enforced from HC output
> */
> >>> + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> >>> + fcw->hcin_size0 = harq_in_length;
> >>> + fcw->hcin_offset = 0;
> >>> + fcw->hcin_size1 = 0;
> >>> + } else {
> >>> + fcw->hcin_size0 = 0;
> >>> + fcw->hcin_offset = 0;
> >>> + fcw->hcin_size1 = 0;
> >>> + }
> >>> +
> >>> + fcw->itmax = op->ldpc_dec.iter_max;
> >>> + fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> >>> + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
> >>> + fcw->synd_precoder = fcw->itstop;
> >>> + /*
> >>> + * These are all implicitly set
> >>> + * fcw->synd_post = 0;
> >>> + * fcw->so_en = 0;
> >>> + * fcw->so_bypass_rm = 0;
> >>> + * fcw->so_bypass_intlv = 0;
> >>> + * fcw->dec_convllr = 0;
> >>> + * fcw->hcout_convllr = 0;
> >>> + * fcw->hcout_size1 = 0;
> >>> + * fcw->so_it = 0;
> >>> + * fcw->hcout_offset = 0;
> >>> + * fcw->negstop_th = 0;
> >>> + * fcw->negstop_it = 0;
> >>> + * fcw->negstop_en = 0;
> >>> + * fcw->gain_i = 1;
> >>> + * fcw->gain_h = 1;
> >>> + */
> >>> + if (fcw->hcout_en > 0) {
> >>> + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
> >>> + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
> >>> + k0_p = (fcw->k0 > parity_offset) ?
> >>> + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
> >>> + ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> >>> + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
> >>> + harq_out_length = (uint16_t) fcw->hcin_size0;
> >>> + harq_out_length = RTE_MAX(harq_out_length, l);
> >>> + /* Cannot exceed the pruned Ncb circular buffer */
> >>> + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> >>> + /* Alignment on next 64B */
> >>> + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> >>> + fcw->hcout_size0 = harq_out_length;
> >>> + fcw->hcout_size1 = 0;
> >>> + fcw->hcout_offset = 0;
> >>> + harq_layout[harq_index].offset = fcw->hcout_offset;
> >>> + harq_layout[harq_index].size0 = fcw->hcout_size0;
> >>> + } else {
> >>> + fcw->hcout_size0 = 0;
> >>> + fcw->hcout_size1 = 0;
> >>> + fcw->hcout_offset = 0;
> >>> + }
> >>> +}
> >>> +
> >>> +static inline void
> >>> +acc10x_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct
> >>> +acc100_fcw_ld
> >> *fcw,
> >>> + union acc100_harq_layout_data *harq_layout, struct
> >> acc100_queue *q)
> >>> +{
> >>> + if (is_acc100(q))
> >> consider having a function table in the private data so the call can
> >> be made without this if-check
> Please answer.
Answered offline I believe. This was left for consideration but I tend to believe that both options are similar, this was slightly less convoluted.
> >>> + return acc100_fcw_ld_fill(op, fcw, harq_layout);
> >>> + else
> >>> + return acc101_fcw_ld_fill(op, fcw, harq_layout); }
> >>> +
> >>> +
> >>> /**
> >>> * Fills descriptor with data pointers of one block type.
> >>> *
> >>> @@ -2960,7 +3100,7 @@
> >>> struct acc100_fcw_ld *fcw;
> >>> uint32_t seg_total_left;
> >>> fcw = &desc->req.fcw_ld;
> >>> - acc100_fcw_ld_fill(op, fcw, harq_layout);
> >>> + acc10x_fcw_ld_fill(op, fcw, harq_layout, q);
> >>>
> >>> /* Special handling when overusing mbuf */
> >>> if (fcw->rm_e < ACC100_MAX_E_MBUF) @@ -3027,7 +3167,7
> >> @@
> >>> desc = q->ring_addr + desc_idx;
> >>> uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
> >>> union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
> >>> - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
> >>> + acc10x_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout, q);
> >>>
> >>> input = op->ldpc_dec.input.data;
> >>> h_output_head = h_output = op->ldpc_dec.hard_output.data; @@
> >>> -4139,9 +4279,17 @@
> >>> dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
> >>> dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
> >>>
> >>> - ((struct acc100_device *) dev->data->dev_private)->pf_device =
> >>> - !strcmp(drv->driver.name,
> >>> - RTE_STR(ACC100PF_DRIVER_NAME));
> >>> + if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME)))
> >> ||
> >>> + (!strcmp(drv->driver.name,
> >> RTE_STR(ACC100VF_DRIVER_NAME)))) {
> >>> + ((struct acc100_device *) dev->data->dev_private)->pf_device
> >> =
> >>> + !strcmp(drv->driver.name,
> >> RTE_STR(ACC100PF_DRIVER_NAME));
> >>> + ((struct acc100_device *) dev->data->dev_private)-
> >>> device_variant = ACC100_VARIANT;
> >>> + } else {
> >>> + ((struct acc100_device *) dev->data->dev_private)->pf_device
> >> =
> >>> + !strcmp(drv->driver.name,
> >> RTE_STR(ACC101PF_DRIVER_NAME));
> >>> + ((struct acc100_device *) dev->data->dev_private)-
> >>> device_variant = ACC101_VARIANT;
> >>> + }
> >>> +
> >>> ((struct acc100_device *) dev->data->dev_private)->mmio_base =
> >>> pci_dev->mem_resource[0].addr;
> >>>
> >>> @@ -4251,6 +4399,42 @@ static int acc100_pci_remove(struct
> >> rte_pci_device *pci_dev)
> >>> RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME,
> >> acc100_pci_vf_driver);
> >>> RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME,
> >>> pci_id_acc100_vf_map);
> >>>
> >>> +/* ACC101 PCI PF address map */
> >>> +static struct rte_pci_id pci_id_acc101_pf_map[] = {
> >>> + {
> >>> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> >> RTE_ACC101_PF_DEVICE_ID)
> >>> + },
> >>> + {.device_id = 0},
> >>> +};
> >>> +
> >>> +/* ACC101 PCI VF address map */
> >>> +static struct rte_pci_id pci_id_acc101_vf_map[] = {
> >>> + {
> >>> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> >> RTE_ACC101_VF_DEVICE_ID)
> >>> + },
> >>> + {.device_id = 0},
> >>> +};
> >>> +
> >>> +
> >>> +static struct rte_pci_driver acc101_pci_pf_driver = {
> >>> + .probe = acc100_pci_probe,
> >>> + .remove = acc100_pci_remove,
> >>> + .id_table = pci_id_acc101_pf_map,
> >>> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING };
> >>> +
> >>> +static struct rte_pci_driver acc101_pci_vf_driver = {
> >>> + .probe = acc100_pci_probe,
> >>> + .remove = acc100_pci_remove,
> >>> + .id_table = pci_id_acc101_vf_map,
> >>> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING };
> >>> +
> >>> +RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME,
> >> acc101_pci_pf_driver);
> >>> +RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME,
> >>> +pci_id_acc101_pf_map);
> >> RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME,
> >>> +acc101_pci_vf_driver);
> >>> +RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME,
> >>> +pci_id_acc101_vf_map);
> >>> +
> >>> /*
> >>> * Workaround implementation to fix the power on status of some
> >>> 5GUL
> >> engines
> >>> * This requires DMA permission if ported outside DPDK diff --git
> >>> a/drivers/baseband/acc100/rte_acc100_pmd.h
> >>> b/drivers/baseband/acc100/rte_acc100_pmd.h
> >>> index cbcece2..6438031 100644
> >>> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> >>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> >>> @@ -22,6 +22,9 @@
> >>> #define rte_bbdev_log_debug(fmt, ...)
> >>> #endif
> >>>
> >>> +#define ACC100_VARIANT 0
> >>> +#define ACC101_VARIANT 1
> >>> +
> >>> /* ACC100 PF and VF driver names */
> >>> #define ACC100PF_DRIVER_NAME intel_acc100_pf
> >>> #define ACC100VF_DRIVER_NAME intel_acc100_vf
> >>> @@ -67,6 +70,8 @@
> >>> #define ACC100_HARQ_LAYOUT (64*1024*1024)
> >>> /* Assume offset for HARQ in memory */
> >>> #define ACC100_HARQ_OFFSET (32*1024)
> >>> +#define ACC100_HARQ_OFFSET_SHIFT 15
> >>> +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
> >>> /* Mask used to calculate an index in an Info Ring array (not a byte
> offset) */
> >>> #define ACC100_INFO_RING_MASK
> >> (ACC100_INFO_RING_NUM_ENTRIES-1)
> >>> /* Number of Virtual Functions ACC100 supports */ @@ -590,6
> >>> +595,7 @@ struct acc100_device {
> >>> uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
> >>> bool pf_device; /**< True if this is a PF ACC100 device */
> >>> bool configured; /**< True if this ACC100 device is configured
> >>> */
> >>> + uint16_t device_variant; /**< Device variant */
> >> this is not needed, check the pci id
> > That device_variant is sent once during probing then we can reuse that
> flexibly through the code.
>
> In the same way the pci id is set once.
>
> Generally if there is a way to use existing data to figure something out, then
> use the existing data.
>
> Special purpose data increases the size and complexity as well as
> destabilizing the api
In that very case it helps to keep in one place I believe, the device ids would be different from PF and VF.
The API is not impacted here, only underlying structure within the PMD.
>
> >
> >
> >>> };
> >>>
> >>> /**
> >>> diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h
> >>> b/drivers/baseband/acc100/rte_acc101_pmd.h
> >>> new file mode 100644
> >>> index 0000000..efab400
> >>> --- /dev/null
> >>> +++ b/drivers/baseband/acc100/rte_acc101_pmd.h
> >> New files need license, copyrights.
> > Thanks!!
> >
> >> This file looks very similar to rte_acc100_pmd.h
> > Actually the configuration of the device differs and could diverge further in
> the future. This is limited to the part that would be specific to the device
> configuration.
> > Already kept to extremely reduced set. Doing it more would be artificial
> and source of possible errors.
> >
> >> The common parts should be in only one file, maybe a rte_acc10x_pmd.h
> >>
> >>> @@ -0,0 +1,61 @@
> >>> +/* ACC101 PF and VF driver names */
> >>> +#define ACC101PF_DRIVER_NAME intel_acc101_pf
> >>> +#define ACC101VF_DRIVER_NAME intel_acc101_vf
> >> this maybe changes to intel_acc10x_pr/vf ?
> > That string would be different from the 2 products on purpose even if
> under the bonnet we try to reuse code as much as possible.
>
> These two devices could be run from the same driver.
>
> I am used to linux kernel drivers that handle multiple devices with the same
> driver.
>
> The reuse in the linux kernel is about 95%.
>
> The reuse here is about 30%, it should be at least 80%
Where did you get this 30% number? I believe the reuse above is already >80% of the PMD code. (The companion configure function being outside of the PMD per se).
Thanks
Nic
>
> Tom
>
> >
> >> Tom
> >>
> >>> +
> >>> +/* ACC101 PCI vendor & device IDs */
> >>> +#define RTE_ACC101_VENDOR_ID (0x8086)
> >>> +#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
> >>> +#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
> >>> +
> >>> +/* Define as 1 to use only a single FEC engine */ #ifndef
> >>> +RTE_ACC101_SINGLE_FEC #define RTE_ACC101_SINGLE_FEC 0 #endif
> >>> +
> >>> +/* Values used in writing to the registers */
> >>> +#define ACC101_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all
> interrupts
> >> */
> >>> +
> >>> +/* Number of Virtual Functions ACC101 supports */
> >>> +#define ACC101_NUM_VFS 16
> >>> +#define ACC101_NUM_QGRPS 8
> >>> +#define ACC101_NUM_AQS 16
> >>> +/* All ACC101 Registers alignment are 32bits = 4B */
> >>> +#define ACC101_BYTES_IN_WORD 4
> >>> +
> >>> +#define ACC101_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
> >>> +#define ACC101_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
> >>> +#define ACC101_VF_OFFSET_QOS 16 /* offset in Memory specific to
> QoS
> >> Mon */
> >>> +#define ACC101_TMPL_PRI_0 0x03020100
> >>> +#define ACC101_TMPL_PRI_1 0x07060504
> >>> +#define ACC101_TMPL_PRI_2 0x0b0a0908
> >>> +#define ACC101_TMPL_PRI_3 0x0f0e0d0c
> >>> +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
> >>> +
> >>> +#define ACC101_NUM_TMPL 32
> >>> +/* Mapping of signals for the available engines */
> >>> +#define ACC101_SIG_UL_5G 0
> >>> +#define ACC101_SIG_UL_5G_LAST 8
> >>> +#define ACC101_SIG_DL_5G 13
> >>> +#define ACC101_SIG_DL_5G_LAST 15
> >>> +#define ACC101_SIG_UL_4G 16
> >>> +#define ACC101_SIG_UL_4G_LAST 19
> >>> +#define ACC101_SIG_DL_4G 27
> >>> +#define ACC101_SIG_DL_4G_LAST 31
> >>> +#define ACC101_NUM_ACCS 5
> >>> +#define ACC101_PF_VAL 2
> >>> +
> >>> +/* ACC101 Configuration */
> >>> +#define ACC101_CFG_DMA_ERROR 0x3D7
> >>> +#define ACC101_CFG_AXI_CACHE 0x11
> >>> +#define ACC101_CFG_QMGR_HI_P 0x0F0F
> >>> +#define ACC101_CFG_PCI_AXI 0xC003
> >>> +#define ACC101_CFG_PCI_BRIDGE 0x40006033
> >>> +#define ACC101_ENGINE_OFFSET 0x1000
> >>> +#define ACC101_LONG_WAIT 1000
> >>> +#define ACC101_GPEX_AXIMAP_NUM 17
> >>> +#define ACC101_CLOCK_GATING_EN 0x30000
> >>> +#define ACC101_DMA_INBOUND 0x104
> >>> +/* DDR Size per VF - 512MB by default
> >>> + * Can be increased up to 4 GB with single PF/VF */
> >>> +#define ACC101_HARQ_DDR (512 * 1)
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (5 preceding siblings ...)
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
@ 2022-05-23 21:25 ` Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
` (4 more replies)
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
7 siblings, 5 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-23 21:25 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
v4: incremental updates based on reviews
Changed order of patchset to include two ACC100 specific commits first: updating formally the companion configure function from PF and the protection adjustment.
Then next 3 commits for the actual changes specific to ACC101: the device specific function for FCW 5GUL generation used as a local function, combined documentations into a single .rst common to both devices, updated comments, removed unused #defines.
v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section calling
the configure companion function for ACC100/101, taking the Pmon commit out
which is not directly required.
v2: Based on good feedback from Thomas and David,
now implementing the ACC101 PMD as a close derivative from
existing ACC100 PMD with hooks to have different behaviour based on variant.
This prevents code duplication and only rely on different functions and behaviour
when hardware requires or support differences.
Note that these are pending changes for ACC100 which would be specific to
that device and not ACC101 but these can be managed based on the new
implementation, ie. is_acc100() etc... (such incremental changes for ACC100
trending 22.11 but confirming this is future proof).
The serie also includes commits which were meant for ACC101 but are also
valuable for ACC100.
v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
This is a derivative from previous Mount Bryce ACC100 which includes silicon
improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
Nicolas Chautru (5):
baseband/acc100: update companion PF configure function
baseband/acc100: add protection for some negative scenario
baseband/acc100: introduce PMD for ACC101
baseband/acc100: modify validation code for ACC101
baseband/acc100: configuration of ACC101 from PF
MAINTAINERS | 1 +
app/test-bbdev/test_bbdev_perf.c | 22 +-
doc/guides/bbdevs/acc100.rst | 37 +-
doc/guides/bbdevs/features/acc101.ini | 13 +
doc/guides/bbdevs/index.rst | 1 +
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/acc100_pf_enum.h | 18 +
drivers/baseband/acc100/rte_acc100_cfg.h | 17 +
drivers/baseband/acc100/rte_acc100_pmd.c | 685 ++++++++++++++++++++++++++++---
drivers/baseband/acc100/rte_acc100_pmd.h | 26 ++
drivers/baseband/acc100/rte_acc101_pmd.h | 59 +++
drivers/baseband/acc100/version.map | 2 +-
12 files changed, 815 insertions(+), 69 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v4 1/5] baseband/acc100: update companion PF configure function
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
@ 2022-05-23 21:25 ` Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
` (3 subsequent siblings)
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-23 21:25 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Update of the device configuration function from PF used for bbdev-test
to latest sequence for ACC199 PRQ device and matching version in
pf_bb_config 22.03.
Fixes: b17d70922d5d ("baseband/acc100: add configure function")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++
drivers/baseband/acc100/rte_acc100_pmd.c | 150 ++++++++++++++++++++++++-------
drivers/baseband/acc100/rte_acc100_pmd.h | 15 ++++
3 files changed, 151 insertions(+), 32 deletions(-)
diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h
index a1ee416..2fba667 100644
--- a/drivers/baseband/acc100/acc100_pf_enum.h
+++ b/drivers/baseband/acc100/acc100_pf_enum.h
@@ -238,6 +238,24 @@ enum {
HWPfPermonBTotalLatLowBusMon = 0x00BAC504,
HWPfPermonBTotalLatUpperBusMon = 0x00BAC508,
HWPfPermonBTotalReqCntBusMon = 0x00BAC50C,
+ HwPfFabI2MArbCntrlReg = 0x00BB0000,
+ HWPfFabricMode = 0x00BB1000,
+ HwPfFabI2MGrp0DebugReg = 0x00BBF000,
+ HwPfFabI2MGrp1DebugReg = 0x00BBF004,
+ HwPfFabI2MGrp2DebugReg = 0x00BBF008,
+ HwPfFabI2MGrp3DebugReg = 0x00BBF00C,
+ HwPfFabI2MBuf0DebugReg = 0x00BBF010,
+ HwPfFabI2MBuf1DebugReg = 0x00BBF014,
+ HwPfFabI2MBuf2DebugReg = 0x00BBF018,
+ HwPfFabI2MBuf3DebugReg = 0x00BBF01C,
+ HwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020,
+ HwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024,
+ HwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028,
+ HwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C,
+ HwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030,
+ HwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034,
+ HwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038,
+ HwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C,
HWPfFecUl5gCntrlReg = 0x00BC0000,
HWPfFecUl5gI2MThreshReg = 0x00BC0004,
HWPfFecUl5gVersionReg = 0x00BC0100,
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index de7e4bc..9135c0e 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -4411,7 +4411,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
{
rte_bbdev_log(INFO, "rte_acc100_configure");
uint32_t value, address, status;
- int qg_idx, template_idx, vf_idx, acc, i;
+ int qg_idx, template_idx, vf_idx, acc, i, j;
struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
/* Compile time checks */
@@ -4431,6 +4431,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* Store configuration */
rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+ value = acc100_reg_read(d, HwPfPcieGpexBridgeControl);
+ bool firstCfg = (value != ACC100_CFG_PCI_BRIDGE);
+
/* PCIe Bridge configuration */
acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE);
for (i = 1; i < ACC100_GPEX_AXIMAP_NUM; i++)
@@ -4451,20 +4454,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = 1;
acc100_reg_write(d, address, value);
- /* DDR Configuration */
- address = HWPfDdrBcTim6;
- value = acc100_reg_read(d, address);
- value &= 0xFFFFFFFB; /* Bit 2 */
-#ifdef ACC100_DDR_ECC_ENABLE
- value |= 0x4;
-#endif
- acc100_reg_write(d, address, value);
- address = HWPfDdrPhyDqsCountNum;
-#ifdef ACC100_DDR_ECC_ENABLE
- value = 9;
-#else
- value = 8;
-#endif
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC100_CLOCK_GATING_EN;
acc100_reg_write(d, address, value);
/* Set default descriptor signature */
@@ -4482,6 +4474,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfDmaAxcacheReg;
acc100_reg_write(d, address, value);
+ /* Adjust PCIe Lane adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ for (j = 0; j < ACC100_LANES_PER_QUAD; j++)
+ acc100_reg_write(d, HwPfPcieLnAdaptctrl + i * ACC100_PCIE_QUAD_OFFSET
+ + j * ACC100_PCIE_LANE_OFFSET, ACC100_ADAPT);
+
+ /* Enable PCIe live adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ acc100_reg_write(d, HwPfPciePcsEqControl +
+ i * ACC100_PCIE_QUAD_OFFSET, ACC100_PCS_EQ);
+
/* Default DMA Configuration (Qmgr Enabled) */
address = HWPfDmaConfig0Reg;
value = 0;
@@ -4500,6 +4503,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = HWPfQmgrEgressQueuesTemplate;
acc100_reg_write(d, address, value);
+ /* Default Fabric Mode */
+ address = HWPfFabricMode;
+ value = ACC100_FABRIC_MODE;
+ acc100_reg_write(d, address, value);
+
/* ===== Qmgr Configuration ===== */
/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
int totalQgs = conf->q_ul_4g.num_qgroups +
@@ -4518,22 +4526,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Template Priority in incremental order */
- for (template_idx = 0; template_idx < ACC100_NUM_TMPL;
- template_idx++) {
- address = HWPfQmgrGrpTmplateReg0Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ for (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_0;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg1Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_1;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg2indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_2;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg3Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_3;
acc100_reg_write(d, address, value);
}
@@ -4623,7 +4626,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Queue Group Function mapping */
- int qman_func_id[5] = {0, 2, 1, 3, 4};
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
address = HWPfQmgrGrpFunction0;
value = 0;
for (qg_idx = 0; qg_idx < 8; qg_idx++) {
@@ -4654,7 +4657,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
}
- /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
uint32_t aram_address = 0;
for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
@@ -4679,6 +4682,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* ==== HI Configuration ==== */
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
/* Prevent Block on Transmit Error */
address = HWPfHiBlockTransmitOnErrorEn;
value = 0;
@@ -4691,10 +4699,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfHiPfMode;
value = (conf->pf_mode_en) ? ACC100_PF_VAL : 0;
acc100_reg_write(d, address, value);
- /* Enable Error Detection in HW */
- address = HWPfDmaErrorDetectionEn;
- value = 0x3D7;
- acc100_reg_write(d, address, value);
/* QoS overflow init */
value = 1;
@@ -4704,7 +4708,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
acc100_reg_write(d, address, value);
/* HARQ DDR Configuration */
- unsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */
+ unsigned int ddrSizeInMb = ACC100_HARQ_DDR;
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
address = HWPfDmaVfDdrBaseRw + vf_idx
* 0x10;
@@ -4718,6 +4722,88 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
if (numEngines < (ACC100_SIG_UL_5G_LAST + 1))
poweron_cleanup(bbdev, d, conf);
+ uint32_t version = 0;
+ for (i = 0; i < 4; i++)
+ version += acc100_reg_read(d,
+ HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
+ if (version != ACC100_PRQ_DDR_VER) {
+ printf("* Note: Not on DDR PRQ version %8x != %08x\n",
+ version, ACC100_PRQ_DDR_VER);
+ } else if (firstCfg) {
+ /* ---- DDR configuration at boot up --- */
+ /* Read Clear Ddr training status */
+ acc100_reg_read(d, HWPfChaDdrStDoneStatus);
+ /* Reset PHY/IDTM/UMMC */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 2);
+ usleep(ACC100_MS_IN_US);
+ /* Reset WB and APB resets */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 3);
+ /* Configure PHY-IDTM */
+ acc100_reg_write(d, HWPfDdrPhyIdletimeout, 0x3e8);
+ /* IDTM timing registers */
+ acc100_reg_write(d, HWPfDdrPhyRdLatency, 0x13);
+ acc100_reg_write(d, HWPfDdrPhyRdLatencyDbi, 0x15);
+ acc100_reg_write(d, HWPfDdrPhyWrLatency, 0x10011);
+ /* Configure SDRAM MRS registers */
+ acc100_reg_write(d, HWPfDdrPhyMr01Dimm, 0x3030b70);
+ acc100_reg_write(d, HWPfDdrPhyMr01DimmDbi, 0x3030b50);
+ acc100_reg_write(d, HWPfDdrPhyMr23Dimm, 0x30);
+ acc100_reg_write(d, HWPfDdrPhyMr67Dimm, 0xc00);
+ acc100_reg_write(d, HWPfDdrPhyMr45Dimm, 0x4000000);
+ /* Configure active lanes */
+ acc100_reg_write(d, HWPfDdrPhyDqsCountMax, 0x9);
+ acc100_reg_write(d, HWPfDdrPhyDqsCountNum, 0x9);
+ /* Configure WR/RD leveling timing registers */
+ acc100_reg_write(d, HWPfDdrPhyWrlvlWwRdlvlRr, 0x101212);
+ /* Configure what trainings to execute */
+ acc100_reg_write(d, HWPfDdrPhyTrngType, 0x2d3c);
+ /* Releasing PHY reset */
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 3);
+ /* Configure Memory Controller registers */
+ acc100_reg_write(d, HWPfDdrMemInitPhyTrng0, 0x3);
+ acc100_reg_write(d, HWPfDdrBcDram, 0x3c232003);
+ acc100_reg_write(d, HWPfDdrBcAddrMap, 0x31);
+ /* Configure UMMC BC timing registers */
+ acc100_reg_write(d, HWPfDdrBcRef, 0xa22);
+ acc100_reg_write(d, HWPfDdrBcTim0, 0x4050501);
+ acc100_reg_write(d, HWPfDdrBcTim1, 0xf0b0476);
+ acc100_reg_write(d, HWPfDdrBcTim2, 0x103);
+ acc100_reg_write(d, HWPfDdrBcTim3, 0x144050a1);
+ acc100_reg_write(d, HWPfDdrBcTim4, 0x23300);
+ acc100_reg_write(d, HWPfDdrBcTim5, 0x4230276);
+ acc100_reg_write(d, HWPfDdrBcTim6, 0x857914);
+ acc100_reg_write(d, HWPfDdrBcTim7, 0x79100232);
+ acc100_reg_write(d, HWPfDdrBcTim8, 0x100007ce);
+ acc100_reg_write(d, HWPfDdrBcTim9, 0x50020);
+ acc100_reg_write(d, HWPfDdrBcTim10, 0x40ee);
+ /* Configure UMMC DFI timing registers */
+ acc100_reg_write(d, HWPfDdrDfiInit, 0x5000);
+ acc100_reg_write(d, HWPfDdrDfiTim0, 0x15030006);
+ acc100_reg_write(d, HWPfDdrDfiTim1, 0x11305);
+ acc100_reg_write(d, HWPfDdrDfiPhyUpdEn, 0x1);
+ acc100_reg_write(d, HWPfDdrUmmcIntEn, 0x1f);
+ /* Release IDTM CPU out of reset */
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 0x2);
+ /* Wait PHY-IDTM to finish static training */
+ for (i = 0; i < ACC100_DDR_TRAINING_MAX; i++) {
+ usleep(ACC100_MS_IN_US);
+ value = acc100_reg_read(d,
+ HWPfChaDdrStDoneStatus);
+ if (value & 1)
+ break;
+ }
+ printf("DDR Training completed in %d ms", i);
+ /* Enable Memory Controller */
+ acc100_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
+ /* Release AXI interface reset */
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 3);
+ }
+
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index cbcece2..8fea322 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -153,6 +153,12 @@
#define ACC100_CFG_QMGR_HI_P 0x0F0F
#define ACC100_CFG_PCI_AXI 0xC003
#define ACC100_CFG_PCI_BRIDGE 0x40006033
+#define ACC100_QUAD_NUMS 4
+#define ACC100_LANES_PER_QUAD 4
+#define ACC100_PCIE_LANE_OFFSET 0x200
+#define ACC100_PCIE_QUAD_OFFSET 0x2000
+#define ACC100_PCS_EQ 0x6007
+#define ACC100_ADAPT 0x8400
#define ACC100_ENGINE_OFFSET 0x1000
#define ACC100_RESET_HI 0x20100
#define ACC100_RESET_LO 0x20000
@@ -160,6 +166,15 @@
#define ACC100_ENGINES_MAX 9
#define ACC100_LONG_WAIT 1000
#define ACC100_GPEX_AXIMAP_NUM 17
+#define ACC100_CLOCK_GATING_EN 0x30000
+#define ACC100_FABRIC_MODE 0xB
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC100_HARQ_DDR (512 * 1)
+#define ACC100_PRQ_DDR_VER 0x10092020
+#define ACC100_MS_IN_US (1000)
+#define ACC100_DDR_TRAINING_MAX (5000)
/* ACC100 DMA Descriptor triplet */
struct acc100_dma_triplet {
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v4 2/5] baseband/acc100: add protection for some negative scenario
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
@ 2022-05-23 21:25 ` Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
` (2 subsequent siblings)
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-23 21:25 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Catch exception in PMD in case of invalid input parameter.
Fixes: 5ad5060f8f7a ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 9135c0e..3fdf17d 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1236,6 +1236,8 @@
return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
}
/* LBRM case - includes a division by N */
+ if (unlikely(z_c == 0))
+ return 0;
if (rv_index == 1)
return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
/ n) * z_c;
@@ -1764,6 +1766,10 @@
/* Soft output */
if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
+ if (op->turbo_dec.soft_output.data == 0) {
+ rte_bbdev_log(ERR, "Soft output is not defined");
+ return -1;
+ }
if (check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_EQUALIZER))
*s_out_length = e;
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v4 3/5] baseband/acc100: introduce PMD for ACC101
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-05-23 21:25 ` Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-23 21:25 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Support for ACC101 as a derivative of ACC100.
Reusing existing code when possible.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
MAINTAINERS | 1 +
doc/guides/bbdevs/acc100.rst | 37 ++++--
doc/guides/bbdevs/features/acc101.ini | 13 +++
doc/guides/bbdevs/index.rst | 1 +
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/rte_acc100_pmd.c | 187 ++++++++++++++++++++++++++++++-
drivers/baseband/acc100/rte_acc100_pmd.h | 11 ++
drivers/baseband/acc100/rte_acc101_pmd.h | 59 ++++++++++
8 files changed, 294 insertions(+), 18 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 17a0559..0610128 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1318,6 +1318,7 @@ F: doc/guides/bbdevs/features/fpga_5gnr_fec.ini
F: drivers/baseband/acc100/
F: doc/guides/bbdevs/acc100.rst
F: doc/guides/bbdevs/features/acc100.ini
+F: doc/guides/bbdevs/features/acc101.ini
Null baseband
M: Nicolas Chautru <nicolas.chautru@intel.com>
diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst
index 9fff6ab..ff07ed9 100644
--- a/doc/guides/bbdevs/acc100.rst
+++ b/doc/guides/bbdevs/acc100.rst
@@ -1,17 +1,19 @@
.. SPDX-License-Identifier: BSD-3-Clause
Copyright(c) 2020 Intel Corporation
-Intel(R) ACC100 5G/4G FEC Poll Mode Driver
-==========================================
+Intel(R) ACC100 and ACC101 5G/4G FEC Poll Mode Drivers
+======================================================
The BBDEV ACC100 5G/4G FEC poll mode driver (PMD) supports an
implementation of a VRAN FEC wireless acceleration function.
This device is also known as Mount Bryce.
+The BBDEV ACC101, also known as Mount Cirrus, is a derivative device from Mount Bryce
+with functional and capacity improvements but still with the same exposed BBDEV capabilities.
Features
--------
-ACC100 5G/4G FEC PMD supports the following features:
+ACC100 and ACC101 5G/4G FEC PMDs support the following features:
- LDPC Encode in the DL (5GNR)
- LDPC Decode in the UL (5GNR)
@@ -23,7 +25,7 @@ ACC100 5G/4G FEC PMD supports the following features:
- MSI
- SR-IOV
-ACC100 5G/4G FEC PMD supports the following BBDEV capabilities:
+ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities:
* For the LDPC encode operation:
- ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
@@ -80,14 +82,16 @@ hugepage configuration of a server may be examined using:
Initialization
--------------
-When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+When the device first powers up, its PCI Physical Functions (PF) can be listed through these
+commands for ACC100 and ACC101 respectively:
.. code-block:: console
sudo lspci -vd8086:0d5c
+ sudo lspci -vd8086:57c4
The physical and virtual functions are compatible with Linux UIO drivers:
-``vfio`` and ``igb_uio``. However, in order to work the ACC100 5G/4G
+``vfio`` and ``igb_uio``. However, in order to work the 5G/4G
FEC device first needs to be bound to one of these linux drivers through DPDK.
@@ -97,7 +101,8 @@ Bind PF UIO driver(s)
Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
-The igb_uio driver may be bound to the PF PCI device using one of two methods:
+The igb_uio driver may be bound to the PF PCI device using one of two methods for ACC100
+(for ACC101 the device id ``57c4`` should be used in lieu of ``0d5c``):
1. PCI functions (physical or virtual, depending on the use case) can be bound to
@@ -121,7 +126,7 @@ the UIO driver by repeating this command for every function.
where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d5c
-In a similar way the ACC100 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
+In a similar way the 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
Enable Virtual Functions
@@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and other settings necessary for the
device to perform FEC functions.
This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the function ``acc100_configure()``, which sets up the
-parameters defined in ``acc100_conf`` structure.
+be achieved by using the functions ``acc100_configure()`` or ``acc101_configure()``,
+which sets up the parameters defined in the compatible ``acc100_conf`` structure.
Test Application
----------------
BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
-the functionality of ACC100 5G/4G FEC encode and decode, depending on the device's
+the functionality of the device 5G/4G FEC encode and decode, depending on the device's
capabilities. The test application is located under app->test-bbdev folder and has the
following options:
@@ -212,7 +217,7 @@ Test Vectors
In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
a range of additional tests under the test_vectors folder, which may be useful. The results
-of these tests will depend on the ACC100 5G/4G FEC capabilities which may cause some
+of these tests will depend on the device 5G/4G FEC capabilities which may cause some
testcases to be skipped, but no failure should be reported.
@@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command below can be used:
./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg
./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
+Specifically for the BBDEV ACC101 PMD, the command below can be used:
+
+.. code-block:: console
+
+ ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg
+ ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
new file mode 100644
index 0000000..0e2c21a
--- /dev/null
+++ b/doc/guides/bbdevs/features/acc101.ini
@@ -0,0 +1,13 @@
+;
+; Supported features of the 'acc101' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G) = Y
+Turbo Encoder (4G) = Y
+LDPC Decoder (5G) = Y
+LDPC Encoder (5G) = Y
+LLR/HARQ Compression = Y
+External DDR Access = Y
+HW Accelerated = Y
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index cedd706..e76883c 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -14,4 +14,5 @@ Baseband Device Drivers
fpga_lte_fec
fpga_5gnr_fec
acc100
+ acc101
la12xx
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index e49cace..1803947 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -104,6 +104,9 @@ New Features
* ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
* ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
+* **Added Intel ACC101 baseband PMD.**
+
+ * Added a new baseband PMD for Intel ACC101 device.
Removed Items
-------------
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 3fdf17d..5f422da 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -22,6 +22,7 @@
#include <rte_bbdev.h>
#include <rte_bbdev_pmd.h>
#include "rte_acc100_pmd.h"
+#include "rte_acc101_pmd.h"
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
@@ -1288,9 +1289,15 @@
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
}
+static inline bool
+is_acc100(struct acc100_queue *q)
+{
+ return (q->d->device_variant == ACC100_VARIANT);
+}
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
-acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
union acc100_harq_layout_data *harq_layout)
{
uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
@@ -1414,6 +1421,128 @@
}
}
+/* Convert offset to harq index for harq_layout structure */
+static inline uint32_t hq_index(uint32_t offset)
+{
+ return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
+}
+
+/* Fill in a frame control word for LDPC decoding for ACC101 */
+static inline void
+acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout)
+{
+ uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
+ uint32_t harq_index;
+ uint32_t l;
+
+ fcw->qm = op->ldpc_dec.q_m;
+ fcw->nfiller = op->ldpc_dec.n_filler;
+ fcw->BG = (op->ldpc_dec.basegraph - 1);
+ fcw->Zc = op->ldpc_dec.z_c;
+ fcw->ncb = op->ldpc_dec.n_cb;
+ fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
+ op->ldpc_dec.rv_index);
+ if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
+ fcw->rm_e = op->ldpc_dec.cb_params.e;
+ else
+ fcw->rm_e = (op->ldpc_dec.tb_params.r <
+ op->ldpc_dec.tb_params.cab) ?
+ op->ldpc_dec.tb_params.ea :
+ op->ldpc_dec.tb_params.eb;
+
+ if (unlikely(check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
+ (op->ldpc_dec.harq_combined_input.length == 0))) {
+ rte_bbdev_log(WARNING, "Null HARQ input size provided");
+ /* Disable HARQ input in that case to carry forward */
+ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+ }
+
+ fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+ fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+ fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+ fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DECODE_BYPASS);
+ fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
+ if (op->ldpc_dec.q_m == 1) {
+ fcw->bypass_intlv = 1;
+ fcw->qm = 2;
+ }
+ fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_LLR_COMPRESSION);
+ harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
+ if (fcw->hcin_en > 0) {
+ harq_in_length = op->ldpc_dec.harq_combined_input.length;
+ if (fcw->hcin_decomp_mode > 0)
+ harq_in_length = harq_in_length * 8 / 6;
+ harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
+ - op->ldpc_dec.n_filler);
+ /* Alignment on next 64B - Already enforced from HC output */
+ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
+ fcw->hcin_size0 = harq_in_length;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ } else {
+ fcw->hcin_size0 = 0;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ }
+
+ fcw->itmax = op->ldpc_dec.iter_max;
+ fcw->itstop = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+ fcw->synd_precoder = fcw->itstop;
+ /*
+ * These are all implicitly set
+ * fcw->synd_post = 0;
+ * fcw->so_en = 0;
+ * fcw->so_bypass_rm = 0;
+ * fcw->so_bypass_intlv = 0;
+ * fcw->dec_convllr = 0;
+ * fcw->hcout_convllr = 0;
+ * fcw->hcout_size1 = 0;
+ * fcw->so_it = 0;
+ * fcw->hcout_offset = 0;
+ * fcw->negstop_th = 0;
+ * fcw->negstop_it = 0;
+ * fcw->negstop_en = 0;
+ * fcw->gain_i = 1;
+ * fcw->gain_h = 1;
+ */
+ if (fcw->hcout_en > 0) {
+ parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
+ * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
+ k0_p = (fcw->k0 > parity_offset) ?
+ fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
+ ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
+ l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
+ harq_out_length = (uint16_t) fcw->hcin_size0;
+ harq_out_length = RTE_MAX(harq_out_length, l);
+ /* Cannot exceed the pruned Ncb circular buffer */
+ harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+ /* Alignment on next 64B */
+ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
+ fcw->hcout_size0 = harq_out_length;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ harq_layout[harq_index].offset = fcw->hcout_offset;
+ harq_layout[harq_index].size0 = fcw->hcout_size0;
+ } else {
+ fcw->hcout_size0 = 0;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ }
+}
+
/**
* Fills descriptor with data pointers of one block type.
*
@@ -2966,7 +3095,7 @@
struct acc100_fcw_ld *fcw;
uint32_t seg_total_left;
fcw = &desc->req.fcw_ld;
- acc100_fcw_ld_fill(op, fcw, harq_layout);
+ q->d->fcw_ld_fill(op, fcw, harq_layout);
/* Special handling when overusing mbuf */
if (fcw->rm_e < ACC100_MAX_E_MBUF)
@@ -3033,7 +3162,7 @@
desc = q->ring_addr + desc_idx;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
- acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
+ q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
input = op->ldpc_dec.input.data;
h_output_head = h_output = op->ldpc_dec.hard_output.data;
@@ -4145,9 +4274,19 @@
dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
- ((struct acc100_device *) dev->data->dev_private)->pf_device =
- !strcmp(drv->driver.name,
- RTE_STR(ACC100PF_DRIVER_NAME));
+ if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) ||
+ (!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc100_fcw_ld_fill;
+ } else {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc101_fcw_ld_fill;
+ }
+
((struct acc100_device *) dev->data->dev_private)->mmio_base =
pci_dev->mem_resource[0].addr;
@@ -4257,6 +4396,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);
RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);
+/* ACC101 PCI PF address map */
+static struct rte_pci_id pci_id_acc101_pf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+/* ACC101 PCI VF address map */
+static struct rte_pci_id pci_id_acc101_vf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+
+static struct rte_pci_driver acc101_pci_pf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_pf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+static struct rte_pci_driver acc101_pci_vf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_vf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);
+RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);
+
/*
* Workaround implementation to fix the power on status of some 5GUL engines
* This requires DMA permission if ported outside DPDK
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index 8fea322..39d5f22 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -22,6 +22,9 @@
#define rte_bbdev_log_debug(fmt, ...)
#endif
+#define ACC100_VARIANT 0
+#define ACC101_VARIANT 1
+
/* ACC100 PF and VF driver names */
#define ACC100PF_DRIVER_NAME intel_acc100_pf
#define ACC100VF_DRIVER_NAME intel_acc100_vf
@@ -67,6 +70,8 @@
#define ACC100_HARQ_LAYOUT (64*1024*1024)
/* Assume offset for HARQ in memory */
#define ACC100_HARQ_OFFSET (32*1024)
+#define ACC100_HARQ_OFFSET_SHIFT 15
+#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
#define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
/* Number of Virtual Functions ACC100 supports */
@@ -574,6 +579,10 @@ struct __rte_cache_aligned acc100_queue {
struct acc100_device *d;
};
+typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,
+ struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout);
+
/* Private data structure for each ACC100 device */
struct acc100_device {
void *mmio_base; /**< Base address of MMIO registers (BAR0) */
@@ -605,6 +614,8 @@ struct acc100_device {
uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
bool pf_device; /**< True if this is a PF ACC100 device */
bool configured; /**< True if this ACC100 device is configured */
+ uint16_t device_variant; /**< Device variant */
+ acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation function */
};
/**
diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h
new file mode 100644
index 0000000..3e419cb
--- /dev/null
+++ b/drivers/baseband/acc100/rte_acc101_pmd.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+/* ACC101 PF and VF driver names */
+#define ACC101PF_DRIVER_NAME intel_acc101_pf
+#define ACC101VF_DRIVER_NAME intel_acc101_vf
+
+/* ACC101 PCI vendor & device IDs */
+#define RTE_ACC101_VENDOR_ID (0x8086)
+#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
+#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
+
+/* Define as 1 to use only a single FEC engine */
+#ifndef RTE_ACC101_SINGLE_FEC
+#define RTE_ACC101_SINGLE_FEC 0
+#endif
+
+/* Number of Virtual Functions ACC101 supports */
+#define ACC101_NUM_VFS 16
+#define ACC101_NUM_QGRPS 8
+#define ACC101_NUM_AQS 16
+/* All ACC101 Registers alignment are 32bits = 4B */
+#define ACC101_BYTES_IN_WORD 4
+
+#define ACC101_TMPL_PRI_0 0x03020100
+#define ACC101_TMPL_PRI_1 0x07060504
+#define ACC101_TMPL_PRI_2 0x0b0a0908
+#define ACC101_TMPL_PRI_3 0x0f0e0d0c
+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
+
+#define ACC101_NUM_TMPL 32
+/* Mapping of signals for the available engines */
+#define ACC101_SIG_UL_5G 0
+#define ACC101_SIG_UL_5G_LAST 8
+#define ACC101_SIG_DL_5G 13
+#define ACC101_SIG_DL_5G_LAST 15
+#define ACC101_SIG_UL_4G 16
+#define ACC101_SIG_UL_4G_LAST 19
+#define ACC101_SIG_DL_4G 27
+#define ACC101_SIG_DL_4G_LAST 31
+#define ACC101_NUM_ACCS 5
+#define ACC101_PF_VAL 2
+
+/* ACC101 Configuration */
+#define ACC101_CFG_DMA_ERROR 0x3D7
+#define ACC101_CFG_AXI_CACHE 0x11
+#define ACC101_CFG_QMGR_HI_P 0x0F0F
+#define ACC101_CFG_PCI_AXI 0xC003
+#define ACC101_CFG_PCI_BRIDGE 0x40006033
+#define ACC101_ENGINE_OFFSET 0x1000
+#define ACC101_LONG_WAIT 1000
+#define ACC101_GPEX_AXIMAP_NUM 17
+#define ACC101_CLOCK_GATING_EN 0x30000
+#define ACC101_DMA_INBOUND 0x104
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC101_HARQ_DDR (512 * 1)
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v4 4/5] baseband/acc100: modify validation code for ACC101
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (2 preceding siblings ...)
2022-05-23 21:25 ` [PATCH v4 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-23 21:25 ` Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-23 21:25 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
The validation requirement is different for the two
devices.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 40 ++++++++++++++++++++++----------
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 5f422da..65b8fac 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1295,6 +1295,14 @@
return (q->d->device_variant == ACC100_VARIANT);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+static inline bool
+validate_op_required(struct acc100_queue *q)
+{
+ return is_acc100(q);
+}
+#endif
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -2182,8 +2190,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo encoder parameters */
static inline int
-validate_enc_op(struct rte_bbdev_enc_op *op)
+validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
@@ -2320,8 +2330,10 @@ static inline uint32_t hq_index(uint32_t offset)
}
/* Validates LDPC encoder parameters */
static inline int
-validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
+validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
if (op->mempool == NULL) {
@@ -2373,8 +2385,10 @@ static inline uint32_t hq_index(uint32_t offset)
/* Validates LDPC decoder parameters */
static inline int
-validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
+validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
if (op->mempool == NULL) {
@@ -2429,7 +2443,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2483,7 +2497,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(ops[0]) == -1) {
+ if (validate_ldpc_enc_op(ops[0], q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2545,7 +2559,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(op) == -1) {
+ if (validate_ldpc_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2602,7 +2616,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2675,8 +2689,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo decoder parameters */
static inline int
-validate_dec_op(struct rte_bbdev_dec_op *op)
+validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
@@ -2822,7 +2838,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
@@ -3047,7 +3063,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3151,7 +3167,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3241,7 +3257,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v4 5/5] baseband/acc100: configuration of ACC101 from PF
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (3 preceding siblings ...)
2022-05-23 21:25 ` [PATCH v4 4/5] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-23 21:25 ` Nicolas Chautru
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-23 21:25 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Adding companion function specific to ACC100 and it
can be called from bbdev-test when running from PF.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 22 ++-
drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++
drivers/baseband/acc100/version.map | 2 +-
4 files changed, 336 insertions(+), 7 deletions(-)
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 0fa119a..89b1e79 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -63,6 +63,8 @@
#define ACC100_QMGR_INVALID_IDX -1
#define ACC100_QMGR_RR 1
#define ACC100_QOS_GBR 0
+#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
+#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
#endif
#define OPS_CACHE_SIZE 256U
@@ -711,11 +713,12 @@ typedef int (test_case_function)(struct active_device *ad,
#endif
#ifdef RTE_BASEBAND_ACC100
if ((get_init_device() == true) &&
- (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
+ ((!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) ||
+ (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))) {
struct rte_acc100_conf conf;
unsigned int i;
- printf("Configure ACC100 FEC Driver %s with default values\n",
+ printf("Configure ACC100/ACC101 FEC Driver %s with default values\n",
info->drv.driver_name);
/* clear default configuration before initialization */
@@ -760,10 +763,17 @@ typedef int (test_case_function)(struct active_device *ad,
conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
/* setup PF with configuration information */
- ret = rte_acc100_configure(info->dev_name, &conf);
- TEST_ASSERT_SUCCESS(ret,
- "Failed to configure ACC100 PF for bbdev %s",
- info->dev_name);
+ if (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) {
+ ret = rte_acc100_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC100 PF for bbdev %s",
+ info->dev_name);
+ } else {
+ ret = rte_acc101_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC101 PF for bbdev %s",
+ info->dev_name);
+ }
}
#endif
/* Let's refresh this now this is configured */
diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
index d233e42..2e3c43f 100644
--- a/drivers/baseband/acc100/rte_acc100_cfg.h
+++ b/drivers/baseband/acc100/rte_acc100_cfg.h
@@ -106,6 +106,23 @@ struct rte_acc100_conf {
int
rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
+/**
+ * Configure a ACC101 device
+ *
+ * @param dev_name
+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ * It can also be retrieved for a bbdev device from the dev_name field in the
+ * rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ * Configuration to apply to ACC101 HW.
+ *
+ * @return
+ * Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 65b8fac..decd01d 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -5004,3 +5004,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
+
+
+/* Initial configuration of a ACC101 device prior to running configure() */
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc101_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc100_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+
+ /* PCIe Bridge configuration */
+ acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
+ for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
+ acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
+
+ /* Prevent blocking AXI read on BRESP for AXI Write */
+ address = HwPfPcieGpexAxiPioControl;
+ value = ACC101_CFG_PCI_AXI;
+ acc100_reg_write(d, address, value);
+
+ /* Explicitly releasing AXI including a 2ms delay on ACC101 */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* Set the default 5GDL DMA configuration */
+ acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
+
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC101_CLOCK_GATING_EN;
+ acc100_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC101_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc100_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC101_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc100_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ address = HWPfDmaConfig1Reg;
+ int alen_r = 0xF;
+ int alen_w = 0x7;
+ value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
+ acc100_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc100_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_1;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_2;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_3;
+ acc100_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC101_CFG_QMGR_HI_P;
+ acc100_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_4G;
+ template_idx <= ACC101_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_5G;
+ template_idx <= ACC101_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg +
+ ACC101_ENGINE_OFFSET * template_idx;
+ status = (acc100_reg_read(d, address) >> 4) & 0xF;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc100_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc100_reg_write(d, address, 0);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ printf("Number of 5GUL engines %d\n", numEngines);
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_4G;
+ template_idx <= ACC101_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_5G;
+ template_idx <= ACC101_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ address = HWPfQmgrGrpFunction0;
+ value = 0;
+ for (qg_idx = 0; qg_idx < 8; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc]<<(qg_idx * 4);
+ }
+ acc100_reg_write(d, address, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC101_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc100_reg_write(d, address, value);
+ }
+ }
+
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC101_BYTES_IN_WORD + qg_idx
+ * ACC101_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc100_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC101_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
+ acc100_reg_write(d, address, value);
+ /* Explicitly releasing AXI after PF Mode and 2 ms */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc100_reg_write(d, address, value);
+
+ /* HARQ DDR Configuration */
+ unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfDmaVfDdrBaseRw + vf_idx
+ * 0x10;
+ value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
+ (ddrSizeInMb - 1);
+ acc100_reg_write(d, address, value);
+ }
+ usleep(ACC101_LONG_WAIT);
+
+ rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
+ return 0;
+}
diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map
index 40604c7..37b850f 100644
--- a/drivers/baseband/acc100/version.map
+++ b/drivers/baseband/acc100/version.map
@@ -6,5 +6,5 @@ EXPERIMENTAL {
global:
rte_acc100_configure;
-
+ rte_acc101_configure;
};
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
` (6 preceding siblings ...)
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
@ 2022-05-24 0:08 ` Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
` (7 more replies)
7 siblings, 8 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-24 0:08 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
v5: minor fix to doc and intermediate commit caught in CI
v4: incremental updates based on reviews Changed order of patchset to include two ACC100 specific commits first: updating formally the companion configure function from PF and the protection adjustment.
Then next 3 commits for the actual changes specific to ACC101: the device specific function for FCW 5GUL generation used as a local function, combined documentations into a single .rst common to both devices, updated comments, removed unused #defines.
v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section calling the configure companion function for ACC100/101, taking the Pmon commit out which is not directly required.
v2: Based on good feedback from Thomas and David, now implementing the ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to have different behaviour based on variant.
This prevents code duplication and only rely on different functions and behaviour when hardware requires or support differences.
Note that these are pending changes for ACC100 which would be specific to that device and not ACC101 but these can be managed based on the new implementation, ie. is_acc100() etc... (such incremental changes for ACC100 trending 22.11 but confirming this is future proof).
The serie also includes commits which were meant for ACC101 but are also valuable for ACC100.
v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
This is a derivative from previous Mount Bryce ACC100 which includes silicon improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
Nicolas Chautru (5):
baseband/acc100: update companion PF configure function
baseband/acc100: add protection for some negative scenario
baseband/acc100: introduce PMD for ACC101
baseband/acc100: modify validation code for ACC101
baseband/acc100: configuration of ACC101 from PF
MAINTAINERS | 1 +
app/test-bbdev/test_bbdev_perf.c | 22 +-
doc/guides/bbdevs/acc100.rst | 37 +-
doc/guides/bbdevs/features/acc101.ini | 13 +
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/acc100_pf_enum.h | 18 +
drivers/baseband/acc100/rte_acc100_cfg.h | 17 +
drivers/baseband/acc100/rte_acc100_pmd.c | 686 ++++++++++++++++++++++++++++---
drivers/baseband/acc100/rte_acc100_pmd.h | 26 ++
drivers/baseband/acc100/rte_acc101_pmd.h | 59 +++
drivers/baseband/acc100/version.map | 2 +-
11 files changed, 815 insertions(+), 69 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v5 1/5] baseband/acc100: update companion PF configure function
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
@ 2022-05-24 0:08 ` Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
` (6 subsequent siblings)
7 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-24 0:08 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Update of the device configuration function from PF used for bbdev-test
to latest sequence for ACC199 PRQ device and matching version in
pf_bb_config 22.03.
Fixes: b17d70922d5d ("baseband/acc100: add configure function")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++
drivers/baseband/acc100/rte_acc100_pmd.c | 150 ++++++++++++++++++++++++-------
drivers/baseband/acc100/rte_acc100_pmd.h | 15 ++++
3 files changed, 151 insertions(+), 32 deletions(-)
diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h
index a1ee416..2fba667 100644
--- a/drivers/baseband/acc100/acc100_pf_enum.h
+++ b/drivers/baseband/acc100/acc100_pf_enum.h
@@ -238,6 +238,24 @@ enum {
HWPfPermonBTotalLatLowBusMon = 0x00BAC504,
HWPfPermonBTotalLatUpperBusMon = 0x00BAC508,
HWPfPermonBTotalReqCntBusMon = 0x00BAC50C,
+ HwPfFabI2MArbCntrlReg = 0x00BB0000,
+ HWPfFabricMode = 0x00BB1000,
+ HwPfFabI2MGrp0DebugReg = 0x00BBF000,
+ HwPfFabI2MGrp1DebugReg = 0x00BBF004,
+ HwPfFabI2MGrp2DebugReg = 0x00BBF008,
+ HwPfFabI2MGrp3DebugReg = 0x00BBF00C,
+ HwPfFabI2MBuf0DebugReg = 0x00BBF010,
+ HwPfFabI2MBuf1DebugReg = 0x00BBF014,
+ HwPfFabI2MBuf2DebugReg = 0x00BBF018,
+ HwPfFabI2MBuf3DebugReg = 0x00BBF01C,
+ HwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020,
+ HwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024,
+ HwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028,
+ HwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C,
+ HwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030,
+ HwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034,
+ HwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038,
+ HwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C,
HWPfFecUl5gCntrlReg = 0x00BC0000,
HWPfFecUl5gI2MThreshReg = 0x00BC0004,
HWPfFecUl5gVersionReg = 0x00BC0100,
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index de7e4bc..9135c0e 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -4411,7 +4411,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
{
rte_bbdev_log(INFO, "rte_acc100_configure");
uint32_t value, address, status;
- int qg_idx, template_idx, vf_idx, acc, i;
+ int qg_idx, template_idx, vf_idx, acc, i, j;
struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
/* Compile time checks */
@@ -4431,6 +4431,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* Store configuration */
rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+ value = acc100_reg_read(d, HwPfPcieGpexBridgeControl);
+ bool firstCfg = (value != ACC100_CFG_PCI_BRIDGE);
+
/* PCIe Bridge configuration */
acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE);
for (i = 1; i < ACC100_GPEX_AXIMAP_NUM; i++)
@@ -4451,20 +4454,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = 1;
acc100_reg_write(d, address, value);
- /* DDR Configuration */
- address = HWPfDdrBcTim6;
- value = acc100_reg_read(d, address);
- value &= 0xFFFFFFFB; /* Bit 2 */
-#ifdef ACC100_DDR_ECC_ENABLE
- value |= 0x4;
-#endif
- acc100_reg_write(d, address, value);
- address = HWPfDdrPhyDqsCountNum;
-#ifdef ACC100_DDR_ECC_ENABLE
- value = 9;
-#else
- value = 8;
-#endif
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC100_CLOCK_GATING_EN;
acc100_reg_write(d, address, value);
/* Set default descriptor signature */
@@ -4482,6 +4474,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfDmaAxcacheReg;
acc100_reg_write(d, address, value);
+ /* Adjust PCIe Lane adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ for (j = 0; j < ACC100_LANES_PER_QUAD; j++)
+ acc100_reg_write(d, HwPfPcieLnAdaptctrl + i * ACC100_PCIE_QUAD_OFFSET
+ + j * ACC100_PCIE_LANE_OFFSET, ACC100_ADAPT);
+
+ /* Enable PCIe live adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ acc100_reg_write(d, HwPfPciePcsEqControl +
+ i * ACC100_PCIE_QUAD_OFFSET, ACC100_PCS_EQ);
+
/* Default DMA Configuration (Qmgr Enabled) */
address = HWPfDmaConfig0Reg;
value = 0;
@@ -4500,6 +4503,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = HWPfQmgrEgressQueuesTemplate;
acc100_reg_write(d, address, value);
+ /* Default Fabric Mode */
+ address = HWPfFabricMode;
+ value = ACC100_FABRIC_MODE;
+ acc100_reg_write(d, address, value);
+
/* ===== Qmgr Configuration ===== */
/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
int totalQgs = conf->q_ul_4g.num_qgroups +
@@ -4518,22 +4526,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Template Priority in incremental order */
- for (template_idx = 0; template_idx < ACC100_NUM_TMPL;
- template_idx++) {
- address = HWPfQmgrGrpTmplateReg0Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ for (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_0;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg1Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_1;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg2indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_2;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg3Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_3;
acc100_reg_write(d, address, value);
}
@@ -4623,7 +4626,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Queue Group Function mapping */
- int qman_func_id[5] = {0, 2, 1, 3, 4};
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
address = HWPfQmgrGrpFunction0;
value = 0;
for (qg_idx = 0; qg_idx < 8; qg_idx++) {
@@ -4654,7 +4657,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
}
- /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
uint32_t aram_address = 0;
for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
@@ -4679,6 +4682,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* ==== HI Configuration ==== */
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
/* Prevent Block on Transmit Error */
address = HWPfHiBlockTransmitOnErrorEn;
value = 0;
@@ -4691,10 +4699,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfHiPfMode;
value = (conf->pf_mode_en) ? ACC100_PF_VAL : 0;
acc100_reg_write(d, address, value);
- /* Enable Error Detection in HW */
- address = HWPfDmaErrorDetectionEn;
- value = 0x3D7;
- acc100_reg_write(d, address, value);
/* QoS overflow init */
value = 1;
@@ -4704,7 +4708,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
acc100_reg_write(d, address, value);
/* HARQ DDR Configuration */
- unsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */
+ unsigned int ddrSizeInMb = ACC100_HARQ_DDR;
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
address = HWPfDmaVfDdrBaseRw + vf_idx
* 0x10;
@@ -4718,6 +4722,88 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
if (numEngines < (ACC100_SIG_UL_5G_LAST + 1))
poweron_cleanup(bbdev, d, conf);
+ uint32_t version = 0;
+ for (i = 0; i < 4; i++)
+ version += acc100_reg_read(d,
+ HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
+ if (version != ACC100_PRQ_DDR_VER) {
+ printf("* Note: Not on DDR PRQ version %8x != %08x\n",
+ version, ACC100_PRQ_DDR_VER);
+ } else if (firstCfg) {
+ /* ---- DDR configuration at boot up --- */
+ /* Read Clear Ddr training status */
+ acc100_reg_read(d, HWPfChaDdrStDoneStatus);
+ /* Reset PHY/IDTM/UMMC */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 2);
+ usleep(ACC100_MS_IN_US);
+ /* Reset WB and APB resets */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 3);
+ /* Configure PHY-IDTM */
+ acc100_reg_write(d, HWPfDdrPhyIdletimeout, 0x3e8);
+ /* IDTM timing registers */
+ acc100_reg_write(d, HWPfDdrPhyRdLatency, 0x13);
+ acc100_reg_write(d, HWPfDdrPhyRdLatencyDbi, 0x15);
+ acc100_reg_write(d, HWPfDdrPhyWrLatency, 0x10011);
+ /* Configure SDRAM MRS registers */
+ acc100_reg_write(d, HWPfDdrPhyMr01Dimm, 0x3030b70);
+ acc100_reg_write(d, HWPfDdrPhyMr01DimmDbi, 0x3030b50);
+ acc100_reg_write(d, HWPfDdrPhyMr23Dimm, 0x30);
+ acc100_reg_write(d, HWPfDdrPhyMr67Dimm, 0xc00);
+ acc100_reg_write(d, HWPfDdrPhyMr45Dimm, 0x4000000);
+ /* Configure active lanes */
+ acc100_reg_write(d, HWPfDdrPhyDqsCountMax, 0x9);
+ acc100_reg_write(d, HWPfDdrPhyDqsCountNum, 0x9);
+ /* Configure WR/RD leveling timing registers */
+ acc100_reg_write(d, HWPfDdrPhyWrlvlWwRdlvlRr, 0x101212);
+ /* Configure what trainings to execute */
+ acc100_reg_write(d, HWPfDdrPhyTrngType, 0x2d3c);
+ /* Releasing PHY reset */
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 3);
+ /* Configure Memory Controller registers */
+ acc100_reg_write(d, HWPfDdrMemInitPhyTrng0, 0x3);
+ acc100_reg_write(d, HWPfDdrBcDram, 0x3c232003);
+ acc100_reg_write(d, HWPfDdrBcAddrMap, 0x31);
+ /* Configure UMMC BC timing registers */
+ acc100_reg_write(d, HWPfDdrBcRef, 0xa22);
+ acc100_reg_write(d, HWPfDdrBcTim0, 0x4050501);
+ acc100_reg_write(d, HWPfDdrBcTim1, 0xf0b0476);
+ acc100_reg_write(d, HWPfDdrBcTim2, 0x103);
+ acc100_reg_write(d, HWPfDdrBcTim3, 0x144050a1);
+ acc100_reg_write(d, HWPfDdrBcTim4, 0x23300);
+ acc100_reg_write(d, HWPfDdrBcTim5, 0x4230276);
+ acc100_reg_write(d, HWPfDdrBcTim6, 0x857914);
+ acc100_reg_write(d, HWPfDdrBcTim7, 0x79100232);
+ acc100_reg_write(d, HWPfDdrBcTim8, 0x100007ce);
+ acc100_reg_write(d, HWPfDdrBcTim9, 0x50020);
+ acc100_reg_write(d, HWPfDdrBcTim10, 0x40ee);
+ /* Configure UMMC DFI timing registers */
+ acc100_reg_write(d, HWPfDdrDfiInit, 0x5000);
+ acc100_reg_write(d, HWPfDdrDfiTim0, 0x15030006);
+ acc100_reg_write(d, HWPfDdrDfiTim1, 0x11305);
+ acc100_reg_write(d, HWPfDdrDfiPhyUpdEn, 0x1);
+ acc100_reg_write(d, HWPfDdrUmmcIntEn, 0x1f);
+ /* Release IDTM CPU out of reset */
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 0x2);
+ /* Wait PHY-IDTM to finish static training */
+ for (i = 0; i < ACC100_DDR_TRAINING_MAX; i++) {
+ usleep(ACC100_MS_IN_US);
+ value = acc100_reg_read(d,
+ HWPfChaDdrStDoneStatus);
+ if (value & 1)
+ break;
+ }
+ printf("DDR Training completed in %d ms", i);
+ /* Enable Memory Controller */
+ acc100_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
+ /* Release AXI interface reset */
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 3);
+ }
+
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index cbcece2..8fea322 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -153,6 +153,12 @@
#define ACC100_CFG_QMGR_HI_P 0x0F0F
#define ACC100_CFG_PCI_AXI 0xC003
#define ACC100_CFG_PCI_BRIDGE 0x40006033
+#define ACC100_QUAD_NUMS 4
+#define ACC100_LANES_PER_QUAD 4
+#define ACC100_PCIE_LANE_OFFSET 0x200
+#define ACC100_PCIE_QUAD_OFFSET 0x2000
+#define ACC100_PCS_EQ 0x6007
+#define ACC100_ADAPT 0x8400
#define ACC100_ENGINE_OFFSET 0x1000
#define ACC100_RESET_HI 0x20100
#define ACC100_RESET_LO 0x20000
@@ -160,6 +166,15 @@
#define ACC100_ENGINES_MAX 9
#define ACC100_LONG_WAIT 1000
#define ACC100_GPEX_AXIMAP_NUM 17
+#define ACC100_CLOCK_GATING_EN 0x30000
+#define ACC100_FABRIC_MODE 0xB
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC100_HARQ_DDR (512 * 1)
+#define ACC100_PRQ_DDR_VER 0x10092020
+#define ACC100_MS_IN_US (1000)
+#define ACC100_DDR_TRAINING_MAX (5000)
/* ACC100 DMA Descriptor triplet */
struct acc100_dma_triplet {
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v5 2/5] baseband/acc100: add protection for some negative scenario
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
@ 2022-05-24 0:08 ` Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
` (5 subsequent siblings)
7 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-24 0:08 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Catch exception in PMD in case of invalid input parameter.
Fixes: 5ad5060f8f7a ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 9135c0e..3fdf17d 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1236,6 +1236,8 @@
return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
}
/* LBRM case - includes a division by N */
+ if (unlikely(z_c == 0))
+ return 0;
if (rv_index == 1)
return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
/ n) * z_c;
@@ -1764,6 +1766,10 @@
/* Soft output */
if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
+ if (op->turbo_dec.soft_output.data == 0) {
+ rte_bbdev_log(ERR, "Soft output is not defined");
+ return -1;
+ }
if (check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_EQUALIZER))
*s_out_length = e;
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v5 3/5] baseband/acc100: introduce PMD for ACC101
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-05-24 0:08 ` Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 4/5] baseband/acc100: modify validation code " Nicolas Chautru
` (4 subsequent siblings)
7 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-24 0:08 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Support for ACC101 as a derivative of ACC100.
Reusing existing code when possible.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
MAINTAINERS | 1 +
doc/guides/bbdevs/acc100.rst | 37 +++++--
doc/guides/bbdevs/features/acc101.ini | 13 +++
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/rte_acc100_pmd.c | 181 ++++++++++++++++++++++++++++++-
drivers/baseband/acc100/rte_acc100_pmd.h | 11 ++
drivers/baseband/acc100/rte_acc101_pmd.h | 59 ++++++++++
7 files changed, 287 insertions(+), 18 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 17a0559..0610128 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1318,6 +1318,7 @@ F: doc/guides/bbdevs/features/fpga_5gnr_fec.ini
F: drivers/baseband/acc100/
F: doc/guides/bbdevs/acc100.rst
F: doc/guides/bbdevs/features/acc100.ini
+F: doc/guides/bbdevs/features/acc101.ini
Null baseband
M: Nicolas Chautru <nicolas.chautru@intel.com>
diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst
index 9fff6ab..ff07ed9 100644
--- a/doc/guides/bbdevs/acc100.rst
+++ b/doc/guides/bbdevs/acc100.rst
@@ -1,17 +1,19 @@
.. SPDX-License-Identifier: BSD-3-Clause
Copyright(c) 2020 Intel Corporation
-Intel(R) ACC100 5G/4G FEC Poll Mode Driver
-==========================================
+Intel(R) ACC100 and ACC101 5G/4G FEC Poll Mode Drivers
+======================================================
The BBDEV ACC100 5G/4G FEC poll mode driver (PMD) supports an
implementation of a VRAN FEC wireless acceleration function.
This device is also known as Mount Bryce.
+The BBDEV ACC101, also known as Mount Cirrus, is a derivative device from Mount Bryce
+with functional and capacity improvements but still with the same exposed BBDEV capabilities.
Features
--------
-ACC100 5G/4G FEC PMD supports the following features:
+ACC100 and ACC101 5G/4G FEC PMDs support the following features:
- LDPC Encode in the DL (5GNR)
- LDPC Decode in the UL (5GNR)
@@ -23,7 +25,7 @@ ACC100 5G/4G FEC PMD supports the following features:
- MSI
- SR-IOV
-ACC100 5G/4G FEC PMD supports the following BBDEV capabilities:
+ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities:
* For the LDPC encode operation:
- ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
@@ -80,14 +82,16 @@ hugepage configuration of a server may be examined using:
Initialization
--------------
-When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+When the device first powers up, its PCI Physical Functions (PF) can be listed through these
+commands for ACC100 and ACC101 respectively:
.. code-block:: console
sudo lspci -vd8086:0d5c
+ sudo lspci -vd8086:57c4
The physical and virtual functions are compatible with Linux UIO drivers:
-``vfio`` and ``igb_uio``. However, in order to work the ACC100 5G/4G
+``vfio`` and ``igb_uio``. However, in order to work the 5G/4G
FEC device first needs to be bound to one of these linux drivers through DPDK.
@@ -97,7 +101,8 @@ Bind PF UIO driver(s)
Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
-The igb_uio driver may be bound to the PF PCI device using one of two methods:
+The igb_uio driver may be bound to the PF PCI device using one of two methods for ACC100
+(for ACC101 the device id ``57c4`` should be used in lieu of ``0d5c``):
1. PCI functions (physical or virtual, depending on the use case) can be bound to
@@ -121,7 +126,7 @@ the UIO driver by repeating this command for every function.
where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d5c
-In a similar way the ACC100 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
+In a similar way the 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
Enable Virtual Functions
@@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and other settings necessary for the
device to perform FEC functions.
This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the function ``acc100_configure()``, which sets up the
-parameters defined in ``acc100_conf`` structure.
+be achieved by using the functions ``acc100_configure()`` or ``acc101_configure()``,
+which sets up the parameters defined in the compatible ``acc100_conf`` structure.
Test Application
----------------
BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
-the functionality of ACC100 5G/4G FEC encode and decode, depending on the device's
+the functionality of the device 5G/4G FEC encode and decode, depending on the device's
capabilities. The test application is located under app->test-bbdev folder and has the
following options:
@@ -212,7 +217,7 @@ Test Vectors
In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
a range of additional tests under the test_vectors folder, which may be useful. The results
-of these tests will depend on the ACC100 5G/4G FEC capabilities which may cause some
+of these tests will depend on the device 5G/4G FEC capabilities which may cause some
testcases to be skipped, but no failure should be reported.
@@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command below can be used:
./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg
./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
+Specifically for the BBDEV ACC101 PMD, the command below can be used:
+
+.. code-block:: console
+
+ ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg
+ ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
new file mode 100644
index 0000000..0e2c21a
--- /dev/null
+++ b/doc/guides/bbdevs/features/acc101.ini
@@ -0,0 +1,13 @@
+;
+; Supported features of the 'acc101' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G) = Y
+Turbo Encoder (4G) = Y
+LDPC Decoder (5G) = Y
+LDPC Encoder (5G) = Y
+LLR/HARQ Compression = Y
+External DDR Access = Y
+HW Accelerated = Y
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index e49cace..1803947 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -104,6 +104,9 @@ New Features
* ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
* ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
+* **Added Intel ACC101 baseband PMD.**
+
+ * Added a new baseband PMD for Intel ACC101 device.
Removed Items
-------------
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 3fdf17d..41475b2 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -22,6 +22,7 @@
#include <rte_bbdev.h>
#include <rte_bbdev_pmd.h>
#include "rte_acc100_pmd.h"
+#include "rte_acc101_pmd.h"
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
@@ -1290,7 +1291,7 @@
/* Fill in a frame control word for LDPC decoding. */
static inline void
-acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
union acc100_harq_layout_data *harq_layout)
{
uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
@@ -1414,6 +1415,128 @@
}
}
+/* Convert offset to harq index for harq_layout structure */
+static inline uint32_t hq_index(uint32_t offset)
+{
+ return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
+}
+
+/* Fill in a frame control word for LDPC decoding for ACC101 */
+static inline void
+acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout)
+{
+ uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
+ uint32_t harq_index;
+ uint32_t l;
+
+ fcw->qm = op->ldpc_dec.q_m;
+ fcw->nfiller = op->ldpc_dec.n_filler;
+ fcw->BG = (op->ldpc_dec.basegraph - 1);
+ fcw->Zc = op->ldpc_dec.z_c;
+ fcw->ncb = op->ldpc_dec.n_cb;
+ fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
+ op->ldpc_dec.rv_index);
+ if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
+ fcw->rm_e = op->ldpc_dec.cb_params.e;
+ else
+ fcw->rm_e = (op->ldpc_dec.tb_params.r <
+ op->ldpc_dec.tb_params.cab) ?
+ op->ldpc_dec.tb_params.ea :
+ op->ldpc_dec.tb_params.eb;
+
+ if (unlikely(check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
+ (op->ldpc_dec.harq_combined_input.length == 0))) {
+ rte_bbdev_log(WARNING, "Null HARQ input size provided");
+ /* Disable HARQ input in that case to carry forward */
+ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+ }
+
+ fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+ fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+ fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+ fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DECODE_BYPASS);
+ fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
+ if (op->ldpc_dec.q_m == 1) {
+ fcw->bypass_intlv = 1;
+ fcw->qm = 2;
+ }
+ fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_LLR_COMPRESSION);
+ harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
+ if (fcw->hcin_en > 0) {
+ harq_in_length = op->ldpc_dec.harq_combined_input.length;
+ if (fcw->hcin_decomp_mode > 0)
+ harq_in_length = harq_in_length * 8 / 6;
+ harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
+ - op->ldpc_dec.n_filler);
+ /* Alignment on next 64B - Already enforced from HC output */
+ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
+ fcw->hcin_size0 = harq_in_length;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ } else {
+ fcw->hcin_size0 = 0;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ }
+
+ fcw->itmax = op->ldpc_dec.iter_max;
+ fcw->itstop = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+ fcw->synd_precoder = fcw->itstop;
+ /*
+ * These are all implicitly set
+ * fcw->synd_post = 0;
+ * fcw->so_en = 0;
+ * fcw->so_bypass_rm = 0;
+ * fcw->so_bypass_intlv = 0;
+ * fcw->dec_convllr = 0;
+ * fcw->hcout_convllr = 0;
+ * fcw->hcout_size1 = 0;
+ * fcw->so_it = 0;
+ * fcw->hcout_offset = 0;
+ * fcw->negstop_th = 0;
+ * fcw->negstop_it = 0;
+ * fcw->negstop_en = 0;
+ * fcw->gain_i = 1;
+ * fcw->gain_h = 1;
+ */
+ if (fcw->hcout_en > 0) {
+ parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
+ * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
+ k0_p = (fcw->k0 > parity_offset) ?
+ fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
+ ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
+ l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
+ harq_out_length = (uint16_t) fcw->hcin_size0;
+ harq_out_length = RTE_MAX(harq_out_length, l);
+ /* Cannot exceed the pruned Ncb circular buffer */
+ harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+ /* Alignment on next 64B */
+ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
+ fcw->hcout_size0 = harq_out_length;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ harq_layout[harq_index].offset = fcw->hcout_offset;
+ harq_layout[harq_index].size0 = fcw->hcout_size0;
+ } else {
+ fcw->hcout_size0 = 0;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ }
+}
+
/**
* Fills descriptor with data pointers of one block type.
*
@@ -2966,7 +3089,7 @@
struct acc100_fcw_ld *fcw;
uint32_t seg_total_left;
fcw = &desc->req.fcw_ld;
- acc100_fcw_ld_fill(op, fcw, harq_layout);
+ q->d->fcw_ld_fill(op, fcw, harq_layout);
/* Special handling when overusing mbuf */
if (fcw->rm_e < ACC100_MAX_E_MBUF)
@@ -3033,7 +3156,7 @@
desc = q->ring_addr + desc_idx;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
- acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
+ q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
input = op->ldpc_dec.input.data;
h_output_head = h_output = op->ldpc_dec.hard_output.data;
@@ -4145,9 +4268,19 @@
dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
- ((struct acc100_device *) dev->data->dev_private)->pf_device =
- !strcmp(drv->driver.name,
- RTE_STR(ACC100PF_DRIVER_NAME));
+ if ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) ||
+ (!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc100_fcw_ld_fill;
+ } else {
+ ((struct acc100_device *) dev->data->dev_private)->pf_device =
+ !strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME));
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc101_fcw_ld_fill;
+ }
+
((struct acc100_device *) dev->data->dev_private)->mmio_base =
pci_dev->mem_resource[0].addr;
@@ -4257,6 +4390,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);
RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);
+/* ACC101 PCI PF address map */
+static struct rte_pci_id pci_id_acc101_pf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+/* ACC101 PCI VF address map */
+static struct rte_pci_id pci_id_acc101_vf_map[] = {
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID)
+ },
+ {.device_id = 0},
+};
+
+
+static struct rte_pci_driver acc101_pci_pf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_pf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+static struct rte_pci_driver acc101_pci_vf_driver = {
+ .probe = acc100_pci_probe,
+ .remove = acc100_pci_remove,
+ .id_table = pci_id_acc101_vf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);
+RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);
+
/*
* Workaround implementation to fix the power on status of some 5GUL engines
* This requires DMA permission if ported outside DPDK
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index 8fea322..39d5f22 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -22,6 +22,9 @@
#define rte_bbdev_log_debug(fmt, ...)
#endif
+#define ACC100_VARIANT 0
+#define ACC101_VARIANT 1
+
/* ACC100 PF and VF driver names */
#define ACC100PF_DRIVER_NAME intel_acc100_pf
#define ACC100VF_DRIVER_NAME intel_acc100_vf
@@ -67,6 +70,8 @@
#define ACC100_HARQ_LAYOUT (64*1024*1024)
/* Assume offset for HARQ in memory */
#define ACC100_HARQ_OFFSET (32*1024)
+#define ACC100_HARQ_OFFSET_SHIFT 15
+#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
#define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
/* Number of Virtual Functions ACC100 supports */
@@ -574,6 +579,10 @@ struct __rte_cache_aligned acc100_queue {
struct acc100_device *d;
};
+typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,
+ struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout);
+
/* Private data structure for each ACC100 device */
struct acc100_device {
void *mmio_base; /**< Base address of MMIO registers (BAR0) */
@@ -605,6 +614,8 @@ struct acc100_device {
uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
bool pf_device; /**< True if this is a PF ACC100 device */
bool configured; /**< True if this ACC100 device is configured */
+ uint16_t device_variant; /**< Device variant */
+ acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation function */
};
/**
diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h
new file mode 100644
index 0000000..3e419cb
--- /dev/null
+++ b/drivers/baseband/acc100/rte_acc101_pmd.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+/* ACC101 PF and VF driver names */
+#define ACC101PF_DRIVER_NAME intel_acc101_pf
+#define ACC101VF_DRIVER_NAME intel_acc101_vf
+
+/* ACC101 PCI vendor & device IDs */
+#define RTE_ACC101_VENDOR_ID (0x8086)
+#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
+#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
+
+/* Define as 1 to use only a single FEC engine */
+#ifndef RTE_ACC101_SINGLE_FEC
+#define RTE_ACC101_SINGLE_FEC 0
+#endif
+
+/* Number of Virtual Functions ACC101 supports */
+#define ACC101_NUM_VFS 16
+#define ACC101_NUM_QGRPS 8
+#define ACC101_NUM_AQS 16
+/* All ACC101 Registers alignment are 32bits = 4B */
+#define ACC101_BYTES_IN_WORD 4
+
+#define ACC101_TMPL_PRI_0 0x03020100
+#define ACC101_TMPL_PRI_1 0x07060504
+#define ACC101_TMPL_PRI_2 0x0b0a0908
+#define ACC101_TMPL_PRI_3 0x0f0e0d0c
+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
+
+#define ACC101_NUM_TMPL 32
+/* Mapping of signals for the available engines */
+#define ACC101_SIG_UL_5G 0
+#define ACC101_SIG_UL_5G_LAST 8
+#define ACC101_SIG_DL_5G 13
+#define ACC101_SIG_DL_5G_LAST 15
+#define ACC101_SIG_UL_4G 16
+#define ACC101_SIG_UL_4G_LAST 19
+#define ACC101_SIG_DL_4G 27
+#define ACC101_SIG_DL_4G_LAST 31
+#define ACC101_NUM_ACCS 5
+#define ACC101_PF_VAL 2
+
+/* ACC101 Configuration */
+#define ACC101_CFG_DMA_ERROR 0x3D7
+#define ACC101_CFG_AXI_CACHE 0x11
+#define ACC101_CFG_QMGR_HI_P 0x0F0F
+#define ACC101_CFG_PCI_AXI 0xC003
+#define ACC101_CFG_PCI_BRIDGE 0x40006033
+#define ACC101_ENGINE_OFFSET 0x1000
+#define ACC101_LONG_WAIT 1000
+#define ACC101_GPEX_AXIMAP_NUM 17
+#define ACC101_CLOCK_GATING_EN 0x30000
+#define ACC101_DMA_INBOUND 0x104
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC101_HARQ_DDR (512 * 1)
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v5 4/5] baseband/acc100: modify validation code for ACC101
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (2 preceding siblings ...)
2022-05-24 0:08 ` [PATCH v5 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-24 0:08 ` Nicolas Chautru
2022-05-25 14:33 ` Maxime Coquelin
2022-05-24 0:08 ` [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
` (3 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-24 0:08 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
The validation requirement is different for the two
devices.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 47 ++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 41475b2..e3706e0 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1289,6 +1289,21 @@
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+static inline bool
+is_acc100(struct acc100_queue *q)
+{
+ return (q->d->device_variant == ACC100_VARIANT);
+}
+
+static inline bool
+validate_op_required(struct acc100_queue *q)
+{
+ return is_acc100(q);
+}
+#endif
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -2176,8 +2191,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo encoder parameters */
static inline int
-validate_enc_op(struct rte_bbdev_enc_op *op)
+validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
@@ -2314,8 +2331,10 @@ static inline uint32_t hq_index(uint32_t offset)
}
/* Validates LDPC encoder parameters */
static inline int
-validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
+validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
if (op->mempool == NULL) {
@@ -2367,8 +2386,10 @@ static inline uint32_t hq_index(uint32_t offset)
/* Validates LDPC decoder parameters */
static inline int
-validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
+validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
if (op->mempool == NULL) {
@@ -2423,7 +2444,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2477,7 +2498,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(ops[0]) == -1) {
+ if (validate_ldpc_enc_op(ops[0], q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2539,7 +2560,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(op) == -1) {
+ if (validate_ldpc_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2596,7 +2617,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2669,8 +2690,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo decoder parameters */
static inline int
-validate_dec_op(struct rte_bbdev_dec_op *op)
+validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
@@ -2816,7 +2839,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
@@ -3041,7 +3064,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3145,7 +3168,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3235,7 +3258,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (3 preceding siblings ...)
2022-05-24 0:08 ` [PATCH v5 4/5] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-24 0:08 ` Nicolas Chautru
2022-05-25 13:24 ` Maxime Coquelin
2022-05-26 0:49 ` [PATCH v6 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (2 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-24 0:08 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Adding companion function specific to ACC100 and it
can be called from bbdev-test when running from PF.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 22 ++-
drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++
drivers/baseband/acc100/version.map | 2 +-
4 files changed, 336 insertions(+), 7 deletions(-)
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 0fa119a..89b1e79 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -63,6 +63,8 @@
#define ACC100_QMGR_INVALID_IDX -1
#define ACC100_QMGR_RR 1
#define ACC100_QOS_GBR 0
+#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
+#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
#endif
#define OPS_CACHE_SIZE 256U
@@ -711,11 +713,12 @@ typedef int (test_case_function)(struct active_device *ad,
#endif
#ifdef RTE_BASEBAND_ACC100
if ((get_init_device() == true) &&
- (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
+ ((!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) ||
+ (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))) {
struct rte_acc100_conf conf;
unsigned int i;
- printf("Configure ACC100 FEC Driver %s with default values\n",
+ printf("Configure ACC100/ACC101 FEC Driver %s with default values\n",
info->drv.driver_name);
/* clear default configuration before initialization */
@@ -760,10 +763,17 @@ typedef int (test_case_function)(struct active_device *ad,
conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
/* setup PF with configuration information */
- ret = rte_acc100_configure(info->dev_name, &conf);
- TEST_ASSERT_SUCCESS(ret,
- "Failed to configure ACC100 PF for bbdev %s",
- info->dev_name);
+ if (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) {
+ ret = rte_acc100_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC100 PF for bbdev %s",
+ info->dev_name);
+ } else {
+ ret = rte_acc101_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC101 PF for bbdev %s",
+ info->dev_name);
+ }
}
#endif
/* Let's refresh this now this is configured */
diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
index d233e42..2e3c43f 100644
--- a/drivers/baseband/acc100/rte_acc100_cfg.h
+++ b/drivers/baseband/acc100/rte_acc100_cfg.h
@@ -106,6 +106,23 @@ struct rte_acc100_conf {
int
rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
+/**
+ * Configure a ACC101 device
+ *
+ * @param dev_name
+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ * It can also be retrieved for a bbdev device from the dev_name field in the
+ * rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ * Configuration to apply to ACC101 HW.
+ *
+ * @return
+ * Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf);
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index e3706e0..78c45d2 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -5005,3 +5005,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
+
+
+/* Initial configuration of a ACC101 device prior to running configure() */
+int
+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc101_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc100_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+
+ /* PCIe Bridge configuration */
+ acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
+ for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
+ acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
+
+ /* Prevent blocking AXI read on BRESP for AXI Write */
+ address = HwPfPcieGpexAxiPioControl;
+ value = ACC101_CFG_PCI_AXI;
+ acc100_reg_write(d, address, value);
+
+ /* Explicitly releasing AXI including a 2ms delay on ACC101 */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* Set the default 5GDL DMA configuration */
+ acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
+
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC101_CLOCK_GATING_EN;
+ acc100_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC101_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc100_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC101_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc100_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ address = HWPfDmaConfig1Reg;
+ int alen_r = 0xF;
+ int alen_w = 0x7;
+ value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
+ acc100_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc100_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_1;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_2;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_3;
+ acc100_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC101_CFG_QMGR_HI_P;
+ acc100_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_4G;
+ template_idx <= ACC101_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_5G;
+ template_idx <= ACC101_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg +
+ ACC101_ENGINE_OFFSET * template_idx;
+ status = (acc100_reg_read(d, address) >> 4) & 0xF;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc100_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc100_reg_write(d, address, 0);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ printf("Number of 5GUL engines %d\n", numEngines);
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_4G;
+ template_idx <= ACC101_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_5G;
+ template_idx <= ACC101_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ address = HWPfQmgrGrpFunction0;
+ value = 0;
+ for (qg_idx = 0; qg_idx < 8; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc]<<(qg_idx * 4);
+ }
+ acc100_reg_write(d, address, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC101_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc100_reg_write(d, address, value);
+ }
+ }
+
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC101_BYTES_IN_WORD + qg_idx
+ * ACC101_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc100_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC101_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
+ acc100_reg_write(d, address, value);
+ /* Explicitly releasing AXI after PF Mode and 2 ms */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc100_reg_write(d, address, value);
+
+ /* HARQ DDR Configuration */
+ unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfDmaVfDdrBaseRw + vf_idx
+ * 0x10;
+ value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
+ (ddrSizeInMb - 1);
+ acc100_reg_write(d, address, value);
+ }
+ usleep(ACC101_LONG_WAIT);
+
+ rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
+ return 0;
+}
diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map
index 40604c7..37b850f 100644
--- a/drivers/baseband/acc100/version.map
+++ b/drivers/baseband/acc100/version.map
@@ -6,5 +6,5 @@ EXPERIMENTAL {
global:
rte_acc100_configure;
-
+ rte_acc101_configure;
};
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF
2022-05-24 0:08 ` [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-05-25 13:24 ` Maxime Coquelin
2022-05-25 22:09 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Maxime Coquelin @ 2022-05-25 13:24 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
Hi Nicolas,
On 5/24/22 02:08, Nicolas Chautru wrote:
> Adding companion function specific to ACC100 and it
> can be called from bbdev-test when running from PF.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> app/test-bbdev/test_bbdev_perf.c | 22 ++-
> drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
> drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++
> drivers/baseband/acc100/version.map | 2 +-
> 4 files changed, 336 insertions(+), 7 deletions(-)
>
> diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
> index 0fa119a..89b1e79 100644
> --- a/app/test-bbdev/test_bbdev_perf.c
> +++ b/app/test-bbdev/test_bbdev_perf.c
> @@ -63,6 +63,8 @@
> #define ACC100_QMGR_INVALID_IDX -1
> #define ACC100_QMGR_RR 1
> #define ACC100_QOS_GBR 0
> +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
> +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
> #endif
>
> #define OPS_CACHE_SIZE 256U
> @@ -711,11 +713,12 @@ typedef int (test_case_function)(struct active_device *ad,
> #endif
> #ifdef RTE_BASEBAND_ACC100
> if ((get_init_device() == true) &&
> - (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
> + ((!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) ||
> + (!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))) {
> struct rte_acc100_conf conf;
> unsigned int i;
>
> - printf("Configure ACC100 FEC Driver %s with default values\n",
> + printf("Configure ACC100/ACC101 FEC Driver %s with default values\n",
> info->drv.driver_name);
>
> /* clear default configuration before initialization */
> @@ -760,10 +763,17 @@ typedef int (test_case_function)(struct active_device *ad,
> conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
>
> /* setup PF with configuration information */
> - ret = rte_acc100_configure(info->dev_name, &conf);
> - TEST_ASSERT_SUCCESS(ret,
> - "Failed to configure ACC100 PF for bbdev %s",
> - info->dev_name);
> + if (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) {
> + ret = rte_acc100_configure(info->dev_name, &conf);
> + TEST_ASSERT_SUCCESS(ret,
> + "Failed to configure ACC100 PF for bbdev %s",
> + info->dev_name);
> + } else {
> + ret = rte_acc101_configure(info->dev_name, &conf);
> + TEST_ASSERT_SUCCESS(ret,
> + "Failed to configure ACC101 PF for bbdev %s",
> + info->dev_name);
> + }
Having a single function for configuration, and a single driver would
avoid this.
You can keep the rte_acc100_configure and rte_acc100_configure functions
almost unmodified, just remove rte_ prefix and remove them from exported
API. Then introduce a rte_acc10x_configure which call proper
configuration function based on device ID.
> }
> #endif
> /* Let's refresh this now this is configured */
> diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
> index d233e42..2e3c43f 100644
> --- a/drivers/baseband/acc100/rte_acc100_cfg.h
> +++ b/drivers/baseband/acc100/rte_acc100_cfg.h
> @@ -106,6 +106,23 @@ struct rte_acc100_conf {
> int
> rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
>
> +/**
> + * Configure a ACC101 device
> + *
> + * @param dev_name
> + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
> + * It can also be retrieved for a bbdev device from the dev_name field in the
> + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> + * @param conf
> + * Configuration to apply to ACC101 HW.
> + *
> + * @return
> + * Zero on success, negative value on failure.
> + */
> +__rte_experimental
> +int
> +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf);
> +
> #ifdef __cplusplus
> }
> #endif
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index e3706e0..78c45d2 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -5005,3 +5005,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
> rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
> return 0;
> }
> +
> +
> +/* Initial configuration of a ACC101 device prior to running configure() */
> +int
> +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
> +{
> + rte_bbdev_log(INFO, "rte_acc101_configure");
> + uint32_t value, address, status;
> + int qg_idx, template_idx, vf_idx, acc, i;
> + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> +
> + /* Compile time checks */
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
> +
> + if (bbdev == NULL) {
> + rte_bbdev_log(ERR,
> + "Invalid dev_name (%s), or device is not yet initialised",
> + dev_name);
> + return -ENODEV;
> + }
> + struct acc100_device *d = bbdev->data->dev_private;
> +
> + /* Store configuration */
> + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
> +
> + /* PCIe Bridge configuration */
> + acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
> + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
> + acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
> +
> + /* Prevent blocking AXI read on BRESP for AXI Write */
> + address = HwPfPcieGpexAxiPioControl;
> + value = ACC101_CFG_PCI_AXI;
> + acc100_reg_write(d, address, value);
> +
> + /* Explicitly releasing AXI including a 2ms delay on ACC101 */
> + usleep(2000);
> + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> +
> + /* Set the default 5GDL DMA configuration */
> + acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
> +
> + /* Enable granular dynamic clock gating */
> + address = HWPfHiClkGateHystReg;
> + value = ACC101_CLOCK_GATING_EN;
> + acc100_reg_write(d, address, value);
> +
> + /* Set default descriptor signature */
> + address = HWPfDmaDescriptorSignatuture;
> + value = 0;
> + acc100_reg_write(d, address, value);
> +
> + /* Enable the Error Detection in DMA */
> + value = ACC101_CFG_DMA_ERROR;
> + address = HWPfDmaErrorDetectionEn;
> + acc100_reg_write(d, address, value);
> +
> + /* AXI Cache configuration */
> + value = ACC101_CFG_AXI_CACHE;
> + address = HWPfDmaAxcacheReg;
> + acc100_reg_write(d, address, value);
> +
> + /* Default DMA Configuration (Qmgr Enabled) */
> + address = HWPfDmaConfig0Reg;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + address = HWPfDmaQmanen;
> + value = 0;
> + acc100_reg_write(d, address, value);
> +
> + /* Default RLIM/ALEN configuration */
> + address = HWPfDmaConfig1Reg;
> + int alen_r = 0xF;
> + int alen_w = 0x7;
> + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
> + acc100_reg_write(d, address, value);
> +
> + /* Configure DMA Qmanager addresses */
> + address = HWPfDmaQmgrAddrReg;
> + value = HWPfQmgrEgressQueuesTemplate;
> + acc100_reg_write(d, address, value);
> +
> + /* ===== Qmgr Configuration ===== */
> + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
> + int totalQgs = conf->q_ul_4g.num_qgroups +
> + conf->q_ul_5g.num_qgroups +
> + conf->q_dl_4g.num_qgroups +
> + conf->q_dl_5g.num_qgroups;
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + address = HWPfQmgrDepthLog2Grp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = aqDepth(qg_idx, conf);
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrTholdGrp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> + acc100_reg_write(d, address, value);
> + }
> +
> + /* Template Priority in incremental order */
> + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_0;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_1;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_2;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_3;
> + acc100_reg_write(d, address, value);
> + }
> +
> + address = HWPfQmgrGrpPriority;
> + value = ACC101_CFG_QMGR_HI_P;
> + acc100_reg_write(d, address, value);
> +
> + /* Template Configuration */
> + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> + template_idx++) {
> + value = 0;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> + }
> + /* 4GUL */
> + int numQgs = conf->q_ul_4g.num_qgroups;
> + int numQqsAcc = 0;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_UL_4G;
> + template_idx <= ACC101_SIG_UL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> + }
> + /* 5GUL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_ul_5g.num_qgroups;
> + value = 0;
> + int numEngines = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_UL_5G;
> + template_idx <= ACC101_SIG_UL_5G_LAST;
> + template_idx++) {
> + /* Check engine power-on status */
> + address = HwPfFecUl5gIbDebugReg +
> + ACC101_ENGINE_OFFSET * template_idx;
> + status = (acc100_reg_read(d, address) >> 4) & 0xF;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + if (status == 1) {
> + acc100_reg_write(d, address, value);
> + numEngines++;
> + } else
> + acc100_reg_write(d, address, 0);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> + printf("Number of 5GUL engines %d\n", numEngines);
> + /* 4GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_4g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_DL_4G;
> + template_idx <= ACC101_SIG_DL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> + /* 5GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_5g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_DL_5G;
> + template_idx <= ACC101_SIG_DL_5G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> +
> + /* Queue Group Function mapping */
> + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> + address = HWPfQmgrGrpFunction0;
> + value = 0;
> + for (qg_idx = 0; qg_idx < 8; qg_idx++) {
> + acc = accFromQgid(qg_idx, conf);
> + value |= qman_func_id[acc]<<(qg_idx * 4);
> + }
> + acc100_reg_write(d, address, value);
> +
> + /* Configuration of the Arbitration QGroup depth to 1 */
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + address = HWPfQmgrArbQDepthGrp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + }
> +
> + /* Enabling AQueues through the Queue hierarchy*/
> + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
> + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
> + value = 0;
> + if (vf_idx < conf->num_vf_bundles &&
> + qg_idx < totalQgs)
> + value = (1 << aqNum(qg_idx, conf)) - 1;
> + address = HWPfQmgrAqEnableVf
> + + vf_idx * ACC101_BYTES_IN_WORD;
> + value += (qg_idx << 16);
> + acc100_reg_write(d, address, value);
> + }
> + }
> +
> + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
> + uint32_t aram_address = 0;
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> + address = HWPfQmgrVfBaseAddr + vf_idx
> + * ACC101_BYTES_IN_WORD + qg_idx
> + * ACC101_BYTES_IN_WORD * 64;
> + value = aram_address;
> + acc100_reg_write(d, address, value);
> + /* Offset ARAM Address for next memory bank
> + * - increment of 4B
> + */
> + aram_address += aqNum(qg_idx, conf) *
> + (1 << aqDepth(qg_idx, conf));
> + }
> + }
> +
> + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
> + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
> + aram_address, ACC101_WORDS_IN_ARAM_SIZE);
> + return -EINVAL;
> + }
> +
> + /* ==== HI Configuration ==== */
> +
> + /* No Info Ring/MSI by default */
> + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
> + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
> + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
> + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
> + /* Prevent Block on Transmit Error */
> + address = HWPfHiBlockTransmitOnErrorEn;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + /* Prevents to drop MSI */
> + address = HWPfHiMsiDropEnableReg;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + /* Set the PF Mode register */
> + address = HWPfHiPfMode;
> + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
> + acc100_reg_write(d, address, value);
> + /* Explicitly releasing AXI after PF Mode and 2 ms */
> + usleep(2000);
> + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> +
> + /* QoS overflow init */
> + value = 1;
> + address = HWPfQosmonAEvalOverflow0;
> + acc100_reg_write(d, address, value);
> + address = HWPfQosmonBEvalOverflow0;
> + acc100_reg_write(d, address, value);
> +
> + /* HARQ DDR Configuration */
> + unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
> + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> + address = HWPfDmaVfDdrBaseRw + vf_idx
> + * 0x10;
> + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
> + (ddrSizeInMb - 1);
> + acc100_reg_write(d, address, value);
> + }
> + usleep(ACC101_LONG_WAIT);
> +
> + rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
> + return 0;
> +}
> diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map
> index 40604c7..37b850f 100644
> --- a/drivers/baseband/acc100/version.map
> +++ b/drivers/baseband/acc100/version.map
> @@ -6,5 +6,5 @@ EXPERIMENTAL {
> global:
>
> rte_acc100_configure;
> -
> + rte_acc101_configure;
> };
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v5 4/5] baseband/acc100: modify validation code for ACC101
2022-05-24 0:08 ` [PATCH v5 4/5] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-25 14:33 ` Maxime Coquelin
2022-05-25 22:15 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Maxime Coquelin @ 2022-05-25 14:33 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
On 5/24/22 02:08, Nicolas Chautru wrote:
> The validation requirement is different for the two
> devices.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/rte_acc100_pmd.c | 47 ++++++++++++++++++++++++--------
> 1 file changed, 35 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index 41475b2..e3706e0 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -1289,6 +1289,21 @@
> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> }
>
> +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> +
> +static inline bool
> +is_acc100(struct acc100_queue *q)
> +{
> + return (q->d->device_variant == ACC100_VARIANT);
I keep insisting, but please rely on the PCI device ID, there is no need
to introduce a new field.
> +}
> +
> +static inline bool
> +validate_op_required(struct acc100_queue *q)
> +{
> + return is_acc100(q);
> +}
> +#endif
> +
> /* Fill in a frame control word for LDPC decoding. */
> static inline void
> acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> @@ -2176,8 +2191,10 @@ static inline uint32_t hq_index(uint32_t offset)
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validates turbo encoder parameters */
> static inline int
> -validate_enc_op(struct rte_bbdev_enc_op *op)
> +validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
> struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
> struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
> struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
> @@ -2314,8 +2331,10 @@ static inline uint32_t hq_index(uint32_t offset)
> }
> /* Validates LDPC encoder parameters */
> static inline int
> -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
> +validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
> struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
>
> if (op->mempool == NULL) {
> @@ -2367,8 +2386,10 @@ static inline uint32_t hq_index(uint32_t offset)
>
> /* Validates LDPC decoder parameters */
> static inline int
> -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
> +validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
> struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
>
> if (op->mempool == NULL) {
> @@ -2423,7 +2444,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_enc_op(op) == -1) {
> + if (validate_enc_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo encoder validation failed");
> return -EINVAL;
> }
> @@ -2477,7 +2498,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_enc_op(ops[0]) == -1) {
> + if (validate_ldpc_enc_op(ops[0], q) == -1) {
> rte_bbdev_log(ERR, "LDPC encoder validation failed");
> return -EINVAL;
> }
> @@ -2539,7 +2560,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_enc_op(op) == -1) {
> + if (validate_ldpc_enc_op(op, q) == -1) {
> rte_bbdev_log(ERR, "LDPC encoder validation failed");
> return -EINVAL;
> }
> @@ -2596,7 +2617,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_enc_op(op) == -1) {
> + if (validate_enc_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo encoder validation failed");
> return -EINVAL;
> }
> @@ -2669,8 +2690,10 @@ static inline uint32_t hq_index(uint32_t offset)
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validates turbo decoder parameters */
> static inline int
> -validate_dec_op(struct rte_bbdev_dec_op *op)
> +validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
> struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
> struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
> struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
> @@ -2816,7 +2839,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_dec_op(op) == -1) {
> + if (validate_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo decoder validation failed");
> return -EINVAL;
> }
> @@ -3041,7 +3064,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_dec_op(op) == -1) {
> + if (validate_ldpc_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "LDPC decoder validation failed");
> return -EINVAL;
> }
> @@ -3145,7 +3168,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_dec_op(op) == -1) {
> + if (validate_ldpc_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "LDPC decoder validation failed");
> return -EINVAL;
> }
> @@ -3235,7 +3258,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_dec_op(op) == -1) {
> + if (validate_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo decoder validation failed");
> return -EINVAL;
> }
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF
2022-05-25 13:24 ` Maxime Coquelin
@ 2022-05-25 22:09 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-25 22:09 UTC (permalink / raw)
To: Maxime Coquelin, dev, gakhil, trix
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Maxime,
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Wednesday, May 25, 2022 6:25 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from
> PF
>
> Hi Nicolas,
>
> On 5/24/22 02:08, Nicolas Chautru wrote:
> > Adding companion function specific to ACC100 and it can be called from
> > bbdev-test when running from PF.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > app/test-bbdev/test_bbdev_perf.c | 22 ++-
> > drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++
> > drivers/baseband/acc100/rte_acc100_pmd.c | 302
> +++++++++++++++++++++++++++++++
> > drivers/baseband/acc100/version.map | 2 +-
> > 4 files changed, 336 insertions(+), 7 deletions(-)
> >
> > diff --git a/app/test-bbdev/test_bbdev_perf.c
> > b/app/test-bbdev/test_bbdev_perf.c
> > index 0fa119a..89b1e79 100644
> > --- a/app/test-bbdev/test_bbdev_perf.c
> > +++ b/app/test-bbdev/test_bbdev_perf.c
> > @@ -63,6 +63,8 @@
> > #define ACC100_QMGR_INVALID_IDX -1
> > #define ACC100_QMGR_RR 1
> > #define ACC100_QOS_GBR 0
> > +#define ACC101PF_DRIVER_NAME ("intel_acc101_pf")
> > +#define ACC101VF_DRIVER_NAME ("intel_acc101_vf")
> > #endif
> >
> > #define OPS_CACHE_SIZE 256U
> > @@ -711,11 +713,12 @@ typedef int (test_case_function)(struct
> active_device *ad,
> > #endif
> > #ifdef RTE_BASEBAND_ACC100
> > if ((get_init_device() == true) &&
> > - (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)))
> {
> > + ((!strcmp(info->drv.driver_name,
> ACC100PF_DRIVER_NAME)) ||
> > + (!strcmp(info->drv.driver_name,
> ACC101PF_DRIVER_NAME)))) {
> > struct rte_acc100_conf conf;
> > unsigned int i;
> >
> > - printf("Configure ACC100 FEC Driver %s with default
> values\n",
> > + printf("Configure ACC100/ACC101 FEC Driver %s with default
> > +values\n",
> > info->drv.driver_name);
> >
> > /* clear default configuration before initialization */ @@ -
> 760,10
> > +763,17 @@ typedef int (test_case_function)(struct active_device *ad,
> > conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
> >
> > /* setup PF with configuration information */
> > - ret = rte_acc100_configure(info->dev_name, &conf);
> > - TEST_ASSERT_SUCCESS(ret,
> > - "Failed to configure ACC100 PF for bbdev
> %s",
> > - info->dev_name);
> > + if (!strcmp(info->drv.driver_name,
> ACC100PF_DRIVER_NAME)) {
> > + ret = rte_acc100_configure(info->dev_name, &conf);
> > + TEST_ASSERT_SUCCESS(ret,
> > + "Failed to configure ACC100 PF for
> bbdev %s",
> > + info->dev_name);
> > + } else {
> > + ret = rte_acc101_configure(info->dev_name, &conf);
> > + TEST_ASSERT_SUCCESS(ret,
> > + "Failed to configure ACC101 PF for
> bbdev %s",
> > + info->dev_name);
> > + }
>
> Having a single function for configuration, and a single driver would avoid
> this.
>
> You can keep the rte_acc100_configure and rte_acc100_configure functions
> almost unmodified, just remove rte_ prefix and remove them from exported
> API. Then introduce a rte_acc10x_configure which call proper configuration
> function based on device ID.
>
Ok fair enough. Thanks!
> > }
> > #endif
> > /* Let's refresh this now this is configured */ diff --git
> > a/drivers/baseband/acc100/rte_acc100_cfg.h
> > b/drivers/baseband/acc100/rte_acc100_cfg.h
> > index d233e42..2e3c43f 100644
> > --- a/drivers/baseband/acc100/rte_acc100_cfg.h
> > +++ b/drivers/baseband/acc100/rte_acc100_cfg.h
> > @@ -106,6 +106,23 @@ struct rte_acc100_conf {
> > int
> > rte_acc100_configure(const char *dev_name, struct rte_acc100_conf
> > *conf);
> >
> > +/**
> > + * Configure a ACC101 device
> > + *
> > + * @param dev_name
> > + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
> > + * It can also be retrieved for a bbdev device from the dev_name field in
> the
> > + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> > + * @param conf
> > + * Configuration to apply to ACC101 HW.
> > + *
> > + * @return
> > + * Zero on success, negative value on failure.
> > + */
> > +__rte_experimental
> > +int
> > +rte_acc101_configure(const char *dev_name, struct rte_acc100_conf
> > +*conf);
> > +
> > #ifdef __cplusplus
> > }
> > #endif
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index e3706e0..78c45d2 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -5005,3 +5005,305 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > rte_bbdev_log_debug("PF Tip configuration complete for %s",
> dev_name);
> > return 0;
> > }
> > +
> > +
> > +/* Initial configuration of a ACC101 device prior to running
> > +configure() */ int rte_acc101_configure(const char *dev_name, struct
> > +rte_acc100_conf *conf) {
> > + rte_bbdev_log(INFO, "rte_acc101_configure");
> > + uint32_t value, address, status;
> > + int qg_idx, template_idx, vf_idx, acc, i;
> > + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> > +
> > + /* Compile time checks */
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
> > +
> > + if (bbdev == NULL) {
> > + rte_bbdev_log(ERR,
> > + "Invalid dev_name (%s), or device is not yet initialised",
> > + dev_name);
> > + return -ENODEV;
> > + }
> > + struct acc100_device *d = bbdev->data->dev_private;
> > +
> > + /* Store configuration */
> > + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
> > +
> > + /* PCIe Bridge configuration */
> > + acc100_reg_write(d, HwPfPcieGpexBridgeControl,
> ACC101_CFG_PCI_BRIDGE);
> > + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
> > + acc100_reg_write(d,
> HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i
> > +* 16, 0);
> > +
> > + /* Prevent blocking AXI read on BRESP for AXI Write */
> > + address = HwPfPcieGpexAxiPioControl;
> > + value = ACC101_CFG_PCI_AXI;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Explicitly releasing AXI including a 2ms delay on ACC101 */
> > + usleep(2000);
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* Set the default 5GDL DMA configuration */
> > + acc100_reg_write(d, HWPfDmaInboundDrainDataSize,
> > +ACC101_DMA_INBOUND);
> > +
> > + /* Enable granular dynamic clock gating */
> > + address = HWPfHiClkGateHystReg;
> > + value = ACC101_CLOCK_GATING_EN;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Set default descriptor signature */
> > + address = HWPfDmaDescriptorSignatuture;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Enable the Error Detection in DMA */
> > + value = ACC101_CFG_DMA_ERROR;
> > + address = HWPfDmaErrorDetectionEn;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* AXI Cache configuration */
> > + value = ACC101_CFG_AXI_CACHE;
> > + address = HWPfDmaAxcacheReg;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default DMA Configuration (Qmgr Enabled) */
> > + address = HWPfDmaConfig0Reg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfDmaQmanen;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default RLIM/ALEN configuration */
> > + address = HWPfDmaConfig1Reg;
> > + int alen_r = 0xF;
> > + int alen_w = 0x7;
> > + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configure DMA Qmanager addresses */
> > + address = HWPfDmaQmgrAddrReg;
> > + value = HWPfQmgrEgressQueuesTemplate;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* ===== Qmgr Configuration ===== */
> > + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2
> for UL */
> > + int totalQgs = conf->q_ul_4g.num_qgroups +
> > + conf->q_ul_5g.num_qgroups +
> > + conf->q_dl_4g.num_qgroups +
> > + conf->q_dl_5g.num_qgroups;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrDepthLog2Grp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = aqDepth(qg_idx, conf);
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrTholdGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Template Priority in incremental order */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg0Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg1Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_1;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg2indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_2;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg3Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_3;
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + address = HWPfQmgrGrpPriority;
> > + value = ACC101_CFG_QMGR_HI_P;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Template Configuration */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + value = 0;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 4GUL */
> > + int numQgs = conf->q_ul_4g.num_qgroups;
> > + int numQqsAcc = 0;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_4G;
> > + template_idx <= ACC101_SIG_UL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 5GUL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_ul_5g.num_qgroups;
> > + value = 0;
> > + int numEngines = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_5G;
> > + template_idx <= ACC101_SIG_UL_5G_LAST;
> > + template_idx++) {
> > + /* Check engine power-on status */
> > + address = HwPfFecUl5gIbDebugReg +
> > + ACC101_ENGINE_OFFSET * template_idx;
> > + status = (acc100_reg_read(d, address) >> 4) & 0xF;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + if (status == 1) {
> > + acc100_reg_write(d, address, value);
> > + numEngines++;
> > + } else
> > + acc100_reg_write(d, address, 0);
> > +#if RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > + printf("Number of 5GUL engines %d\n", numEngines);
> > + /* 4GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_4g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_4G;
> > + template_idx <= ACC101_SIG_DL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value); #if
> RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > + /* 5GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_5g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_5G;
> > + template_idx <= ACC101_SIG_DL_5G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value); #if
> RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > +
> > + /* Queue Group Function mapping */
> > + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> > + address = HWPfQmgrGrpFunction0;
> > + value = 0;
> > + for (qg_idx = 0; qg_idx < 8; qg_idx++) {
> > + acc = accFromQgid(qg_idx, conf);
> > + value |= qman_func_id[acc]<<(qg_idx * 4);
> > + }
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configuration of the Arbitration QGroup depth to 1 */
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrArbQDepthGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Enabling AQueues through the Queue hierarchy*/
> > + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
> > + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
> > + value = 0;
> > + if (vf_idx < conf->num_vf_bundles &&
> > + qg_idx < totalQgs)
> > + value = (1 << aqNum(qg_idx, conf)) - 1;
> > + address = HWPfQmgrAqEnableVf
> > + + vf_idx * ACC101_BYTES_IN_WORD;
> > + value += (qg_idx << 16);
> > + acc100_reg_write(d, address, value);
> > + }
> > + }
> > +
> > + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
> > + uint32_t aram_address = 0;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfQmgrVfBaseAddr + vf_idx
> > + * ACC101_BYTES_IN_WORD + qg_idx
> > + * ACC101_BYTES_IN_WORD * 64;
> > + value = aram_address;
> > + acc100_reg_write(d, address, value);
> > + /* Offset ARAM Address for next memory bank
> > + * - increment of 4B
> > + */
> > + aram_address += aqNum(qg_idx, conf) *
> > + (1 << aqDepth(qg_idx, conf));
> > + }
> > + }
> > +
> > + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
> > + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d
> %d\n",
> > + aram_address,
> ACC101_WORDS_IN_ARAM_SIZE);
> > + return -EINVAL;
> > + }
> > +
> > + /* ==== HI Configuration ==== */
> > +
> > + /* No Info Ring/MSI by default */
> > + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
> > + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
> > + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
> > + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
> > + /* Prevent Block on Transmit Error */
> > + address = HWPfHiBlockTransmitOnErrorEn;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Prevents to drop MSI */
> > + address = HWPfHiMsiDropEnableReg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Set the PF Mode register */
> > + address = HWPfHiPfMode;
> > + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
> > + acc100_reg_write(d, address, value);
> > + /* Explicitly releasing AXI after PF Mode and 2 ms */
> > + usleep(2000);
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* QoS overflow init */
> > + value = 1;
> > + address = HWPfQosmonAEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQosmonBEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* HARQ DDR Configuration */
> > + unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfDmaVfDdrBaseRw + vf_idx
> > + * 0x10;
> > + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
> > + (ddrSizeInMb - 1);
> > + acc100_reg_write(d, address, value);
> > + }
> > + usleep(ACC101_LONG_WAIT);
> > +
> > + rte_bbdev_log_debug("PF TIP configuration complete for %s",
> dev_name);
> > + return 0;
> > +}
> > diff --git a/drivers/baseband/acc100/version.map
> > b/drivers/baseband/acc100/version.map
> > index 40604c7..37b850f 100644
> > --- a/drivers/baseband/acc100/version.map
> > +++ b/drivers/baseband/acc100/version.map
> > @@ -6,5 +6,5 @@ EXPERIMENTAL {
> > global:
> >
> > rte_acc100_configure;
> > -
> > + rte_acc101_configure;
> > };
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v5 4/5] baseband/acc100: modify validation code for ACC101
2022-05-25 14:33 ` Maxime Coquelin
@ 2022-05-25 22:15 ` Chautru, Nicolas
2022-05-31 7:59 ` Maxime Coquelin
0 siblings, 1 reply; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-25 22:15 UTC (permalink / raw)
To: Maxime Coquelin, dev, gakhil, trix
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Wednesday, May 25, 2022 7:33 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v5 4/5] baseband/acc100: modify validation code for
> ACC101
>
>
>
> On 5/24/22 02:08, Nicolas Chautru wrote:
> > The validation requirement is different for the two devices.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > drivers/baseband/acc100/rte_acc100_pmd.c | 47
> ++++++++++++++++++++++++--------
> > 1 file changed, 35 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index 41475b2..e3706e0 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -1289,6 +1289,21 @@
> > RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> > }
> >
> > +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> > +
> > +static inline bool
> > +is_acc100(struct acc100_queue *q)
> > +{
> > + return (q->d->device_variant == ACC100_VARIANT);
>
> I keep insisting, but please rely on the PCI device ID, there is no need to
> introduce a new field.
Thanks. I have a couple of concerns changing this:
1) the device id is not accessible from the structures currently passed by the functions which would rely on this. Ie. device_id is accessible from rte_bbdev/rte_device but not from acc100_device or acc100_queue. Would be convoluted to have to carry forward this structure when needed instead of using directly acc100_device structure.
2) These call would be done as part of the workload operation where performance matters, best to keep the check as trivial as possible within the PMD.
Will aim for new patch in next few days based on the other refactory suggestions and unified driver.
Thanks
Nic
>
> > +}
> > +
> > +static inline bool
> > +validate_op_required(struct acc100_queue *q) {
> > + return is_acc100(q);
> > +}
> > +#endif
> > +
> > /* Fill in a frame control word for LDPC decoding. */
> > static inline void
> > acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld
> > *fcw, @@ -2176,8 +2191,10 @@ static inline uint32_t hq_index(uint32_t
> offset)
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validates turbo encoder parameters */
> > static inline int
> > -validate_enc_op(struct rte_bbdev_enc_op *op)
> > +validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
> > struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
> > struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
> > struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL; @@ -2314,8
> > +2331,10 @@ static inline uint32_t hq_index(uint32_t offset)
> > }
> > /* Validates LDPC encoder parameters */
> > static inline int
> > -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
> > +validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue
> > +*q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
> > struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
> >
> > if (op->mempool == NULL) {
> > @@ -2367,8 +2386,10 @@ static inline uint32_t hq_index(uint32_t
> > offset)
> >
> > /* Validates LDPC decoder parameters */
> > static inline int
> > -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
> > +validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue
> > +*q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
> > struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
> >
> > if (op->mempool == NULL) {
> > @@ -2423,7 +2444,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_enc_op(op) == -1) {
> > + if (validate_enc_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2477,7 +2498,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_enc_op(ops[0]) == -1) {
> > + if (validate_ldpc_enc_op(ops[0], q) == -1) {
> > rte_bbdev_log(ERR, "LDPC encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2539,7 +2560,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_enc_op(op) == -1) {
> > + if (validate_ldpc_enc_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "LDPC encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2596,7 +2617,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_enc_op(op) == -1) {
> > + if (validate_enc_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2669,8 +2690,10 @@ static inline uint32_t hq_index(uint32_t offset)
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validates turbo decoder parameters */
> > static inline int
> > -validate_dec_op(struct rte_bbdev_dec_op *op)
> > +validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
> > struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
> > struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
> > struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL; @@ -2816,7
> > +2839,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_dec_op(op) == -1) {
> > + if (validate_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo decoder validation failed");
> > return -EINVAL;
> > }
> > @@ -3041,7 +3064,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_dec_op(op) == -1) {
> > + if (validate_ldpc_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "LDPC decoder validation failed");
> > return -EINVAL;
> > }
> > @@ -3145,7 +3168,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_dec_op(op) == -1) {
> > + if (validate_ldpc_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "LDPC decoder validation failed");
> > return -EINVAL;
> > }
> > @@ -3235,7 +3258,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_dec_op(op) == -1) {
> > + if (validate_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo decoder validation failed");
> > return -EINVAL;
> > }
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v6 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (4 preceding siblings ...)
2022-05-24 0:08 ` [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-05-26 0:49 ` Nicolas Chautru
2022-05-26 0:55 ` Nicolas Chautru
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
7 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-26 0:49 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
v6: use formally an unified driver for AC100 and AC101. Exposing single unified function for the PF device configuration used by bbdev-test.
v5: minor fix to doc and intermediate commit caught in CI
v4: incremental updates based on reviews Changed order of patchset to include two ACC100 specific commits first: updating formally the companion configure function from PF and the protection adjustment.
Then next 3 commits for the actual changes specific to ACC101: the device specific function for FCW 5GUL generation used as a local function, combined documentations into a single .rst common to both devices, updated comments, removed unused #defines.
v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section calling the configure companion function for ACC100/101, taking the Pmon commit out which is not directly required.
v2: Based on good feedback from Thomas and David, now implementing the ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to have different behaviour based on variant.
This prevents code duplication and only rely on different functions and behaviour when hardware requires or support differences.
Note that these are pending changes for ACC100 which would be specific to that device and not ACC101 but these can be managed based on the new implementation, ie. is_acc100() etc... (such incremental changes for ACC100 trending 22.11 but confirming this is future proof).
The serie also includes commits which were meant for ACC101 but are also valuable for ACC100.
v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
This is a derivative from previous Mount Bryce ACC100 which includes silicon improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
Nicolas Chautru (5):
baseband/acc100: update companion PF configure function
baseband/acc100: add protection for some negative scenario
baseband/acc100: introduce PMD for ACC101
baseband/acc100: modify validation code for ACC101
baseband/acc100: configuration of ACC101 from PF
MAINTAINERS | 1 +
app/test-bbdev/test_bbdev_perf.c | 6 +-
doc/guides/bbdevs/acc100.rst | 37 +-
doc/guides/bbdevs/features/acc101.ini | 13 +
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/acc100_pf_enum.h | 18 +
drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
drivers/baseband/acc100/rte_acc100_pmd.c | 679 ++++++++++++++++++++++++++++---
drivers/baseband/acc100/rte_acc100_pmd.h | 26 ++
drivers/baseband/acc100/rte_acc101_pmd.h | 55 +++
drivers/baseband/acc100/version.map | 3 +-
11 files changed, 773 insertions(+), 72 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v6 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (5 preceding siblings ...)
2022-05-26 0:49 ` [PATCH v6 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
@ 2022-05-26 0:55 ` Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
` (4 more replies)
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
7 siblings, 5 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-26 0:55 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
v6: use formally an unified driver for AC100 and AC101. Exposing single unified function for the PF device configuration used by bbdev-test.
v5: minor fix to doc and intermediate commit caught in CI
v4: incremental updates based on reviews Changed order of patchset to include two ACC100 specific commits first: updating formally the companion configure function from PF and the protection adjustment.
Then next 3 commits for the actual changes specific to ACC101: the device specific function for FCW 5GUL generation used as a local function, combined documentations into a single .rst common to both devices, updated comments, removed unused #defines.
v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section calling the configure companion function for ACC100/101, taking the Pmon commit out which is not directly required.
v2: Based on good feedback from Thomas and David, now implementing the ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to have different behaviour based on variant.
This prevents code duplication and only rely on different functions and behaviour when hardware requires or support differences.
Note that these are pending changes for ACC100 which would be specific to that device and not ACC101 but these can be managed based on the new implementation, ie. is_acc100() etc... (such incremental changes for ACC100 trending 22.11 but confirming this is future proof).
The serie also includes commits which were meant for ACC101 but are also valuable for ACC100.
v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
This is a derivative from previous Mount Bryce ACC100 which includes silicon improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
Nicolas Chautru (5):
baseband/acc100: update companion PF configure function
baseband/acc100: add protection for some negative scenario
baseband/acc100: introduce PMD for ACC101
baseband/acc100: modify validation code for ACC101
baseband/acc100: configuration of ACC101 from PF
MAINTAINERS | 1 +
app/test-bbdev/test_bbdev_perf.c | 6 +-
doc/guides/bbdevs/acc100.rst | 37 +-
doc/guides/bbdevs/features/acc101.ini | 13 +
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/acc100_pf_enum.h | 18 +
drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
drivers/baseband/acc100/rte_acc100_pmd.c | 679 ++++++++++++++++++++++++++++---
drivers/baseband/acc100/rte_acc100_pmd.h | 26 ++
drivers/baseband/acc100/rte_acc101_pmd.h | 55 +++
drivers/baseband/acc100/version.map | 3 +-
11 files changed, 773 insertions(+), 72 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v6 1/5] baseband/acc100: update companion PF configure function
2022-05-26 0:55 ` Nicolas Chautru
@ 2022-05-26 0:55 ` Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
` (3 subsequent siblings)
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-26 0:55 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Update of the device configuration function from PF used for bbdev-test
to latest sequence for ACC199 PRQ device and matching version in
pf_bb_config 22.03.
Fixes: b17d70922d5d ("baseband/acc100: add configure function")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++
drivers/baseband/acc100/rte_acc100_pmd.c | 150 ++++++++++++++++++++++++-------
drivers/baseband/acc100/rte_acc100_pmd.h | 15 ++++
3 files changed, 151 insertions(+), 32 deletions(-)
diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h
index a1ee416..2fba667 100644
--- a/drivers/baseband/acc100/acc100_pf_enum.h
+++ b/drivers/baseband/acc100/acc100_pf_enum.h
@@ -238,6 +238,24 @@ enum {
HWPfPermonBTotalLatLowBusMon = 0x00BAC504,
HWPfPermonBTotalLatUpperBusMon = 0x00BAC508,
HWPfPermonBTotalReqCntBusMon = 0x00BAC50C,
+ HwPfFabI2MArbCntrlReg = 0x00BB0000,
+ HWPfFabricMode = 0x00BB1000,
+ HwPfFabI2MGrp0DebugReg = 0x00BBF000,
+ HwPfFabI2MGrp1DebugReg = 0x00BBF004,
+ HwPfFabI2MGrp2DebugReg = 0x00BBF008,
+ HwPfFabI2MGrp3DebugReg = 0x00BBF00C,
+ HwPfFabI2MBuf0DebugReg = 0x00BBF010,
+ HwPfFabI2MBuf1DebugReg = 0x00BBF014,
+ HwPfFabI2MBuf2DebugReg = 0x00BBF018,
+ HwPfFabI2MBuf3DebugReg = 0x00BBF01C,
+ HwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020,
+ HwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024,
+ HwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028,
+ HwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C,
+ HwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030,
+ HwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034,
+ HwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038,
+ HwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C,
HWPfFecUl5gCntrlReg = 0x00BC0000,
HWPfFecUl5gI2MThreshReg = 0x00BC0004,
HWPfFecUl5gVersionReg = 0x00BC0100,
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index de7e4bc..9135c0e 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -4411,7 +4411,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
{
rte_bbdev_log(INFO, "rte_acc100_configure");
uint32_t value, address, status;
- int qg_idx, template_idx, vf_idx, acc, i;
+ int qg_idx, template_idx, vf_idx, acc, i, j;
struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
/* Compile time checks */
@@ -4431,6 +4431,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* Store configuration */
rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+ value = acc100_reg_read(d, HwPfPcieGpexBridgeControl);
+ bool firstCfg = (value != ACC100_CFG_PCI_BRIDGE);
+
/* PCIe Bridge configuration */
acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE);
for (i = 1; i < ACC100_GPEX_AXIMAP_NUM; i++)
@@ -4451,20 +4454,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = 1;
acc100_reg_write(d, address, value);
- /* DDR Configuration */
- address = HWPfDdrBcTim6;
- value = acc100_reg_read(d, address);
- value &= 0xFFFFFFFB; /* Bit 2 */
-#ifdef ACC100_DDR_ECC_ENABLE
- value |= 0x4;
-#endif
- acc100_reg_write(d, address, value);
- address = HWPfDdrPhyDqsCountNum;
-#ifdef ACC100_DDR_ECC_ENABLE
- value = 9;
-#else
- value = 8;
-#endif
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC100_CLOCK_GATING_EN;
acc100_reg_write(d, address, value);
/* Set default descriptor signature */
@@ -4482,6 +4474,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfDmaAxcacheReg;
acc100_reg_write(d, address, value);
+ /* Adjust PCIe Lane adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ for (j = 0; j < ACC100_LANES_PER_QUAD; j++)
+ acc100_reg_write(d, HwPfPcieLnAdaptctrl + i * ACC100_PCIE_QUAD_OFFSET
+ + j * ACC100_PCIE_LANE_OFFSET, ACC100_ADAPT);
+
+ /* Enable PCIe live adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ acc100_reg_write(d, HwPfPciePcsEqControl +
+ i * ACC100_PCIE_QUAD_OFFSET, ACC100_PCS_EQ);
+
/* Default DMA Configuration (Qmgr Enabled) */
address = HWPfDmaConfig0Reg;
value = 0;
@@ -4500,6 +4503,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = HWPfQmgrEgressQueuesTemplate;
acc100_reg_write(d, address, value);
+ /* Default Fabric Mode */
+ address = HWPfFabricMode;
+ value = ACC100_FABRIC_MODE;
+ acc100_reg_write(d, address, value);
+
/* ===== Qmgr Configuration ===== */
/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
int totalQgs = conf->q_ul_4g.num_qgroups +
@@ -4518,22 +4526,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Template Priority in incremental order */
- for (template_idx = 0; template_idx < ACC100_NUM_TMPL;
- template_idx++) {
- address = HWPfQmgrGrpTmplateReg0Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ for (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_0;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg1Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_1;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg2indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_2;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg3Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_3;
acc100_reg_write(d, address, value);
}
@@ -4623,7 +4626,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Queue Group Function mapping */
- int qman_func_id[5] = {0, 2, 1, 3, 4};
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
address = HWPfQmgrGrpFunction0;
value = 0;
for (qg_idx = 0; qg_idx < 8; qg_idx++) {
@@ -4654,7 +4657,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
}
- /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
uint32_t aram_address = 0;
for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
@@ -4679,6 +4682,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* ==== HI Configuration ==== */
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
/* Prevent Block on Transmit Error */
address = HWPfHiBlockTransmitOnErrorEn;
value = 0;
@@ -4691,10 +4699,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfHiPfMode;
value = (conf->pf_mode_en) ? ACC100_PF_VAL : 0;
acc100_reg_write(d, address, value);
- /* Enable Error Detection in HW */
- address = HWPfDmaErrorDetectionEn;
- value = 0x3D7;
- acc100_reg_write(d, address, value);
/* QoS overflow init */
value = 1;
@@ -4704,7 +4708,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
acc100_reg_write(d, address, value);
/* HARQ DDR Configuration */
- unsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */
+ unsigned int ddrSizeInMb = ACC100_HARQ_DDR;
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
address = HWPfDmaVfDdrBaseRw + vf_idx
* 0x10;
@@ -4718,6 +4722,88 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
if (numEngines < (ACC100_SIG_UL_5G_LAST + 1))
poweron_cleanup(bbdev, d, conf);
+ uint32_t version = 0;
+ for (i = 0; i < 4; i++)
+ version += acc100_reg_read(d,
+ HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
+ if (version != ACC100_PRQ_DDR_VER) {
+ printf("* Note: Not on DDR PRQ version %8x != %08x\n",
+ version, ACC100_PRQ_DDR_VER);
+ } else if (firstCfg) {
+ /* ---- DDR configuration at boot up --- */
+ /* Read Clear Ddr training status */
+ acc100_reg_read(d, HWPfChaDdrStDoneStatus);
+ /* Reset PHY/IDTM/UMMC */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 2);
+ usleep(ACC100_MS_IN_US);
+ /* Reset WB and APB resets */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 3);
+ /* Configure PHY-IDTM */
+ acc100_reg_write(d, HWPfDdrPhyIdletimeout, 0x3e8);
+ /* IDTM timing registers */
+ acc100_reg_write(d, HWPfDdrPhyRdLatency, 0x13);
+ acc100_reg_write(d, HWPfDdrPhyRdLatencyDbi, 0x15);
+ acc100_reg_write(d, HWPfDdrPhyWrLatency, 0x10011);
+ /* Configure SDRAM MRS registers */
+ acc100_reg_write(d, HWPfDdrPhyMr01Dimm, 0x3030b70);
+ acc100_reg_write(d, HWPfDdrPhyMr01DimmDbi, 0x3030b50);
+ acc100_reg_write(d, HWPfDdrPhyMr23Dimm, 0x30);
+ acc100_reg_write(d, HWPfDdrPhyMr67Dimm, 0xc00);
+ acc100_reg_write(d, HWPfDdrPhyMr45Dimm, 0x4000000);
+ /* Configure active lanes */
+ acc100_reg_write(d, HWPfDdrPhyDqsCountMax, 0x9);
+ acc100_reg_write(d, HWPfDdrPhyDqsCountNum, 0x9);
+ /* Configure WR/RD leveling timing registers */
+ acc100_reg_write(d, HWPfDdrPhyWrlvlWwRdlvlRr, 0x101212);
+ /* Configure what trainings to execute */
+ acc100_reg_write(d, HWPfDdrPhyTrngType, 0x2d3c);
+ /* Releasing PHY reset */
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 3);
+ /* Configure Memory Controller registers */
+ acc100_reg_write(d, HWPfDdrMemInitPhyTrng0, 0x3);
+ acc100_reg_write(d, HWPfDdrBcDram, 0x3c232003);
+ acc100_reg_write(d, HWPfDdrBcAddrMap, 0x31);
+ /* Configure UMMC BC timing registers */
+ acc100_reg_write(d, HWPfDdrBcRef, 0xa22);
+ acc100_reg_write(d, HWPfDdrBcTim0, 0x4050501);
+ acc100_reg_write(d, HWPfDdrBcTim1, 0xf0b0476);
+ acc100_reg_write(d, HWPfDdrBcTim2, 0x103);
+ acc100_reg_write(d, HWPfDdrBcTim3, 0x144050a1);
+ acc100_reg_write(d, HWPfDdrBcTim4, 0x23300);
+ acc100_reg_write(d, HWPfDdrBcTim5, 0x4230276);
+ acc100_reg_write(d, HWPfDdrBcTim6, 0x857914);
+ acc100_reg_write(d, HWPfDdrBcTim7, 0x79100232);
+ acc100_reg_write(d, HWPfDdrBcTim8, 0x100007ce);
+ acc100_reg_write(d, HWPfDdrBcTim9, 0x50020);
+ acc100_reg_write(d, HWPfDdrBcTim10, 0x40ee);
+ /* Configure UMMC DFI timing registers */
+ acc100_reg_write(d, HWPfDdrDfiInit, 0x5000);
+ acc100_reg_write(d, HWPfDdrDfiTim0, 0x15030006);
+ acc100_reg_write(d, HWPfDdrDfiTim1, 0x11305);
+ acc100_reg_write(d, HWPfDdrDfiPhyUpdEn, 0x1);
+ acc100_reg_write(d, HWPfDdrUmmcIntEn, 0x1f);
+ /* Release IDTM CPU out of reset */
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 0x2);
+ /* Wait PHY-IDTM to finish static training */
+ for (i = 0; i < ACC100_DDR_TRAINING_MAX; i++) {
+ usleep(ACC100_MS_IN_US);
+ value = acc100_reg_read(d,
+ HWPfChaDdrStDoneStatus);
+ if (value & 1)
+ break;
+ }
+ printf("DDR Training completed in %d ms", i);
+ /* Enable Memory Controller */
+ acc100_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
+ /* Release AXI interface reset */
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 3);
+ }
+
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index cbcece2..8fea322 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -153,6 +153,12 @@
#define ACC100_CFG_QMGR_HI_P 0x0F0F
#define ACC100_CFG_PCI_AXI 0xC003
#define ACC100_CFG_PCI_BRIDGE 0x40006033
+#define ACC100_QUAD_NUMS 4
+#define ACC100_LANES_PER_QUAD 4
+#define ACC100_PCIE_LANE_OFFSET 0x200
+#define ACC100_PCIE_QUAD_OFFSET 0x2000
+#define ACC100_PCS_EQ 0x6007
+#define ACC100_ADAPT 0x8400
#define ACC100_ENGINE_OFFSET 0x1000
#define ACC100_RESET_HI 0x20100
#define ACC100_RESET_LO 0x20000
@@ -160,6 +166,15 @@
#define ACC100_ENGINES_MAX 9
#define ACC100_LONG_WAIT 1000
#define ACC100_GPEX_AXIMAP_NUM 17
+#define ACC100_CLOCK_GATING_EN 0x30000
+#define ACC100_FABRIC_MODE 0xB
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC100_HARQ_DDR (512 * 1)
+#define ACC100_PRQ_DDR_VER 0x10092020
+#define ACC100_MS_IN_US (1000)
+#define ACC100_DDR_TRAINING_MAX (5000)
/* ACC100 DMA Descriptor triplet */
struct acc100_dma_triplet {
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v6 2/5] baseband/acc100: add protection for some negative scenario
2022-05-26 0:55 ` Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
@ 2022-05-26 0:55 ` Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
` (2 subsequent siblings)
4 siblings, 0 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-26 0:55 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Catch exception in PMD in case of invalid input parameter.
Fixes: 5ad5060f8f7a ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 9135c0e..3fdf17d 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1236,6 +1236,8 @@
return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
}
/* LBRM case - includes a division by N */
+ if (unlikely(z_c == 0))
+ return 0;
if (rv_index == 1)
return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
/ n) * z_c;
@@ -1764,6 +1766,10 @@
/* Soft output */
if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
+ if (op->turbo_dec.soft_output.data == 0) {
+ rte_bbdev_log(ERR, "Soft output is not defined");
+ return -1;
+ }
if (check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_EQUALIZER))
*s_out_length = e;
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101
2022-05-26 0:55 ` Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-05-26 0:55 ` Nicolas Chautru
2022-05-30 7:40 ` [EXT] " Akhil Goyal
2022-05-26 0:55 ` [PATCH v6 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
4 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-26 0:55 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Support for ACC101 as a derivative of ACC100.
Integrated in unified driver and reusing existing code when possible.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
MAINTAINERS | 1 +
doc/guides/bbdevs/acc100.rst | 37 +++++---
doc/guides/bbdevs/features/acc101.ini | 13 +++
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/rte_acc100_pmd.c | 153 +++++++++++++++++++++++++++++--
drivers/baseband/acc100/rte_acc100_pmd.h | 11 +++
drivers/baseband/acc100/rte_acc101_pmd.h | 55 +++++++++++
7 files changed, 254 insertions(+), 19 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 17a0559..0610128 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1318,6 +1318,7 @@ F: doc/guides/bbdevs/features/fpga_5gnr_fec.ini
F: drivers/baseband/acc100/
F: doc/guides/bbdevs/acc100.rst
F: doc/guides/bbdevs/features/acc100.ini
+F: doc/guides/bbdevs/features/acc101.ini
Null baseband
M: Nicolas Chautru <nicolas.chautru@intel.com>
diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst
index 9fff6ab..ff07ed9 100644
--- a/doc/guides/bbdevs/acc100.rst
+++ b/doc/guides/bbdevs/acc100.rst
@@ -1,17 +1,19 @@
.. SPDX-License-Identifier: BSD-3-Clause
Copyright(c) 2020 Intel Corporation
-Intel(R) ACC100 5G/4G FEC Poll Mode Driver
-==========================================
+Intel(R) ACC100 and ACC101 5G/4G FEC Poll Mode Drivers
+======================================================
The BBDEV ACC100 5G/4G FEC poll mode driver (PMD) supports an
implementation of a VRAN FEC wireless acceleration function.
This device is also known as Mount Bryce.
+The BBDEV ACC101, also known as Mount Cirrus, is a derivative device from Mount Bryce
+with functional and capacity improvements but still with the same exposed BBDEV capabilities.
Features
--------
-ACC100 5G/4G FEC PMD supports the following features:
+ACC100 and ACC101 5G/4G FEC PMDs support the following features:
- LDPC Encode in the DL (5GNR)
- LDPC Decode in the UL (5GNR)
@@ -23,7 +25,7 @@ ACC100 5G/4G FEC PMD supports the following features:
- MSI
- SR-IOV
-ACC100 5G/4G FEC PMD supports the following BBDEV capabilities:
+ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities:
* For the LDPC encode operation:
- ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
@@ -80,14 +82,16 @@ hugepage configuration of a server may be examined using:
Initialization
--------------
-When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+When the device first powers up, its PCI Physical Functions (PF) can be listed through these
+commands for ACC100 and ACC101 respectively:
.. code-block:: console
sudo lspci -vd8086:0d5c
+ sudo lspci -vd8086:57c4
The physical and virtual functions are compatible with Linux UIO drivers:
-``vfio`` and ``igb_uio``. However, in order to work the ACC100 5G/4G
+``vfio`` and ``igb_uio``. However, in order to work the 5G/4G
FEC device first needs to be bound to one of these linux drivers through DPDK.
@@ -97,7 +101,8 @@ Bind PF UIO driver(s)
Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
-The igb_uio driver may be bound to the PF PCI device using one of two methods:
+The igb_uio driver may be bound to the PF PCI device using one of two methods for ACC100
+(for ACC101 the device id ``57c4`` should be used in lieu of ``0d5c``):
1. PCI functions (physical or virtual, depending on the use case) can be bound to
@@ -121,7 +126,7 @@ the UIO driver by repeating this command for every function.
where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d5c
-In a similar way the ACC100 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
+In a similar way the 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
Enable Virtual Functions
@@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and other settings necessary for the
device to perform FEC functions.
This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the function ``acc100_configure()``, which sets up the
-parameters defined in ``acc100_conf`` structure.
+be achieved by using the functions ``acc100_configure()`` or ``acc101_configure()``,
+which sets up the parameters defined in the compatible ``acc100_conf`` structure.
Test Application
----------------
BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
-the functionality of ACC100 5G/4G FEC encode and decode, depending on the device's
+the functionality of the device 5G/4G FEC encode and decode, depending on the device's
capabilities. The test application is located under app->test-bbdev folder and has the
following options:
@@ -212,7 +217,7 @@ Test Vectors
In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
a range of additional tests under the test_vectors folder, which may be useful. The results
-of these tests will depend on the ACC100 5G/4G FEC capabilities which may cause some
+of these tests will depend on the device 5G/4G FEC capabilities which may cause some
testcases to be skipped, but no failure should be reported.
@@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command below can be used:
./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg
./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
+Specifically for the BBDEV ACC101 PMD, the command below can be used:
+
+.. code-block:: console
+
+ ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg
+ ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
new file mode 100644
index 0000000..0e2c21a
--- /dev/null
+++ b/doc/guides/bbdevs/features/acc101.ini
@@ -0,0 +1,13 @@
+;
+; Supported features of the 'acc101' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G) = Y
+Turbo Encoder (4G) = Y
+LDPC Decoder (5G) = Y
+LDPC Encoder (5G) = Y
+LLR/HARQ Compression = Y
+External DDR Access = Y
+HW Accelerated = Y
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index e49cace..1803947 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -104,6 +104,9 @@ New Features
* ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
* ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
+* **Added Intel ACC101 baseband PMD.**
+
+ * Added a new baseband PMD for Intel ACC101 device.
Removed Items
-------------
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 3fdf17d..6a2123b 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -22,6 +22,7 @@
#include <rte_bbdev.h>
#include <rte_bbdev_pmd.h>
#include "rte_acc100_pmd.h"
+#include "rte_acc101_pmd.h"
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
@@ -1133,7 +1134,10 @@
/* ACC100 PCI PF address map */
static struct rte_pci_id pci_id_acc100_pf_map[] = {
{
- RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_PF_DEVICE_ID)
+ RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_PF_DEVICE_ID),
+ },
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID),
},
{.device_id = 0},
};
@@ -1141,7 +1145,10 @@
/* ACC100 PCI VF address map */
static struct rte_pci_id pci_id_acc100_vf_map[] = {
{
- RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_VF_DEVICE_ID)
+ RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_VF_DEVICE_ID),
+ },
+ {
+ RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID),
},
{.device_id = 0},
};
@@ -1290,7 +1297,7 @@
/* Fill in a frame control word for LDPC decoding. */
static inline void
-acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
union acc100_harq_layout_data *harq_layout)
{
uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
@@ -1414,6 +1421,128 @@
}
}
+/* Convert offset to harq index for harq_layout structure */
+static inline uint32_t hq_index(uint32_t offset)
+{
+ return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
+}
+
+/* Fill in a frame control word for LDPC decoding for ACC101 */
+static inline void
+acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout)
+{
+ uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
+ uint32_t harq_index;
+ uint32_t l;
+
+ fcw->qm = op->ldpc_dec.q_m;
+ fcw->nfiller = op->ldpc_dec.n_filler;
+ fcw->BG = (op->ldpc_dec.basegraph - 1);
+ fcw->Zc = op->ldpc_dec.z_c;
+ fcw->ncb = op->ldpc_dec.n_cb;
+ fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
+ op->ldpc_dec.rv_index);
+ if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
+ fcw->rm_e = op->ldpc_dec.cb_params.e;
+ else
+ fcw->rm_e = (op->ldpc_dec.tb_params.r <
+ op->ldpc_dec.tb_params.cab) ?
+ op->ldpc_dec.tb_params.ea :
+ op->ldpc_dec.tb_params.eb;
+
+ if (unlikely(check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
+ (op->ldpc_dec.harq_combined_input.length == 0))) {
+ rte_bbdev_log(WARNING, "Null HARQ input size provided");
+ /* Disable HARQ input in that case to carry forward */
+ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+ }
+
+ fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+ fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+ fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+ fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DECODE_BYPASS);
+ fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
+ if (op->ldpc_dec.q_m == 1) {
+ fcw->bypass_intlv = 1;
+ fcw->qm = 2;
+ }
+ fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_LLR_COMPRESSION);
+ harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
+ if (fcw->hcin_en > 0) {
+ harq_in_length = op->ldpc_dec.harq_combined_input.length;
+ if (fcw->hcin_decomp_mode > 0)
+ harq_in_length = harq_in_length * 8 / 6;
+ harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
+ - op->ldpc_dec.n_filler);
+ /* Alignment on next 64B - Already enforced from HC output */
+ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
+ fcw->hcin_size0 = harq_in_length;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ } else {
+ fcw->hcin_size0 = 0;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ }
+
+ fcw->itmax = op->ldpc_dec.iter_max;
+ fcw->itstop = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+ fcw->synd_precoder = fcw->itstop;
+ /*
+ * These are all implicitly set
+ * fcw->synd_post = 0;
+ * fcw->so_en = 0;
+ * fcw->so_bypass_rm = 0;
+ * fcw->so_bypass_intlv = 0;
+ * fcw->dec_convllr = 0;
+ * fcw->hcout_convllr = 0;
+ * fcw->hcout_size1 = 0;
+ * fcw->so_it = 0;
+ * fcw->hcout_offset = 0;
+ * fcw->negstop_th = 0;
+ * fcw->negstop_it = 0;
+ * fcw->negstop_en = 0;
+ * fcw->gain_i = 1;
+ * fcw->gain_h = 1;
+ */
+ if (fcw->hcout_en > 0) {
+ parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
+ * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
+ k0_p = (fcw->k0 > parity_offset) ?
+ fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
+ ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
+ l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
+ harq_out_length = (uint16_t) fcw->hcin_size0;
+ harq_out_length = RTE_MAX(harq_out_length, l);
+ /* Cannot exceed the pruned Ncb circular buffer */
+ harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+ /* Alignment on next 64B */
+ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
+ fcw->hcout_size0 = harq_out_length;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ harq_layout[harq_index].offset = fcw->hcout_offset;
+ harq_layout[harq_index].size0 = fcw->hcout_size0;
+ } else {
+ fcw->hcout_size0 = 0;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ }
+}
+
/**
* Fills descriptor with data pointers of one block type.
*
@@ -2966,7 +3095,7 @@
struct acc100_fcw_ld *fcw;
uint32_t seg_total_left;
fcw = &desc->req.fcw_ld;
- acc100_fcw_ld_fill(op, fcw, harq_layout);
+ q->d->fcw_ld_fill(op, fcw, harq_layout);
/* Special handling when overusing mbuf */
if (fcw->rm_e < ACC100_MAX_E_MBUF)
@@ -3033,7 +3162,7 @@
desc = q->ring_addr + desc_idx;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
- acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
+ q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
input = op->ldpc_dec.input.data;
h_output_head = h_output = op->ldpc_dec.hard_output.data;
@@ -4145,9 +4274,19 @@
dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
+ /* Device variant specific handling */
+ if ((pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID) ||
+ (pci_dev->id.device_id == RTE_ACC100_VF_DEVICE_ID)) {
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc100_fcw_ld_fill;
+ } else {
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc101_fcw_ld_fill;
+ }
+
((struct acc100_device *) dev->data->dev_private)->pf_device =
- !strcmp(drv->driver.name,
- RTE_STR(ACC100PF_DRIVER_NAME));
+ !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
+
((struct acc100_device *) dev->data->dev_private)->mmio_base =
pci_dev->mem_resource[0].addr;
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index 8fea322..39d5f22 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -22,6 +22,9 @@
#define rte_bbdev_log_debug(fmt, ...)
#endif
+#define ACC100_VARIANT 0
+#define ACC101_VARIANT 1
+
/* ACC100 PF and VF driver names */
#define ACC100PF_DRIVER_NAME intel_acc100_pf
#define ACC100VF_DRIVER_NAME intel_acc100_vf
@@ -67,6 +70,8 @@
#define ACC100_HARQ_LAYOUT (64*1024*1024)
/* Assume offset for HARQ in memory */
#define ACC100_HARQ_OFFSET (32*1024)
+#define ACC100_HARQ_OFFSET_SHIFT 15
+#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
#define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
/* Number of Virtual Functions ACC100 supports */
@@ -574,6 +579,10 @@ struct __rte_cache_aligned acc100_queue {
struct acc100_device *d;
};
+typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,
+ struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout);
+
/* Private data structure for each ACC100 device */
struct acc100_device {
void *mmio_base; /**< Base address of MMIO registers (BAR0) */
@@ -605,6 +614,8 @@ struct acc100_device {
uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
bool pf_device; /**< True if this is a PF ACC100 device */
bool configured; /**< True if this ACC100 device is configured */
+ uint16_t device_variant; /**< Device variant */
+ acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation function */
};
/**
diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h
new file mode 100644
index 0000000..8f1f4ab
--- /dev/null
+++ b/drivers/baseband/acc100/rte_acc101_pmd.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+/* ACC101 PCI vendor & device IDs */
+#define RTE_ACC101_VENDOR_ID (0x8086)
+#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
+#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
+
+/* Define as 1 to use only a single FEC engine */
+#ifndef RTE_ACC101_SINGLE_FEC
+#define RTE_ACC101_SINGLE_FEC 0
+#endif
+
+/* Number of Virtual Functions ACC101 supports */
+#define ACC101_NUM_VFS 16
+#define ACC101_NUM_QGRPS 8
+#define ACC101_NUM_AQS 16
+/* All ACC101 Registers alignment are 32bits = 4B */
+#define ACC101_BYTES_IN_WORD 4
+
+#define ACC101_TMPL_PRI_0 0x03020100
+#define ACC101_TMPL_PRI_1 0x07060504
+#define ACC101_TMPL_PRI_2 0x0b0a0908
+#define ACC101_TMPL_PRI_3 0x0f0e0d0c
+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
+
+#define ACC101_NUM_TMPL 32
+/* Mapping of signals for the available engines */
+#define ACC101_SIG_UL_5G 0
+#define ACC101_SIG_UL_5G_LAST 8
+#define ACC101_SIG_DL_5G 13
+#define ACC101_SIG_DL_5G_LAST 15
+#define ACC101_SIG_UL_4G 16
+#define ACC101_SIG_UL_4G_LAST 19
+#define ACC101_SIG_DL_4G 27
+#define ACC101_SIG_DL_4G_LAST 31
+#define ACC101_NUM_ACCS 5
+#define ACC101_PF_VAL 2
+
+/* ACC101 Configuration */
+#define ACC101_CFG_DMA_ERROR 0x3D7
+#define ACC101_CFG_AXI_CACHE 0x11
+#define ACC101_CFG_QMGR_HI_P 0x0F0F
+#define ACC101_CFG_PCI_AXI 0xC003
+#define ACC101_CFG_PCI_BRIDGE 0x40006033
+#define ACC101_ENGINE_OFFSET 0x1000
+#define ACC101_LONG_WAIT 1000
+#define ACC101_GPEX_AXIMAP_NUM 17
+#define ACC101_CLOCK_GATING_EN 0x30000
+#define ACC101_DMA_INBOUND 0x104
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC101_HARQ_DDR (512 * 1)
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v6 4/5] baseband/acc100: modify validation code for ACC101
2022-05-26 0:55 ` Nicolas Chautru
` (2 preceding siblings ...)
2022-05-26 0:55 ` [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-26 0:55 ` Nicolas Chautru
2022-05-31 8:02 ` Maxime Coquelin
2022-05-26 0:55 ` [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
4 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-26 0:55 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
The validation requirement is different for the two
devices.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 47 ++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 6a2123b..a057edf 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1295,6 +1295,21 @@
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+static inline bool
+is_acc100(struct acc100_queue *q)
+{
+ return (q->d->device_variant == ACC100_VARIANT);
+}
+
+static inline bool
+validate_op_required(struct acc100_queue *q)
+{
+ return is_acc100(q);
+}
+#endif
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -2182,8 +2197,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo encoder parameters */
static inline int
-validate_enc_op(struct rte_bbdev_enc_op *op)
+validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
@@ -2320,8 +2337,10 @@ static inline uint32_t hq_index(uint32_t offset)
}
/* Validates LDPC encoder parameters */
static inline int
-validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
+validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
if (op->mempool == NULL) {
@@ -2373,8 +2392,10 @@ static inline uint32_t hq_index(uint32_t offset)
/* Validates LDPC decoder parameters */
static inline int
-validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
+validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
if (op->mempool == NULL) {
@@ -2429,7 +2450,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2483,7 +2504,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(ops[0]) == -1) {
+ if (validate_ldpc_enc_op(ops[0], q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2545,7 +2566,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(op) == -1) {
+ if (validate_ldpc_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2602,7 +2623,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2675,8 +2696,10 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo decoder parameters */
static inline int
-validate_dec_op(struct rte_bbdev_dec_op *op)
+validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
+ if (!validate_op_required(q))
+ return 0;
struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
@@ -2822,7 +2845,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
@@ -3047,7 +3070,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3151,7 +3174,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3241,7 +3264,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF
2022-05-26 0:55 ` Nicolas Chautru
` (3 preceding siblings ...)
2022-05-26 0:55 ` [PATCH v6 4/5] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-26 0:55 ` Nicolas Chautru
2022-05-31 7:35 ` Maxime Coquelin
4 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-26 0:55 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Adding companion function common to ACC100/ACC101 which
can be called from bbdev-test when running from PF.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 6 +-
drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
drivers/baseband/acc100/rte_acc100_pmd.c | 323 ++++++++++++++++++++++++++++++-
drivers/baseband/acc100/version.map | 3 +-
4 files changed, 327 insertions(+), 9 deletions(-)
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 0fa119a..718e5ef 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -711,11 +711,11 @@ typedef int (test_case_function)(struct active_device *ad,
#endif
#ifdef RTE_BASEBAND_ACC100
if ((get_init_device() == true) &&
- (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
+ (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
struct rte_acc100_conf conf;
unsigned int i;
- printf("Configure ACC100 FEC Driver %s with default values\n",
+ printf("Configure ACC100/ACC101 FEC Driver %s with default values\n",
info->drv.driver_name);
/* clear default configuration before initialization */
@@ -760,7 +760,7 @@ typedef int (test_case_function)(struct active_device *ad,
conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
/* setup PF with configuration information */
- ret = rte_acc100_configure(info->dev_name, &conf);
+ ret = rte_acc10x_configure(info->dev_name, &conf);
TEST_ASSERT_SUCCESS(ret,
"Failed to configure ACC100 PF for bbdev %s",
info->dev_name);
diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
index d233e42..b70803d 100644
--- a/drivers/baseband/acc100/rte_acc100_cfg.h
+++ b/drivers/baseband/acc100/rte_acc100_cfg.h
@@ -90,7 +90,7 @@ struct rte_acc100_conf {
};
/**
- * Configure a ACC100 device
+ * Configure a ACC100/ACC101 device in PF mode notably for bbdev-test
*
* @param dev_name
* The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
@@ -104,7 +104,7 @@ struct rte_acc100_conf {
*/
__rte_experimental
int
-rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
+rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf);
#ifdef __cplusplus
}
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index a057edf..86545cc 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -4574,8 +4574,8 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Initial configuration of a ACC100 device prior to running configure() */
-int
-rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
+static int
+acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
{
rte_bbdev_log(INFO, "rte_acc100_configure");
uint32_t value, address, status;
@@ -4975,3 +4975,322 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
+
+
+/* Initial configuration of a ACC101 device prior to running configure() */
+static int
+acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc101_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc100_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+
+ /* PCIe Bridge configuration */
+ acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
+ for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
+ acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
+
+ /* Prevent blocking AXI read on BRESP for AXI Write */
+ address = HwPfPcieGpexAxiPioControl;
+ value = ACC101_CFG_PCI_AXI;
+ acc100_reg_write(d, address, value);
+
+ /* Explicitly releasing AXI including a 2ms delay on ACC101 */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* Set the default 5GDL DMA configuration */
+ acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
+
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC101_CLOCK_GATING_EN;
+ acc100_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC101_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc100_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC101_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc100_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ address = HWPfDmaConfig1Reg;
+ int alen_r = 0xF;
+ int alen_w = 0x7;
+ value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
+ acc100_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc100_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_1;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_2;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_3;
+ acc100_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC101_CFG_QMGR_HI_P;
+ acc100_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_4G;
+ template_idx <= ACC101_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_5G;
+ template_idx <= ACC101_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg +
+ ACC101_ENGINE_OFFSET * template_idx;
+ status = (acc100_reg_read(d, address) >> 4) & 0xF;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc100_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc100_reg_write(d, address, 0);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ printf("Number of 5GUL engines %d\n", numEngines);
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_4G;
+ template_idx <= ACC101_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_5G;
+ template_idx <= ACC101_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+#if RTE_ACC101_SINGLE_FEC == 1
+ value = 0;
+#endif
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ address = HWPfQmgrGrpFunction0;
+ value = 0;
+ for (qg_idx = 0; qg_idx < 8; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc]<<(qg_idx * 4);
+ }
+ acc100_reg_write(d, address, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC101_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc100_reg_write(d, address, value);
+ }
+ }
+
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC101_BYTES_IN_WORD + qg_idx
+ * ACC101_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc100_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC101_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
+ acc100_reg_write(d, address, value);
+ /* Explicitly releasing AXI after PF Mode and 2 ms */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc100_reg_write(d, address, value);
+
+ /* HARQ DDR Configuration */
+ unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfDmaVfDdrBaseRw + vf_idx
+ * 0x10;
+ value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
+ (ddrSizeInMb - 1);
+ acc100_reg_write(d, address, value);
+ }
+ usleep(ACC101_LONG_WAIT);
+
+ rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
+ return 0;
+}
+
+int
+rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
+ printf("Configure dev id %x\n", pci_dev->id.device_id);
+ if (pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID)
+ return acc100_configure(dev_name, conf);
+ else
+ return acc101_configure(dev_name, conf);
+}
diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map
index 40604c7..13f0398 100644
--- a/drivers/baseband/acc100/version.map
+++ b/drivers/baseband/acc100/version.map
@@ -5,6 +5,5 @@ DPDK_22 {
EXPERIMENTAL {
global:
- rte_acc100_configure;
-
+ rte_acc10x_configure;
};
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101
2022-05-26 0:55 ` [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-30 7:40 ` Akhil Goyal
2022-05-31 18:59 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Akhil Goyal @ 2022-05-30 7:40 UTC (permalink / raw)
To: Nicolas Chautru, dev, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
>
>
> Enable Virtual Functions
> @@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and other
> settings necessary for the
> device to perform FEC functions.
>
> This configuration needs to be executed at least once after reboot or PCI FLR
> and can
> -be achieved by using the function ``acc100_configure()``, which sets up the
> -parameters defined in ``acc100_conf`` structure.
> +be achieved by using the functions ``acc100_configure()`` or
> ``acc101_configure()``,
I believe the API for user is common now. Right? So why to have two references?
> +which sets up the parameters defined in the compatible ``acc100_conf``
> structure.
>
> Test Application
> ----------------
>
> BBDEV provides a test application, ``test-bbdev.py`` and range of test data for
> testing
> -the functionality of ACC100 5G/4G FEC encode and decode, depending on the
> device's
> +the functionality of the device 5G/4G FEC encode and decode, depending on
> the device's
> capabilities. The test application is located under app->test-bbdev folder and
> has the
> following options:
>
> @@ -212,7 +217,7 @@ Test Vectors
>
> In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also
> provides
> a range of additional tests under the test_vectors folder, which may be useful.
> The results
> -of these tests will depend on the ACC100 5G/4G FEC capabilities which may
> cause some
> +of these tests will depend on the device 5G/4G FEC capabilities which may
> cause some
> testcases to be skipped, but no failure should be reported.
>
>
> @@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command
> below can be used:
>
> ./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg
> ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v
> ./ldpc_dec_default.data
> +
> +Specifically for the BBDEV ACC101 PMD, the command below can be used:
> +
> +.. code-block:: console
> +
> + ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg
> + ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -
> v ./ldpc_dec_default.data
> +
> diff --git a/doc/guides/bbdevs/features/acc101.ini
> b/doc/guides/bbdevs/features/acc101.ini
> new file mode 100644
> index 0000000..0e2c21a
> --- /dev/null
> +++ b/doc/guides/bbdevs/features/acc101.ini
> @@ -0,0 +1,13 @@
> +;
> +; Supported features of the 'acc101' bbdev driver.
> +;
> +; Refer to default.ini for the full list of available PMD features.
> +;
> +[Features]
> +Turbo Decoder (4G) = Y
> +Turbo Encoder (4G) = Y
> +LDPC Decoder (5G) = Y
> +LDPC Encoder (5G) = Y
> +LLR/HARQ Compression = Y
> +External DDR Access = Y
> +HW Accelerated = Y
> diff --git a/doc/guides/rel_notes/release_22_07.rst
> b/doc/guides/rel_notes/release_22_07.rst
> index e49cace..1803947 100644
> --- a/doc/guides/rel_notes/release_22_07.rst
> +++ b/doc/guides/rel_notes/release_22_07.rst
> @@ -104,6 +104,9 @@ New Features
> * ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
> * ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
>
> +* **Added Intel ACC101 baseband PMD.**
> +
> + * Added a new baseband PMD for Intel ACC101 device.
>
> Removed Items
> -------------
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> b/drivers/baseband/acc100/rte_acc100_pmd.c
> index 3fdf17d..6a2123b 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -22,6 +22,7 @@
> #include <rte_bbdev.h>
> #include <rte_bbdev_pmd.h>
> #include "rte_acc100_pmd.h"
> +#include "rte_acc101_pmd.h"
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
> @@ -1133,7 +1134,10 @@
> /* ACC100 PCI PF address map */
> static struct rte_pci_id pci_id_acc100_pf_map[] = {
> {
> - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> RTE_ACC100_PF_DEVICE_ID)
> + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> RTE_ACC100_PF_DEVICE_ID),
> + },
> + {
> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> RTE_ACC101_PF_DEVICE_ID),
> },
> {.device_id = 0},
> };
> @@ -1141,7 +1145,10 @@
> /* ACC100 PCI VF address map */
> static struct rte_pci_id pci_id_acc100_vf_map[] = {
> {
> - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> RTE_ACC100_VF_DEVICE_ID)
> + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> RTE_ACC100_VF_DEVICE_ID),
> + },
> + {
> + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> RTE_ACC101_VF_DEVICE_ID),
> },
> {.device_id = 0},
> };
> @@ -1290,7 +1297,7 @@
>
> /* Fill in a frame control word for LDPC decoding. */
> static inline void
> -acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld
> *fcw,
> +acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> union acc100_harq_layout_data *harq_layout)
> {
> uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
> @@ -1414,6 +1421,128 @@
> }
> }
>
> +/* Convert offset to harq index for harq_layout structure */
> +static inline uint32_t hq_index(uint32_t offset)
> +{
> + return (offset >> ACC100_HARQ_OFFSET_SHIFT) &
> ACC100_HARQ_OFFSET_MASK;
> +}
> +
> +/* Fill in a frame control word for LDPC decoding for ACC101 */
> +static inline void
> +acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> + union acc100_harq_layout_data *harq_layout)
> +{
> + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
> + uint32_t harq_index;
> + uint32_t l;
> +
> + fcw->qm = op->ldpc_dec.q_m;
> + fcw->nfiller = op->ldpc_dec.n_filler;
> + fcw->BG = (op->ldpc_dec.basegraph - 1);
> + fcw->Zc = op->ldpc_dec.z_c;
> + fcw->ncb = op->ldpc_dec.n_cb;
> + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
> + op->ldpc_dec.rv_index);
> + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
> + fcw->rm_e = op->ldpc_dec.cb_params.e;
> + else
> + fcw->rm_e = (op->ldpc_dec.tb_params.r <
> + op->ldpc_dec.tb_params.cab) ?
> + op->ldpc_dec.tb_params.ea :
> + op->ldpc_dec.tb_params.eb;
> +
> + if (unlikely(check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
> + (op->ldpc_dec.harq_combined_input.length == 0))) {
> + rte_bbdev_log(WARNING, "Null HARQ input size provided");
> + /* Disable HARQ input in that case to carry forward */
> + op->ldpc_dec.op_flags ^=
> RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> + }
> +
> + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
> + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
> + fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
> + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_DECODE_BYPASS);
> + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
> + if (op->ldpc_dec.q_m == 1) {
> + fcw->bypass_intlv = 1;
> + fcw->qm = 2;
> + }
> + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_LLR_COMPRESSION);
> + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
> + if (fcw->hcin_en > 0) {
> + harq_in_length = op->ldpc_dec.harq_combined_input.length;
> + if (fcw->hcin_decomp_mode > 0)
> + harq_in_length = harq_in_length * 8 / 6;
> + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
> + - op->ldpc_dec.n_filler);
> + /* Alignment on next 64B - Already enforced from HC output */
> + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> + fcw->hcin_size0 = harq_in_length;
> + fcw->hcin_offset = 0;
> + fcw->hcin_size1 = 0;
> + } else {
> + fcw->hcin_size0 = 0;
> + fcw->hcin_offset = 0;
> + fcw->hcin_size1 = 0;
> + }
> +
> + fcw->itmax = op->ldpc_dec.iter_max;
> + fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
> + fcw->synd_precoder = fcw->itstop;
> + /*
> + * These are all implicitly set
> + * fcw->synd_post = 0;
> + * fcw->so_en = 0;
> + * fcw->so_bypass_rm = 0;
> + * fcw->so_bypass_intlv = 0;
> + * fcw->dec_convllr = 0;
> + * fcw->hcout_convllr = 0;
> + * fcw->hcout_size1 = 0;
> + * fcw->so_it = 0;
> + * fcw->hcout_offset = 0;
> + * fcw->negstop_th = 0;
> + * fcw->negstop_it = 0;
> + * fcw->negstop_en = 0;
> + * fcw->gain_i = 1;
> + * fcw->gain_h = 1;
> + */
> + if (fcw->hcout_en > 0) {
> + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
> + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
> + k0_p = (fcw->k0 > parity_offset) ?
> + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
> + ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
> + harq_out_length = (uint16_t) fcw->hcin_size0;
> + harq_out_length = RTE_MAX(harq_out_length, l);
> + /* Cannot exceed the pruned Ncb circular buffer */
> + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> + /* Alignment on next 64B */
> + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> + fcw->hcout_size0 = harq_out_length;
> + fcw->hcout_size1 = 0;
> + fcw->hcout_offset = 0;
> + harq_layout[harq_index].offset = fcw->hcout_offset;
> + harq_layout[harq_index].size0 = fcw->hcout_size0;
> + } else {
> + fcw->hcout_size0 = 0;
> + fcw->hcout_size1 = 0;
> + fcw->hcout_offset = 0;
> + }
> +}
> +
> /**
> * Fills descriptor with data pointers of one block type.
> *
> @@ -2966,7 +3095,7 @@
> struct acc100_fcw_ld *fcw;
> uint32_t seg_total_left;
> fcw = &desc->req.fcw_ld;
> - acc100_fcw_ld_fill(op, fcw, harq_layout);
> + q->d->fcw_ld_fill(op, fcw, harq_layout);
>
> /* Special handling when overusing mbuf */
> if (fcw->rm_e < ACC100_MAX_E_MBUF)
> @@ -3033,7 +3162,7 @@
> desc = q->ring_addr + desc_idx;
> uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
> union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
> - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
> + q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
>
> input = op->ldpc_dec.input.data;
> h_output_head = h_output = op->ldpc_dec.hard_output.data;
> @@ -4145,9 +4274,19 @@
> dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
> dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
>
> + /* Device variant specific handling */
> + if ((pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID) ||
> + (pci_dev->id.device_id == RTE_ACC100_VF_DEVICE_ID))
> {
> + ((struct acc100_device *) dev->data->dev_private)-
> >device_variant = ACC100_VARIANT;
> + ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill
> = acc100_fcw_ld_fill;
> + } else {
> + ((struct acc100_device *) dev->data->dev_private)-
> >device_variant = ACC101_VARIANT;
> + ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill
> = acc101_fcw_ld_fill;
> + }
> +
> ((struct acc100_device *) dev->data->dev_private)->pf_device =
> - !strcmp(drv->driver.name,
> - RTE_STR(ACC100PF_DRIVER_NAME));
> + !strcmp(drv->driver.name,
> RTE_STR(ACC100PF_DRIVER_NAME));
> +
> ((struct acc100_device *) dev->data->dev_private)->mmio_base =
> pci_dev->mem_resource[0].addr;
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h
> b/drivers/baseband/acc100/rte_acc100_pmd.h
> index 8fea322..39d5f22 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> @@ -22,6 +22,9 @@
> #define rte_bbdev_log_debug(fmt, ...)
> #endif
>
> +#define ACC100_VARIANT 0
> +#define ACC101_VARIANT 1
Since you are using PCI dev id for identifying the device. Do we still need above defines?
> +
> /* ACC100 PF and VF driver names */
> #define ACC100PF_DRIVER_NAME intel_acc100_pf
> #define ACC100VF_DRIVER_NAME intel_acc100_vf
> @@ -67,6 +70,8 @@
> #define ACC100_HARQ_LAYOUT (64*1024*1024)
> /* Assume offset for HARQ in memory */
> #define ACC100_HARQ_OFFSET (32*1024)
> +#define ACC100_HARQ_OFFSET_SHIFT 15
> +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
> /* Mask used to calculate an index in an Info Ring array (not a byte offset) */
> #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-
> 1)
> /* Number of Virtual Functions ACC100 supports */
> @@ -574,6 +579,10 @@ struct __rte_cache_aligned acc100_queue {
> struct acc100_device *d;
> };
>
> +typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,
> + struct acc100_fcw_ld *fcw,
> + union acc100_harq_layout_data *harq_layout);
> +
> /* Private data structure for each ACC100 device */
> struct acc100_device {
> void *mmio_base; /**< Base address of MMIO registers (BAR0) */
> @@ -605,6 +614,8 @@ struct acc100_device {
> uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
> bool pf_device; /**< True if this is a PF ACC100 device */
> bool configured; /**< True if this ACC100 device is configured */
> + uint16_t device_variant; /**< Device variant */
> + acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation
> function */
> };
>
> /**
> diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h
> b/drivers/baseband/acc100/rte_acc101_pmd.h
> new file mode 100644
> index 0000000..8f1f4ab
> --- /dev/null
> +++ b/drivers/baseband/acc100/rte_acc101_pmd.h
This file is internal, shouldn't we drop the rte?
> @@ -0,0 +1,55 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +/* ACC101 PCI vendor & device IDs */
> +#define RTE_ACC101_VENDOR_ID (0x8086)
> +#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
> +#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
> +
> +/* Define as 1 to use only a single FEC engine */
> +#ifndef RTE_ACC101_SINGLE_FEC
> +#define RTE_ACC101_SINGLE_FEC 0
> +#endif
Also the above defines should drop RTE if they are internal symbols.
> +
> +/* Number of Virtual Functions ACC101 supports */
> +#define ACC101_NUM_VFS 16
> +#define ACC101_NUM_QGRPS 8
> +#define ACC101_NUM_AQS 16
> +/* All ACC101 Registers alignment are 32bits = 4B */
> +#define ACC101_BYTES_IN_WORD 4
> +
> +#define ACC101_TMPL_PRI_0 0x03020100
> +#define ACC101_TMPL_PRI_1 0x07060504
> +#define ACC101_TMPL_PRI_2 0x0b0a0908
> +#define ACC101_TMPL_PRI_3 0x0f0e0d0c
> +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
> +
> +#define ACC101_NUM_TMPL 32
> +/* Mapping of signals for the available engines */
> +#define ACC101_SIG_UL_5G 0
> +#define ACC101_SIG_UL_5G_LAST 8
> +#define ACC101_SIG_DL_5G 13
> +#define ACC101_SIG_DL_5G_LAST 15
> +#define ACC101_SIG_UL_4G 16
> +#define ACC101_SIG_UL_4G_LAST 19
> +#define ACC101_SIG_DL_4G 27
> +#define ACC101_SIG_DL_4G_LAST 31
> +#define ACC101_NUM_ACCS 5
> +#define ACC101_PF_VAL 2
> +
> +/* ACC101 Configuration */
> +#define ACC101_CFG_DMA_ERROR 0x3D7
> +#define ACC101_CFG_AXI_CACHE 0x11
> +#define ACC101_CFG_QMGR_HI_P 0x0F0F
> +#define ACC101_CFG_PCI_AXI 0xC003
> +#define ACC101_CFG_PCI_BRIDGE 0x40006033
> +#define ACC101_ENGINE_OFFSET 0x1000
> +#define ACC101_LONG_WAIT 1000
> +#define ACC101_GPEX_AXIMAP_NUM 17
> +#define ACC101_CLOCK_GATING_EN 0x30000
> +#define ACC101_DMA_INBOUND 0x104
> +/* DDR Size per VF - 512MB by default
> + * Can be increased up to 4 GB with single PF/VF
> + */
> +#define ACC101_HARQ_DDR (512 * 1)
> --
> 1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF
2022-05-26 0:55 ` [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-05-31 7:35 ` Maxime Coquelin
2022-05-31 18:28 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Maxime Coquelin @ 2022-05-31 7:35 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
Hi Nicolas,
Thanks for doing the API change, this part looks good to me now.
I just have one comment below that was not addressed:
On 5/26/22 02:55, Nicolas Chautru wrote:
> Adding companion function common to ACC100/ACC101 which
> can be called from bbdev-test when running from PF.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> app/test-bbdev/test_bbdev_perf.c | 6 +-
> drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> drivers/baseband/acc100/rte_acc100_pmd.c | 323 ++++++++++++++++++++++++++++++-
> drivers/baseband/acc100/version.map | 3 +-
> 4 files changed, 327 insertions(+), 9 deletions(-)
>
...
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index a057edf..86545cc 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -4574,8 +4574,8 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
> }
>
> /* Initial configuration of a ACC100 device prior to running configure() */
> -int
> -rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
> +static int
> +acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
> {
> rte_bbdev_log(INFO, "rte_acc100_configure");
> uint32_t value, address, status;
> @@ -4975,3 +4975,322 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
> rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
> return 0;
> }
> +
> +
> +/* Initial configuration of a ACC101 device prior to running configure() */
> +static int
> +acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
> +{
> + rte_bbdev_log(INFO, "rte_acc101_configure");
> + uint32_t value, address, status;
> + int qg_idx, template_idx, vf_idx, acc, i;
> + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> +
> + /* Compile time checks */
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
> + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
> +
> + if (bbdev == NULL) {
> + rte_bbdev_log(ERR,
> + "Invalid dev_name (%s), or device is not yet initialised",
> + dev_name);
> + return -ENODEV;
> + }
> + struct acc100_device *d = bbdev->data->dev_private;
> +
> + /* Store configuration */
> + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
> +
> + /* PCIe Bridge configuration */
> + acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
> + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
> + acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
> +
> + /* Prevent blocking AXI read on BRESP for AXI Write */
> + address = HwPfPcieGpexAxiPioControl;
> + value = ACC101_CFG_PCI_AXI;
> + acc100_reg_write(d, address, value);
> +
> + /* Explicitly releasing AXI including a 2ms delay on ACC101 */
> + usleep(2000);
> + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> +
> + /* Set the default 5GDL DMA configuration */
> + acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
> +
> + /* Enable granular dynamic clock gating */
> + address = HWPfHiClkGateHystReg;
> + value = ACC101_CLOCK_GATING_EN;
> + acc100_reg_write(d, address, value);
> +
> + /* Set default descriptor signature */
> + address = HWPfDmaDescriptorSignatuture;
> + value = 0;
> + acc100_reg_write(d, address, value);
> +
> + /* Enable the Error Detection in DMA */
> + value = ACC101_CFG_DMA_ERROR;
> + address = HWPfDmaErrorDetectionEn;
> + acc100_reg_write(d, address, value);
> +
> + /* AXI Cache configuration */
> + value = ACC101_CFG_AXI_CACHE;
> + address = HWPfDmaAxcacheReg;
> + acc100_reg_write(d, address, value);
> +
> + /* Default DMA Configuration (Qmgr Enabled) */
> + address = HWPfDmaConfig0Reg;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + address = HWPfDmaQmanen;
> + value = 0;
> + acc100_reg_write(d, address, value);
> +
> + /* Default RLIM/ALEN configuration */
> + address = HWPfDmaConfig1Reg;
> + int alen_r = 0xF;
> + int alen_w = 0x7;
> + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
> + acc100_reg_write(d, address, value);
> +
> + /* Configure DMA Qmanager addresses */
> + address = HWPfDmaQmgrAddrReg;
> + value = HWPfQmgrEgressQueuesTemplate;
> + acc100_reg_write(d, address, value);
> +
> + /* ===== Qmgr Configuration ===== */
> + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
> + int totalQgs = conf->q_ul_4g.num_qgroups +
> + conf->q_ul_5g.num_qgroups +
> + conf->q_dl_4g.num_qgroups +
> + conf->q_dl_5g.num_qgroups;
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + address = HWPfQmgrDepthLog2Grp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = aqDepth(qg_idx, conf);
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrTholdGrp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> + acc100_reg_write(d, address, value);
> + }
> +
> + /* Template Priority in incremental order */
> + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_0;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_1;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_2;
> + acc100_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
> + value = ACC101_TMPL_PRI_3;
> + acc100_reg_write(d, address, value);
> + }
> +
> + address = HWPfQmgrGrpPriority;
> + value = ACC101_CFG_QMGR_HI_P;
> + acc100_reg_write(d, address, value);
> +
> + /* Template Configuration */
> + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> + template_idx++) {
> + value = 0;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> + }
> + /* 4GUL */
> + int numQgs = conf->q_ul_4g.num_qgroups;
> + int numQqsAcc = 0;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_UL_4G;
> + template_idx <= ACC101_SIG_UL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> + }
> + /* 5GUL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_ul_5g.num_qgroups;
> + value = 0;
> + int numEngines = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_UL_5G;
> + template_idx <= ACC101_SIG_UL_5G_LAST;
> + template_idx++) {
> + /* Check engine power-on status */
> + address = HwPfFecUl5gIbDebugReg +
> + ACC101_ENGINE_OFFSET * template_idx;
> + status = (acc100_reg_read(d, address) >> 4) & 0xF;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + if (status == 1) {
> + acc100_reg_write(d, address, value);
> + numEngines++;
> + } else
> + acc100_reg_write(d, address, 0);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> + printf("Number of 5GUL engines %d\n", numEngines);
> + /* 4GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_4g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_DL_4G;
> + template_idx <= ACC101_SIG_DL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
As I mentionned on previous revision, single FEC case should be handled
via a devarg, so that testing both cases do not require a rebuild.
> + }
> + /* 5GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_5g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC101_SIG_DL_5G;
> + template_idx <= ACC101_SIG_DL_5G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC101_BYTES_IN_WORD * template_idx;
> + acc100_reg_write(d, address, value);
> +#if RTE_ACC101_SINGLE_FEC == 1
> + value = 0;
> +#endif
> + }
> +
> + /* Queue Group Function mapping */
> + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> + address = HWPfQmgrGrpFunction0;
> + value = 0;
> + for (qg_idx = 0; qg_idx < 8; qg_idx++) {
> + acc = accFromQgid(qg_idx, conf);
> + value |= qman_func_id[acc]<<(qg_idx * 4);
> + }
> + acc100_reg_write(d, address, value);
> +
> + /* Configuration of the Arbitration QGroup depth to 1 */
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + address = HWPfQmgrArbQDepthGrp +
> + ACC101_BYTES_IN_WORD * qg_idx;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + }
> +
> + /* Enabling AQueues through the Queue hierarchy*/
> + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
> + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
> + value = 0;
> + if (vf_idx < conf->num_vf_bundles &&
> + qg_idx < totalQgs)
> + value = (1 << aqNum(qg_idx, conf)) - 1;
> + address = HWPfQmgrAqEnableVf
> + + vf_idx * ACC101_BYTES_IN_WORD;
> + value += (qg_idx << 16);
> + acc100_reg_write(d, address, value);
> + }
> + }
> +
> + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
> + uint32_t aram_address = 0;
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> + address = HWPfQmgrVfBaseAddr + vf_idx
> + * ACC101_BYTES_IN_WORD + qg_idx
> + * ACC101_BYTES_IN_WORD * 64;
> + value = aram_address;
> + acc100_reg_write(d, address, value);
> + /* Offset ARAM Address for next memory bank
> + * - increment of 4B
> + */
> + aram_address += aqNum(qg_idx, conf) *
> + (1 << aqDepth(qg_idx, conf));
> + }
> + }
> +
> + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
> + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
> + aram_address, ACC101_WORDS_IN_ARAM_SIZE);
> + return -EINVAL;
> + }
> +
> + /* ==== HI Configuration ==== */
> +
> + /* No Info Ring/MSI by default */
> + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
> + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
> + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
> + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
> + /* Prevent Block on Transmit Error */
> + address = HWPfHiBlockTransmitOnErrorEn;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + /* Prevents to drop MSI */
> + address = HWPfHiMsiDropEnableReg;
> + value = 0;
> + acc100_reg_write(d, address, value);
> + /* Set the PF Mode register */
> + address = HWPfHiPfMode;
> + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
> + acc100_reg_write(d, address, value);
> + /* Explicitly releasing AXI after PF Mode and 2 ms */
> + usleep(2000);
> + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> +
> + /* QoS overflow init */
> + value = 1;
> + address = HWPfQosmonAEvalOverflow0;
> + acc100_reg_write(d, address, value);
> + address = HWPfQosmonBEvalOverflow0;
> + acc100_reg_write(d, address, value);
> +
> + /* HARQ DDR Configuration */
> + unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
> + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> + address = HWPfDmaVfDdrBaseRw + vf_idx
> + * 0x10;
> + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
> + (ddrSizeInMb - 1);
> + acc100_reg_write(d, address, value);
> + }
> + usleep(ACC101_LONG_WAIT);
> +
> + rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
> + return 0;
> +}
> +
> +int
> +rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf)
> +{
> + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> + if (bbdev == NULL) {
> + rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not yet initialised",
> + dev_name);
> + return -ENODEV;
> + }
> + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
> + printf("Configure dev id %x\n", pci_dev->id.device_id);
> + if (pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID)
> + return acc100_configure(dev_name, conf);
> + else
> + return acc101_configure(dev_name, conf);
> +}
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v5 4/5] baseband/acc100: modify validation code for ACC101
2022-05-25 22:15 ` Chautru, Nicolas
@ 2022-05-31 7:59 ` Maxime Coquelin
2022-05-31 18:19 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Maxime Coquelin @ 2022-05-31 7:59 UTC (permalink / raw)
To: Chautru, Nicolas, dev, gakhil, trix
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Nicolas,
On 5/26/22 00:15, Chautru, Nicolas wrote:
>
>
>> -----Original Message-----
>> From: Maxime Coquelin <maxime.coquelin@redhat.com>
>> Sent: Wednesday, May 25, 2022 7:33 AM
>> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
>> gakhil@marvell.com; trix@redhat.com
>> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
>> Richardson, Bruce <bruce.richardson@intel.com>;
>> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
>> david.marchand@redhat.com
>> Subject: Re: [PATCH v5 4/5] baseband/acc100: modify validation code for
>> ACC101
>>
>>
>>
>> On 5/24/22 02:08, Nicolas Chautru wrote:
>>> The validation requirement is different for the two devices.
>>>
>>> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
>>> ---
>>> drivers/baseband/acc100/rte_acc100_pmd.c | 47
>> ++++++++++++++++++++++++--------
>>> 1 file changed, 35 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> index 41475b2..e3706e0 100644
>>> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
>>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
>>> @@ -1289,6 +1289,21 @@
>>> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
>>> }
>>>
>>> +#ifdef RTE_LIBRTE_BBDEV_DEBUG
>>> +
>>> +static inline bool
>>> +is_acc100(struct acc100_queue *q)
>>> +{
>>> + return (q->d->device_variant == ACC100_VARIANT);
>>
>> I keep insisting, but please rely on the PCI device ID, there is no need to
>> introduce a new field.
>
> Thanks. I have a couple of concerns changing this:
> 1) the device id is not accessible from the structures currently passed by the functions which would rely on this. Ie. device_id is accessible from rte_bbdev/rte_device but not from acc100_device or acc100_queue. Would be convoluted to have to carry forward this structure when needed instead of using directly acc100_device structure.
> 2) These call would be done as part of the workload operation where performance matters, best to keep the check as trivial as possible within the PMD.
I think it is better to have a pointer to the rte_bbdev/rte_device than
introducing a new ID.
Regarding performance, is_acc100 is only defined in
RTE_LIBRTE_BBDEV_DEBUG, so it should not be that critical.
Regarding that, I have hard time to understand why we need to validate
encoder/decoder parameters in ACC100 case, but not in ACC101 one. For
example, I guess having a valid mempool pointer is required in both
ACC100 and ACC101 cases.
> Will aim for new patch in next few days based on the other refactory suggestions and unified driver.
>
> Thanks
> Nic
Thanks,
Maxime
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v6 4/5] baseband/acc100: modify validation code for ACC101
2022-05-26 0:55 ` [PATCH v6 4/5] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-31 8:02 ` Maxime Coquelin
2022-05-31 18:16 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Maxime Coquelin @ 2022-05-31 8:02 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
On 5/26/22 02:55, Nicolas Chautru wrote:
> The validation requirement is different for the two
> devices.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/rte_acc100_pmd.c | 47 ++++++++++++++++++++++++--------
> 1 file changed, 35 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index 6a2123b..a057edf 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -1295,6 +1295,21 @@
> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> }
>
> +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> +
> +static inline bool
> +is_acc100(struct acc100_queue *q)
> +{
> + return (q->d->device_variant == ACC100_VARIANT);
> +}
> +
> +static inline bool
> +validate_op_required(struct acc100_queue *q)
> +{
> + return is_acc100(q);
> +}
> +#endif
> +
> /* Fill in a frame control word for LDPC decoding. */
> static inline void
> acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
> @@ -2182,8 +2197,10 @@ static inline uint32_t hq_index(uint32_t offset)
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validates turbo encoder parameters */
> static inline int
> -validate_enc_op(struct rte_bbdev_enc_op *op)
> +validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
This check should be done after the variables declarations as per the
project coding style:
"
Local Variables
~~~~~~~~~~~~~~~
* Variables should be declared at the start of a block of code rather
than in the middle.
"
> struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
> struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
> struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
> @@ -2320,8 +2337,10 @@ static inline uint32_t hq_index(uint32_t offset)
> }
> /* Validates LDPC encoder parameters */
> static inline int
> -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
> +validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
> struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
>
> if (op->mempool == NULL) {
> @@ -2373,8 +2392,10 @@ static inline uint32_t hq_index(uint32_t offset)
>
> /* Validates LDPC decoder parameters */
> static inline int
> -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
> +validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
> struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
>
> if (op->mempool == NULL) {
> @@ -2429,7 +2450,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_enc_op(op) == -1) {
> + if (validate_enc_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo encoder validation failed");
> return -EINVAL;
> }
> @@ -2483,7 +2504,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_enc_op(ops[0]) == -1) {
> + if (validate_ldpc_enc_op(ops[0], q) == -1) {
> rte_bbdev_log(ERR, "LDPC encoder validation failed");
> return -EINVAL;
> }
> @@ -2545,7 +2566,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_enc_op(op) == -1) {
> + if (validate_ldpc_enc_op(op, q) == -1) {
> rte_bbdev_log(ERR, "LDPC encoder validation failed");
> return -EINVAL;
> }
> @@ -2602,7 +2623,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_enc_op(op) == -1) {
> + if (validate_enc_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo encoder validation failed");
> return -EINVAL;
> }
> @@ -2675,8 +2696,10 @@ static inline uint32_t hq_index(uint32_t offset)
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validates turbo decoder parameters */
> static inline int
> -validate_dec_op(struct rte_bbdev_dec_op *op)
> +validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
> {
> + if (!validate_op_required(q))
> + return 0;
> struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
> struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
> struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
> @@ -2822,7 +2845,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_dec_op(op) == -1) {
> + if (validate_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo decoder validation failed");
> return -EINVAL;
> }
> @@ -3047,7 +3070,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_dec_op(op) == -1) {
> + if (validate_ldpc_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "LDPC decoder validation failed");
> return -EINVAL;
> }
> @@ -3151,7 +3174,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_ldpc_dec_op(op) == -1) {
> + if (validate_ldpc_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "LDPC decoder validation failed");
> return -EINVAL;
> }
> @@ -3241,7 +3264,7 @@ static inline uint32_t hq_index(uint32_t offset)
>
> #ifdef RTE_LIBRTE_BBDEV_DEBUG
> /* Validate op structure */
> - if (validate_dec_op(op) == -1) {
> + if (validate_dec_op(op, q) == -1) {
> rte_bbdev_log(ERR, "Turbo decoder validation failed");
> return -EINVAL;
> }
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v6 4/5] baseband/acc100: modify validation code for ACC101
2022-05-31 8:02 ` Maxime Coquelin
@ 2022-05-31 18:16 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-31 18:16 UTC (permalink / raw)
To: Maxime Coquelin, dev, gakhil, trix
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Maxime,
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Tuesday, May 31, 2022 1:03 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v6 4/5] baseband/acc100: modify validation code for
> ACC101
>
>
>
> On 5/26/22 02:55, Nicolas Chautru wrote:
> > The validation requirement is different for the two devices.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > drivers/baseband/acc100/rte_acc100_pmd.c | 47
> ++++++++++++++++++++++++--------
> > 1 file changed, 35 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index 6a2123b..a057edf 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -1295,6 +1295,21 @@
> > RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> > }
> >
> > +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> > +
> > +static inline bool
> > +is_acc100(struct acc100_queue *q)
> > +{
> > + return (q->d->device_variant == ACC100_VARIANT); }
> > +
> > +static inline bool
> > +validate_op_required(struct acc100_queue *q) {
> > + return is_acc100(q);
> > +}
> > +#endif
> > +
> > /* Fill in a frame control word for LDPC decoding. */
> > static inline void
> > acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld
> > *fcw, @@ -2182,8 +2197,10 @@ static inline uint32_t hq_index(uint32_t
> offset)
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validates turbo encoder parameters */
> > static inline int
> > -validate_enc_op(struct rte_bbdev_enc_op *op)
> > +validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
>
>
> This check should be done after the variables declarations as per the project
> coding style:'
Thanks, I will update now.
>
> "
> Local Variables
> ~~~~~~~~~~~~~~~
>
> * Variables should be declared at the start of a block of code rather than in
> the middle.
> "
>
> > struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
> > struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
> > struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL; @@ -2320,8
> > +2337,10 @@ static inline uint32_t hq_index(uint32_t offset)
> > }
> > /* Validates LDPC encoder parameters */
> > static inline int
> > -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
> > +validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue
> > +*q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
> > struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
> >
> > if (op->mempool == NULL) {
> > @@ -2373,8 +2392,10 @@ static inline uint32_t hq_index(uint32_t
> > offset)
> >
> > /* Validates LDPC decoder parameters */
> > static inline int
> > -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
> > +validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue
> > +*q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
> > struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
> >
> > if (op->mempool == NULL) {
> > @@ -2429,7 +2450,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_enc_op(op) == -1) {
> > + if (validate_enc_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2483,7 +2504,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_enc_op(ops[0]) == -1) {
> > + if (validate_ldpc_enc_op(ops[0], q) == -1) {
> > rte_bbdev_log(ERR, "LDPC encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2545,7 +2566,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_enc_op(op) == -1) {
> > + if (validate_ldpc_enc_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "LDPC encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2602,7 +2623,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_enc_op(op) == -1) {
> > + if (validate_enc_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo encoder validation failed");
> > return -EINVAL;
> > }
> > @@ -2675,8 +2696,10 @@ static inline uint32_t hq_index(uint32_t offset)
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validates turbo decoder parameters */
> > static inline int
> > -validate_dec_op(struct rte_bbdev_dec_op *op)
> > +validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
> > {
> > + if (!validate_op_required(q))
> > + return 0;
> > struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
> > struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
> > struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL; @@ -2822,7
> > +2845,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_dec_op(op) == -1) {
> > + if (validate_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo decoder validation failed");
> > return -EINVAL;
> > }
> > @@ -3047,7 +3070,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_dec_op(op) == -1) {
> > + if (validate_ldpc_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "LDPC decoder validation failed");
> > return -EINVAL;
> > }
> > @@ -3151,7 +3174,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_ldpc_dec_op(op) == -1) {
> > + if (validate_ldpc_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "LDPC decoder validation failed");
> > return -EINVAL;
> > }
> > @@ -3241,7 +3264,7 @@ static inline uint32_t hq_index(uint32_t offset)
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > /* Validate op structure */
> > - if (validate_dec_op(op) == -1) {
> > + if (validate_dec_op(op, q) == -1) {
> > rte_bbdev_log(ERR, "Turbo decoder validation failed");
> > return -EINVAL;
> > }
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v5 4/5] baseband/acc100: modify validation code for ACC101
2022-05-31 7:59 ` Maxime Coquelin
@ 2022-05-31 18:19 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-31 18:19 UTC (permalink / raw)
To: Maxime Coquelin, dev, gakhil, trix
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Maxime,
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Tuesday, May 31, 2022 1:00 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v5 4/5] baseband/acc100: modify validation code for
> ACC101
>
> Hi Nicolas,
>
> On 5/26/22 00:15, Chautru, Nicolas wrote:
> >
> >
> >> -----Original Message-----
> >> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> >> Sent: Wednesday, May 25, 2022 7:33 AM
> >> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> >> gakhil@marvell.com; trix@redhat.com
> >> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> >> Richardson, Bruce <bruce.richardson@intel.com>;
> >> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> >> david.marchand@redhat.com
> >> Subject: Re: [PATCH v5 4/5] baseband/acc100: modify validation code
> >> for
> >> ACC101
> >>
> >>
> >>
> >> On 5/24/22 02:08, Nicolas Chautru wrote:
> >>> The validation requirement is different for the two devices.
> >>>
> >>> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> >>> ---
> >>> drivers/baseband/acc100/rte_acc100_pmd.c | 47
> >> ++++++++++++++++++++++++--------
> >>> 1 file changed, 35 insertions(+), 12 deletions(-)
> >>>
> >>> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> b/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> index 41475b2..e3706e0 100644
> >>> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> >>> @@ -1289,6 +1289,21 @@
> >>> RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
> >>> }
> >>>
> >>> +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> >>> +
> >>> +static inline bool
> >>> +is_acc100(struct acc100_queue *q)
> >>> +{
> >>> + return (q->d->device_variant == ACC100_VARIANT);
> >>
> >> I keep insisting, but please rely on the PCI device ID, there is no
> >> need to introduce a new field.
> >
> > Thanks. I have a couple of concerns changing this:
> > 1) the device id is not accessible from the structures currently passed by the
> functions which would rely on this. Ie. device_id is accessible from
> rte_bbdev/rte_device but not from acc100_device or acc100_queue. Would
> be convoluted to have to carry forward this structure when needed instead
> of using directly acc100_device structure.
> > 2) These call would be done as part of the workload operation where
> performance matters, best to keep the check as trivial as possible within the
> PMD.
>
> I think it is better to have a pointer to the rte_bbdev/rte_device than
> introducing a new ID.
>
> Regarding performance, is_acc100 is only defined in
> RTE_LIBRTE_BBDEV_DEBUG, so it should not be that critical.
That function is not intended to be only used for debug purpose but more generally for other handling
when the code would differ from ACC100 vs ACC101, includes future changes targeting next release.
>
> Regarding that, I have hard time to understand why we need to validate
> encoder/decoder parameters in ACC100 case, but not in ACC101 one. For
> example, I guess having a valid mempool pointer is required in both
> ACC100 and ACC101 cases.
This is due to difference in HW implementation in ACC100 and ACC101, ACC101 HW interface
would not require validation in driver of the input API.
>
> > Will aim for new patch in next few days based on the other refactory
> suggestions and unified driver.
> >
> > Thanks
> > Nic
>
> Thanks,
> Maxime
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF
2022-05-31 7:35 ` Maxime Coquelin
@ 2022-05-31 18:28 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-31 18:28 UTC (permalink / raw)
To: Maxime Coquelin, dev, gakhil, trix
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Maxime,
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Tuesday, May 31, 2022 12:36 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: Re: [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from
> PF
>
> Hi Nicolas,
>
> Thanks for doing the API change, this part looks good to me now.
> I just have one comment below that was not addressed:
>
> On 5/26/22 02:55, Nicolas Chautru wrote:
> > Adding companion function common to ACC100/ACC101 which can be
> called
> > from bbdev-test when running from PF.
> >
> > Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> > ---
> > app/test-bbdev/test_bbdev_perf.c | 6 +-
> > drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> > drivers/baseband/acc100/rte_acc100_pmd.c | 323
> ++++++++++++++++++++++++++++++-
> > drivers/baseband/acc100/version.map | 3 +-
> > 4 files changed, 327 insertions(+), 9 deletions(-)
> >
>
> ...
>
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index a057edf..86545cc 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -4574,8 +4574,8 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > }
> >
> > /* Initial configuration of a ACC100 device prior to running
> > configure() */ -int -rte_acc100_configure(const char *dev_name, struct
> > rte_acc100_conf *conf)
> > +static int
> > +acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
> > {
> > rte_bbdev_log(INFO, "rte_acc100_configure");
> > uint32_t value, address, status;
> > @@ -4975,3 +4975,322 @@ static int acc100_pci_remove(struct
> rte_pci_device *pci_dev)
> > rte_bbdev_log_debug("PF Tip configuration complete for %s",
> dev_name);
> > return 0;
> > }
> > +
> > +
> > +/* Initial configuration of a ACC101 device prior to running
> > +configure() */ static int acc101_configure(const char *dev_name,
> > +struct rte_acc100_conf *conf) {
> > + rte_bbdev_log(INFO, "rte_acc101_configure");
> > + uint32_t value, address, status;
> > + int qg_idx, template_idx, vf_idx, acc, i;
> > + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> > +
> > + /* Compile time checks */
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
> > +
> > + if (bbdev == NULL) {
> > + rte_bbdev_log(ERR,
> > + "Invalid dev_name (%s), or device is not yet initialised",
> > + dev_name);
> > + return -ENODEV;
> > + }
> > + struct acc100_device *d = bbdev->data->dev_private;
> > +
> > + /* Store configuration */
> > + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
> > +
> > + /* PCIe Bridge configuration */
> > + acc100_reg_write(d, HwPfPcieGpexBridgeControl,
> ACC101_CFG_PCI_BRIDGE);
> > + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
> > + acc100_reg_write(d,
> HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i
> > +* 16, 0);
> > +
> > + /* Prevent blocking AXI read on BRESP for AXI Write */
> > + address = HwPfPcieGpexAxiPioControl;
> > + value = ACC101_CFG_PCI_AXI;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Explicitly releasing AXI including a 2ms delay on ACC101 */
> > + usleep(2000);
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* Set the default 5GDL DMA configuration */
> > + acc100_reg_write(d, HWPfDmaInboundDrainDataSize,
> > +ACC101_DMA_INBOUND);
> > +
> > + /* Enable granular dynamic clock gating */
> > + address = HWPfHiClkGateHystReg;
> > + value = ACC101_CLOCK_GATING_EN;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Set default descriptor signature */
> > + address = HWPfDmaDescriptorSignatuture;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Enable the Error Detection in DMA */
> > + value = ACC101_CFG_DMA_ERROR;
> > + address = HWPfDmaErrorDetectionEn;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* AXI Cache configuration */
> > + value = ACC101_CFG_AXI_CACHE;
> > + address = HWPfDmaAxcacheReg;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default DMA Configuration (Qmgr Enabled) */
> > + address = HWPfDmaConfig0Reg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfDmaQmanen;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Default RLIM/ALEN configuration */
> > + address = HWPfDmaConfig1Reg;
> > + int alen_r = 0xF;
> > + int alen_w = 0x7;
> > + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configure DMA Qmanager addresses */
> > + address = HWPfDmaQmgrAddrReg;
> > + value = HWPfQmgrEgressQueuesTemplate;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* ===== Qmgr Configuration ===== */
> > + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2
> for UL */
> > + int totalQgs = conf->q_ul_4g.num_qgroups +
> > + conf->q_ul_5g.num_qgroups +
> > + conf->q_dl_4g.num_qgroups +
> > + conf->q_dl_5g.num_qgroups;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrDepthLog2Grp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = aqDepth(qg_idx, conf);
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrTholdGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Template Priority in incremental order */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg0Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg1Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_1;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg2indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_2;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg3Indx +
> ACC101_BYTES_IN_WORD * template_idx;
> > + value = ACC101_TMPL_PRI_3;
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + address = HWPfQmgrGrpPriority;
> > + value = ACC101_CFG_QMGR_HI_P;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Template Configuration */
> > + for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
> > + template_idx++) {
> > + value = 0;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 4GUL */
> > + int numQgs = conf->q_ul_4g.num_qgroups;
> > + int numQqsAcc = 0;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_4G;
> > + template_idx <= ACC101_SIG_UL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value);
> > + }
> > + /* 5GUL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_ul_5g.num_qgroups;
> > + value = 0;
> > + int numEngines = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_UL_5G;
> > + template_idx <= ACC101_SIG_UL_5G_LAST;
> > + template_idx++) {
> > + /* Check engine power-on status */
> > + address = HwPfFecUl5gIbDebugReg +
> > + ACC101_ENGINE_OFFSET * template_idx;
> > + status = (acc100_reg_read(d, address) >> 4) & 0xF;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + if (status == 1) {
> > + acc100_reg_write(d, address, value);
> > + numEngines++;
> > + } else
> > + acc100_reg_write(d, address, 0);
> > +#if RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > + printf("Number of 5GUL engines %d\n", numEngines);
> > + /* 4GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_4g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_4G;
> > + template_idx <= ACC101_SIG_DL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value); #if
> RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
>
> As I mentionned on previous revision, single FEC case should be handled via
> a devarg, so that testing both cases do not require a rebuild.
This is already done like this in ACC100 and is meant to be a build time parameter.
Still I will take it out of the commit to avoid any confusion.
Thanks
>
> > + }
> > + /* 5GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_5g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC101_SIG_DL_5G;
> > + template_idx <= ACC101_SIG_DL_5G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC101_BYTES_IN_WORD * template_idx;
> > + acc100_reg_write(d, address, value); #if
> RTE_ACC101_SINGLE_FEC == 1
> > + value = 0;
> > +#endif
> > + }
> > +
> > + /* Queue Group Function mapping */
> > + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> > + address = HWPfQmgrGrpFunction0;
> > + value = 0;
> > + for (qg_idx = 0; qg_idx < 8; qg_idx++) {
> > + acc = accFromQgid(qg_idx, conf);
> > + value |= qman_func_id[acc]<<(qg_idx * 4);
> > + }
> > + acc100_reg_write(d, address, value);
> > +
> > + /* Configuration of the Arbitration QGroup depth to 1 */
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + address = HWPfQmgrArbQDepthGrp +
> > + ACC101_BYTES_IN_WORD * qg_idx;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + }
> > +
> > + /* Enabling AQueues through the Queue hierarchy*/
> > + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
> > + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
> > + value = 0;
> > + if (vf_idx < conf->num_vf_bundles &&
> > + qg_idx < totalQgs)
> > + value = (1 << aqNum(qg_idx, conf)) - 1;
> > + address = HWPfQmgrAqEnableVf
> > + + vf_idx * ACC101_BYTES_IN_WORD;
> > + value += (qg_idx << 16);
> > + acc100_reg_write(d, address, value);
> > + }
> > + }
> > +
> > + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
> > + uint32_t aram_address = 0;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfQmgrVfBaseAddr + vf_idx
> > + * ACC101_BYTES_IN_WORD + qg_idx
> > + * ACC101_BYTES_IN_WORD * 64;
> > + value = aram_address;
> > + acc100_reg_write(d, address, value);
> > + /* Offset ARAM Address for next memory bank
> > + * - increment of 4B
> > + */
> > + aram_address += aqNum(qg_idx, conf) *
> > + (1 << aqDepth(qg_idx, conf));
> > + }
> > + }
> > +
> > + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
> > + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d
> %d\n",
> > + aram_address,
> ACC101_WORDS_IN_ARAM_SIZE);
> > + return -EINVAL;
> > + }
> > +
> > + /* ==== HI Configuration ==== */
> > +
> > + /* No Info Ring/MSI by default */
> > + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
> > + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
> > + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
> > + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
> > + /* Prevent Block on Transmit Error */
> > + address = HWPfHiBlockTransmitOnErrorEn;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Prevents to drop MSI */
> > + address = HWPfHiMsiDropEnableReg;
> > + value = 0;
> > + acc100_reg_write(d, address, value);
> > + /* Set the PF Mode register */
> > + address = HWPfHiPfMode;
> > + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
> > + acc100_reg_write(d, address, value);
> > + /* Explicitly releasing AXI after PF Mode and 2 ms */
> > + usleep(2000);
> > + acc100_reg_write(d, HWPfDmaAxiControl, 1);
> > +
> > + /* QoS overflow init */
> > + value = 1;
> > + address = HWPfQosmonAEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > + address = HWPfQosmonBEvalOverflow0;
> > + acc100_reg_write(d, address, value);
> > +
> > + /* HARQ DDR Configuration */
> > + unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfDmaVfDdrBaseRw + vf_idx
> > + * 0x10;
> > + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
> > + (ddrSizeInMb - 1);
> > + acc100_reg_write(d, address, value);
> > + }
> > + usleep(ACC101_LONG_WAIT);
> > +
> > + rte_bbdev_log_debug("PF TIP configuration complete for %s",
> dev_name);
> > + return 0;
> > +}
> > +
> > +int
> > +rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf
> > +*conf) {
> > + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> > + if (bbdev == NULL) {
> > + rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not
> yet initialised",
> > + dev_name);
> > + return -ENODEV;
> > + }
> > + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
> > + printf("Configure dev id %x\n", pci_dev->id.device_id);
> > + if (pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID)
> > + return acc100_configure(dev_name, conf);
> > + else
> > + return acc101_configure(dev_name, conf); }
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101
2022-05-30 7:40 ` [EXT] " Akhil Goyal
@ 2022-05-31 18:59 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-05-31 18:59 UTC (permalink / raw)
To: Akhil Goyal, dev, trix, maxime.coquelin
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Akhil,
> -----Original Message-----
> From: Akhil Goyal <gakhil@marvell.com>
> Sent: Monday, May 30, 2022 12:40 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> trix@redhat.com; maxime.coquelin@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com
> Subject: RE: [EXT] [PATCH v6 3/5] baseband/acc100: introduce PMD for
> ACC101
>
> >
> >
> > Enable Virtual Functions
> > @@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and
> > other settings necessary for the device to perform FEC functions.
> >
> > This configuration needs to be executed at least once after reboot or
> > PCI FLR and can -be achieved by using the function
> > ``acc100_configure()``, which sets up the -parameters defined in
> > ``acc100_conf`` structure.
> > +be achieved by using the functions ``acc100_configure()`` or
> > ``acc101_configure()``,
>
> I believe the API for user is common now. Right? So why to have two
> references?
Thanks, I will amend the documentation now.
>
> > +which sets up the parameters defined in the compatible
> > +``acc100_conf``
> > structure.
> >
> > Test Application
> > ----------------
> >
> > BBDEV provides a test application, ``test-bbdev.py`` and range of
> > test data for testing -the functionality of ACC100 5G/4G FEC encode
> > and decode, depending on the device's
> > +the functionality of the device 5G/4G FEC encode and decode,
> > +depending on
> > the device's
> > capabilities. The test application is located under app->test-bbdev
> > folder and has the following options:
> >
> > @@ -212,7 +217,7 @@ Test Vectors
> >
> > In addition to the simple LDPC decoder and LDPC encoder tests, bbdev
> > also provides a range of additional tests under the test_vectors
> > folder, which may be useful.
> > The results
> > -of these tests will depend on the ACC100 5G/4G FEC capabilities which
> > may cause some
> > +of these tests will depend on the device 5G/4G FEC capabilities which
> > +may
> > cause some
> > testcases to be skipped, but no failure should be reported.
> >
> >
> > @@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the
> > command below can be used:
> >
> > ./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg
> > ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64
> > -b 32 -l 1 -v ./ldpc_dec_default.data
> > +
> > +Specifically for the BBDEV ACC101 PMD, the command below can be used:
> > +
> > +.. code-block:: console
> > +
> > + ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg
> > + ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64
> > + -b 32 -l 1 -
> > v ./ldpc_dec_default.data
> > +
> > diff --git a/doc/guides/bbdevs/features/acc101.ini
> > b/doc/guides/bbdevs/features/acc101.ini
> > new file mode 100644
> > index 0000000..0e2c21a
> > --- /dev/null
> > +++ b/doc/guides/bbdevs/features/acc101.ini
> > @@ -0,0 +1,13 @@
> > +;
> > +; Supported features of the 'acc101' bbdev driver.
> > +;
> > +; Refer to default.ini for the full list of available PMD features.
> > +;
> > +[Features]
> > +Turbo Decoder (4G) = Y
> > +Turbo Encoder (4G) = Y
> > +LDPC Decoder (5G) = Y
> > +LDPC Encoder (5G) = Y
> > +LLR/HARQ Compression = Y
> > +External DDR Access = Y
> > +HW Accelerated = Y
> > diff --git a/doc/guides/rel_notes/release_22_07.rst
> > b/doc/guides/rel_notes/release_22_07.rst
> > index e49cace..1803947 100644
> > --- a/doc/guides/rel_notes/release_22_07.rst
> > +++ b/doc/guides/rel_notes/release_22_07.rst
> > @@ -104,6 +104,9 @@ New Features
> > * ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
> > * ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
> >
> > +* **Added Intel ACC101 baseband PMD.**
> > +
> > + * Added a new baseband PMD for Intel ACC101 device.
> >
> > Removed Items
> > -------------
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c
> > b/drivers/baseband/acc100/rte_acc100_pmd.c
> > index 3fdf17d..6a2123b 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> > @@ -22,6 +22,7 @@
> > #include <rte_bbdev.h>
> > #include <rte_bbdev_pmd.h>
> > #include "rte_acc100_pmd.h"
> > +#include "rte_acc101_pmd.h"
> >
> > #ifdef RTE_LIBRTE_BBDEV_DEBUG
> > RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); @@ -1133,7
> +1134,10
> > @@
> > /* ACC100 PCI PF address map */
> > static struct rte_pci_id pci_id_acc100_pf_map[] = {
> > {
> > - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> > RTE_ACC100_PF_DEVICE_ID)
> > + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> > RTE_ACC100_PF_DEVICE_ID),
> > + },
> > + {
> > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> > RTE_ACC101_PF_DEVICE_ID),
> > },
> > {.device_id = 0},
> > };
> > @@ -1141,7 +1145,10 @@
> > /* ACC100 PCI VF address map */
> > static struct rte_pci_id pci_id_acc100_vf_map[] = {
> > {
> > - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> > RTE_ACC100_VF_DEVICE_ID)
> > + RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID,
> > RTE_ACC100_VF_DEVICE_ID),
> > + },
> > + {
> > + RTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID,
> > RTE_ACC101_VF_DEVICE_ID),
> > },
> > {.device_id = 0},
> > };
> > @@ -1290,7 +1297,7 @@
> >
> > /* Fill in a frame control word for LDPC decoding. */ static inline
> > void -acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct
> > acc100_fcw_ld *fcw,
> > +acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld
> > +*fcw,
> > union acc100_harq_layout_data *harq_layout) {
> > uint16_t harq_out_length, harq_in_length, ncb_p, k0_p,
> > parity_offset; @@ -1414,6 +1421,128 @@
> > }
> > }
> >
> > +/* Convert offset to harq index for harq_layout structure */ static
> > +inline uint32_t hq_index(uint32_t offset) {
> > + return (offset >> ACC100_HARQ_OFFSET_SHIFT) &
> > ACC100_HARQ_OFFSET_MASK;
> > +}
> > +
> > +/* Fill in a frame control word for LDPC decoding for ACC101 */
> > +static inline void acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op,
> > +struct acc100_fcw_ld *fcw,
> > + union acc100_harq_layout_data *harq_layout) {
> > + uint16_t harq_out_length, harq_in_length, ncb_p, k0_p,
> parity_offset;
> > + uint32_t harq_index;
> > + uint32_t l;
> > +
> > + fcw->qm = op->ldpc_dec.q_m;
> > + fcw->nfiller = op->ldpc_dec.n_filler;
> > + fcw->BG = (op->ldpc_dec.basegraph - 1);
> > + fcw->Zc = op->ldpc_dec.z_c;
> > + fcw->ncb = op->ldpc_dec.n_cb;
> > + fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
> > + op->ldpc_dec.rv_index);
> > + if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
> > + fcw->rm_e = op->ldpc_dec.cb_params.e;
> > + else
> > + fcw->rm_e = (op->ldpc_dec.tb_params.r <
> > + op->ldpc_dec.tb_params.cab) ?
> > + op->ldpc_dec.tb_params.ea :
> > + op->ldpc_dec.tb_params.eb;
> > +
> > + if (unlikely(check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
> > + (op->ldpc_dec.harq_combined_input.length == 0))) {
> > + rte_bbdev_log(WARNING, "Null HARQ input size provided");
> > + /* Disable HARQ input in that case to carry forward */
> > + op->ldpc_dec.op_flags ^=
> > RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
> > + }
> > +
> > + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
> > + fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
> > + fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
> > + fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_DECODE_BYPASS);
> > + fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
> > + if (op->ldpc_dec.q_m == 1) {
> > + fcw->bypass_intlv = 1;
> > + fcw->qm = 2;
> > + }
> > + fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> > + fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
> > + fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_LLR_COMPRESSION);
> > + harq_index = hq_index(op-
> >ldpc_dec.harq_combined_output.offset);
> > + if (fcw->hcin_en > 0) {
> > + harq_in_length = op-
> >ldpc_dec.harq_combined_input.length;
> > + if (fcw->hcin_decomp_mode > 0)
> > + harq_in_length = harq_in_length * 8 / 6;
> > + harq_in_length = RTE_MIN(harq_in_length, op-
> >ldpc_dec.n_cb
> > + - op->ldpc_dec.n_filler);
> > + /* Alignment on next 64B - Already enforced from HC output
> */
> > + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
> > + fcw->hcin_size0 = harq_in_length;
> > + fcw->hcin_offset = 0;
> > + fcw->hcin_size1 = 0;
> > + } else {
> > + fcw->hcin_size0 = 0;
> > + fcw->hcin_offset = 0;
> > + fcw->hcin_size1 = 0;
> > + }
> > +
> > + fcw->itmax = op->ldpc_dec.iter_max;
> > + fcw->itstop = check_bit(op->ldpc_dec.op_flags,
> > + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
> > + fcw->synd_precoder = fcw->itstop;
> > + /*
> > + * These are all implicitly set
> > + * fcw->synd_post = 0;
> > + * fcw->so_en = 0;
> > + * fcw->so_bypass_rm = 0;
> > + * fcw->so_bypass_intlv = 0;
> > + * fcw->dec_convllr = 0;
> > + * fcw->hcout_convllr = 0;
> > + * fcw->hcout_size1 = 0;
> > + * fcw->so_it = 0;
> > + * fcw->hcout_offset = 0;
> > + * fcw->negstop_th = 0;
> > + * fcw->negstop_it = 0;
> > + * fcw->negstop_en = 0;
> > + * fcw->gain_i = 1;
> > + * fcw->gain_h = 1;
> > + */
> > + if (fcw->hcout_en > 0) {
> > + parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
> > + * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
> > + k0_p = (fcw->k0 > parity_offset) ?
> > + fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
> > + ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
> > + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
> > + harq_out_length = (uint16_t) fcw->hcin_size0;
> > + harq_out_length = RTE_MAX(harq_out_length, l);
> > + /* Cannot exceed the pruned Ncb circular buffer */
> > + harq_out_length = RTE_MIN(harq_out_length, ncb_p);
> > + /* Alignment on next 64B */
> > + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
> > + fcw->hcout_size0 = harq_out_length;
> > + fcw->hcout_size1 = 0;
> > + fcw->hcout_offset = 0;
> > + harq_layout[harq_index].offset = fcw->hcout_offset;
> > + harq_layout[harq_index].size0 = fcw->hcout_size0;
> > + } else {
> > + fcw->hcout_size0 = 0;
> > + fcw->hcout_size1 = 0;
> > + fcw->hcout_offset = 0;
> > + }
> > +}
> > +
> > /**
> > * Fills descriptor with data pointers of one block type.
> > *
> > @@ -2966,7 +3095,7 @@
> > struct acc100_fcw_ld *fcw;
> > uint32_t seg_total_left;
> > fcw = &desc->req.fcw_ld;
> > - acc100_fcw_ld_fill(op, fcw, harq_layout);
> > + q->d->fcw_ld_fill(op, fcw, harq_layout);
> >
> > /* Special handling when overusing mbuf */
> > if (fcw->rm_e < ACC100_MAX_E_MBUF)
> > @@ -3033,7 +3162,7 @@
> > desc = q->ring_addr + desc_idx;
> > uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
> > union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
> > - acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
> > + q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
> >
> > input = op->ldpc_dec.input.data;
> > h_output_head = h_output = op->ldpc_dec.hard_output.data; @@ -
> 4145,9
> > +4274,19 @@
> > dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
> > dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
> >
> > + /* Device variant specific handling */
> > + if ((pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID) ||
> > + (pci_dev->id.device_id ==
> RTE_ACC100_VF_DEVICE_ID))
> > {
> > + ((struct acc100_device *) dev->data->dev_private)-
> > >device_variant = ACC100_VARIANT;
> > + ((struct acc100_device *) dev->data->dev_private)-
> >fcw_ld_fill
> > = acc100_fcw_ld_fill;
> > + } else {
> > + ((struct acc100_device *) dev->data->dev_private)-
> > >device_variant = ACC101_VARIANT;
> > + ((struct acc100_device *) dev->data->dev_private)-
> >fcw_ld_fill
> > = acc101_fcw_ld_fill;
> > + }
> > +
> > ((struct acc100_device *) dev->data->dev_private)->pf_device =
> > - !strcmp(drv->driver.name,
> > - RTE_STR(ACC100PF_DRIVER_NAME));
> > + !strcmp(drv->driver.name,
> > RTE_STR(ACC100PF_DRIVER_NAME));
> > +
> > ((struct acc100_device *) dev->data->dev_private)->mmio_base =
> > pci_dev->mem_resource[0].addr;
> >
> > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h
> > b/drivers/baseband/acc100/rte_acc100_pmd.h
> > index 8fea322..39d5f22 100644
> > --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> > +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> > @@ -22,6 +22,9 @@
> > #define rte_bbdev_log_debug(fmt, ...) #endif
> >
> > +#define ACC100_VARIANT 0
> > +#define ACC101_VARIANT 1
>
> Since you are using PCI dev id for identifying the device. Do we still need
> above defines?
The implementation is_acc100() is based on checking that enum
(q->d->device_variant == ACC100_VARIANT);
> > +
> > /* ACC100 PF and VF driver names */
> > #define ACC100PF_DRIVER_NAME intel_acc100_pf
> > #define ACC100VF_DRIVER_NAME intel_acc100_vf
> > @@ -67,6 +70,8 @@
> > #define ACC100_HARQ_LAYOUT (64*1024*1024)
> > /* Assume offset for HARQ in memory */
> > #define ACC100_HARQ_OFFSET (32*1024)
> > +#define ACC100_HARQ_OFFSET_SHIFT 15
> > +#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
> > /* Mask used to calculate an index in an Info Ring array (not a byte offset)
> */
> > #define ACC100_INFO_RING_MASK
> (ACC100_INFO_RING_NUM_ENTRIES-
> > 1)
> > /* Number of Virtual Functions ACC100 supports */ @@ -574,6 +579,10
> > @@ struct __rte_cache_aligned acc100_queue {
> > struct acc100_device *d;
> > };
> >
> > +typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,
> > + struct acc100_fcw_ld *fcw,
> > + union acc100_harq_layout_data *harq_layout);
> > +
> > /* Private data structure for each ACC100 device */ struct
> > acc100_device {
> > void *mmio_base; /**< Base address of MMIO registers (BAR0) */
> @@
> > -605,6 +614,8 @@ struct acc100_device {
> > uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
> > bool pf_device; /**< True if this is a PF ACC100 device */
> > bool configured; /**< True if this ACC100 device is configured */
> > + uint16_t device_variant; /**< Device variant */
> > + acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation
> > function */
> > };
> >
> > /**
> > diff --git a/drivers/baseband/acc100/rte_acc101_pmd.h
> > b/drivers/baseband/acc100/rte_acc101_pmd.h
> > new file mode 100644
> > index 0000000..8f1f4ab
> > --- /dev/null
> > +++ b/drivers/baseband/acc100/rte_acc101_pmd.h
>
> This file is internal, shouldn't we drop the rte?
There is lack of consistency on the filenaming really historically, still will update the new file. Thanks
>
>
> > @@ -0,0 +1,55 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2022 Intel Corporation */
> > +
> > +/* ACC101 PCI vendor & device IDs */
> > +#define RTE_ACC101_VENDOR_ID (0x8086)
> > +#define RTE_ACC101_PF_DEVICE_ID (0x57c4)
> > +#define RTE_ACC101_VF_DEVICE_ID (0x57c5)
> > +
> > +/* Define as 1 to use only a single FEC engine */ #ifndef
> > +RTE_ACC101_SINGLE_FEC #define RTE_ACC101_SINGLE_FEC 0 #endif
>
> Also the above defines should drop RTE if they are internal symbols.
This is historical as well but will update on current code first with additional commit.
Thanks
>
> > +
> > +/* Number of Virtual Functions ACC101 supports */
> > +#define ACC101_NUM_VFS 16
> > +#define ACC101_NUM_QGRPS 8
> > +#define ACC101_NUM_AQS 16
> > +/* All ACC101 Registers alignment are 32bits = 4B */
> > +#define ACC101_BYTES_IN_WORD 4
> > +
> > +#define ACC101_TMPL_PRI_0 0x03020100
> > +#define ACC101_TMPL_PRI_1 0x07060504
> > +#define ACC101_TMPL_PRI_2 0x0b0a0908
> > +#define ACC101_TMPL_PRI_3 0x0f0e0d0c
> > +#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
> > +
> > +#define ACC101_NUM_TMPL 32
> > +/* Mapping of signals for the available engines */
> > +#define ACC101_SIG_UL_5G 0
> > +#define ACC101_SIG_UL_5G_LAST 8
> > +#define ACC101_SIG_DL_5G 13
> > +#define ACC101_SIG_DL_5G_LAST 15
> > +#define ACC101_SIG_UL_4G 16
> > +#define ACC101_SIG_UL_4G_LAST 19
> > +#define ACC101_SIG_DL_4G 27
> > +#define ACC101_SIG_DL_4G_LAST 31
> > +#define ACC101_NUM_ACCS 5
> > +#define ACC101_PF_VAL 2
> > +
> > +/* ACC101 Configuration */
> > +#define ACC101_CFG_DMA_ERROR 0x3D7
> > +#define ACC101_CFG_AXI_CACHE 0x11
> > +#define ACC101_CFG_QMGR_HI_P 0x0F0F
> > +#define ACC101_CFG_PCI_AXI 0xC003
> > +#define ACC101_CFG_PCI_BRIDGE 0x40006033
> > +#define ACC101_ENGINE_OFFSET 0x1000
> > +#define ACC101_LONG_WAIT 1000
> > +#define ACC101_GPEX_AXIMAP_NUM 17
> > +#define ACC101_CLOCK_GATING_EN 0x30000
> > +#define ACC101_DMA_INBOUND 0x104
> > +/* DDR Size per VF - 512MB by default
> > + * Can be increased up to 4 GB with single PF/VF */
> > +#define ACC101_HARQ_DDR (512 * 1)
> > --
> > 1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (6 preceding siblings ...)
2022-05-26 0:55 ` Nicolas Chautru
@ 2022-05-31 22:31 ` Nicolas Chautru
2022-05-31 22:31 ` [PATCH v7 1/6] baseband/acc100: update companion PF configure function Nicolas Chautru
` (7 more replies)
7 siblings, 8 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-31 22:31 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
v7: updates suggested by Akhil and Maxime. Removed RTE prefix for internal #define, removed
build-time single FEC engine configuration mode, documentation fix, coding guideline fix, renamed new file without rte prefix.
v6: use formally an unified driver for AC100 and AC101. Exposing single unified function for the PF device configuration used by bbdev-test.
v5: minor fix to doc and intermediate commit caught in CI
v4: incremental updates based on reviews Changed order of patchset to include two ACC100 specific commits first: updating formally the companion configure function from PF and the protection adjustment.
Then next 3 commits for the actual changes specific to ACC101: the device specific function for FCW 5GUL generation used as a local function, combined documentations into a single .rst common to both devices, updated comments, removed unused #defines.
v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section calling the configure companion function for ACC100/101, taking the Pmon commit out which is not directly required.
v2: Based on good feedback from Thomas and David, now implementing the ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to have different behaviour based on variant.
This prevents code duplication and only rely on different functions and behaviour when hardware requires or support differences.
Note that these are pending changes for ACC100 which would be specific to that device and not ACC101 but these can be managed based on the new implementation, ie. is_acc100() etc... (such incremental changes for ACC100 trending 22.11 but confirming this is future proof).
The serie also includes commits which were meant for ACC101 but are also valuable for ACC100.
v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount Cirrus).
This is a derivative from previous Mount Bryce ACC100 which includes silicon improvement, bug fixes, capacity improvement for 5GNR and feature improvement.
Nicolas Chautru (6):
baseband/acc100: update companion PF configure function
baseband/acc100: add protection for some negative scenario
baseband/acc100: remove RTE prefix for internal macro
baseband/acc100: introduce PMD for ACC101
baseband/acc100: modify validation code for ACC101
baseband/acc100: configuration of ACC101 from PF
MAINTAINERS | 1 +
app/test-bbdev/test_bbdev_perf.c | 6 +-
doc/guides/bbdevs/acc100.rst | 37 +-
doc/guides/bbdevs/features/acc101.ini | 13 +
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/acc100_pf_enum.h | 18 +
drivers/baseband/acc100/acc101_pmd.h | 50 +++
drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
drivers/baseband/acc100/rte_acc100_pmd.c | 687 ++++++++++++++++++++++++++++---
drivers/baseband/acc100/rte_acc100_pmd.h | 37 +-
drivers/baseband/acc100/version.map | 3 +-
11 files changed, 768 insertions(+), 91 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/acc101_pmd.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v7 1/6] baseband/acc100: update companion PF configure function
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
@ 2022-05-31 22:31 ` Nicolas Chautru
2022-06-02 9:49 ` Kevin Traynor
2022-06-03 20:25 ` Vargas, Hernan
2022-05-31 22:31 ` [PATCH v7 2/6] baseband/acc100: add protection for some negative scenario Nicolas Chautru
` (6 subsequent siblings)
7 siblings, 2 replies; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-31 22:31 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Update of the device configuration function from PF used for bbdev-test
to latest sequence for ACC199 PRQ device and matching version in
pf_bb_config 22.03.
Fixes: b17d70922d5d ("baseband/acc100: add configure function")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++
drivers/baseband/acc100/rte_acc100_pmd.c | 163 +++++++++++++++++++++++--------
drivers/baseband/acc100/rte_acc100_pmd.h | 20 +++-
3 files changed, 153 insertions(+), 48 deletions(-)
diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h
index a1ee416..2fba667 100644
--- a/drivers/baseband/acc100/acc100_pf_enum.h
+++ b/drivers/baseband/acc100/acc100_pf_enum.h
@@ -238,6 +238,24 @@ enum {
HWPfPermonBTotalLatLowBusMon = 0x00BAC504,
HWPfPermonBTotalLatUpperBusMon = 0x00BAC508,
HWPfPermonBTotalReqCntBusMon = 0x00BAC50C,
+ HwPfFabI2MArbCntrlReg = 0x00BB0000,
+ HWPfFabricMode = 0x00BB1000,
+ HwPfFabI2MGrp0DebugReg = 0x00BBF000,
+ HwPfFabI2MGrp1DebugReg = 0x00BBF004,
+ HwPfFabI2MGrp2DebugReg = 0x00BBF008,
+ HwPfFabI2MGrp3DebugReg = 0x00BBF00C,
+ HwPfFabI2MBuf0DebugReg = 0x00BBF010,
+ HwPfFabI2MBuf1DebugReg = 0x00BBF014,
+ HwPfFabI2MBuf2DebugReg = 0x00BBF018,
+ HwPfFabI2MBuf3DebugReg = 0x00BBF01C,
+ HwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020,
+ HwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024,
+ HwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028,
+ HwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C,
+ HwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030,
+ HwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034,
+ HwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038,
+ HwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C,
HWPfFecUl5gCntrlReg = 0x00BC0000,
HWPfFecUl5gI2MThreshReg = 0x00BC0004,
HWPfFecUl5gVersionReg = 0x00BC0100,
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index de7e4bc..79bee43 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -141,8 +141,8 @@
int acc_enum = accFromQgid(qg_idx, acc100_conf);
qtopFromAcc(&q_top, acc_enum, acc100_conf);
if (unlikely(q_top == NULL))
- return 0;
- return q_top->aq_depth_log2;
+ return 1;
+ return RTE_MAX(1, q_top->aq_depth_log2);
}
/* Return the AQ depth for a Queue Group Index */
@@ -4411,7 +4411,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
{
rte_bbdev_log(INFO, "rte_acc100_configure");
uint32_t value, address, status;
- int qg_idx, template_idx, vf_idx, acc, i;
+ int qg_idx, template_idx, vf_idx, acc, i, j;
struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
/* Compile time checks */
@@ -4431,6 +4431,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* Store configuration */
rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+ value = acc100_reg_read(d, HwPfPcieGpexBridgeControl);
+ bool firstCfg = (value != ACC100_CFG_PCI_BRIDGE);
+
/* PCIe Bridge configuration */
acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE);
for (i = 1; i < ACC100_GPEX_AXIMAP_NUM; i++)
@@ -4451,20 +4454,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = 1;
acc100_reg_write(d, address, value);
- /* DDR Configuration */
- address = HWPfDdrBcTim6;
- value = acc100_reg_read(d, address);
- value &= 0xFFFFFFFB; /* Bit 2 */
-#ifdef ACC100_DDR_ECC_ENABLE
- value |= 0x4;
-#endif
- acc100_reg_write(d, address, value);
- address = HWPfDdrPhyDqsCountNum;
-#ifdef ACC100_DDR_ECC_ENABLE
- value = 9;
-#else
- value = 8;
-#endif
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC100_CLOCK_GATING_EN;
acc100_reg_write(d, address, value);
/* Set default descriptor signature */
@@ -4482,6 +4474,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfDmaAxcacheReg;
acc100_reg_write(d, address, value);
+ /* Adjust PCIe Lane adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ for (j = 0; j < ACC100_LANES_PER_QUAD; j++)
+ acc100_reg_write(d, HwPfPcieLnAdaptctrl + i * ACC100_PCIE_QUAD_OFFSET
+ + j * ACC100_PCIE_LANE_OFFSET, ACC100_ADAPT);
+
+ /* Enable PCIe live adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ acc100_reg_write(d, HwPfPciePcsEqControl +
+ i * ACC100_PCIE_QUAD_OFFSET, ACC100_PCS_EQ);
+
/* Default DMA Configuration (Qmgr Enabled) */
address = HWPfDmaConfig0Reg;
value = 0;
@@ -4500,6 +4503,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = HWPfQmgrEgressQueuesTemplate;
acc100_reg_write(d, address, value);
+ /* Default Fabric Mode */
+ address = HWPfFabricMode;
+ value = ACC100_FABRIC_MODE;
+ acc100_reg_write(d, address, value);
+
/* ===== Qmgr Configuration ===== */
/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
int totalQgs = conf->q_ul_4g.num_qgroups +
@@ -4518,22 +4526,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Template Priority in incremental order */
- for (template_idx = 0; template_idx < ACC100_NUM_TMPL;
- template_idx++) {
- address = HWPfQmgrGrpTmplateReg0Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ for (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_0;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg1Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_1;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg2indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_2;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg3Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC100_BYTES_IN_WORD * template_idx;
value = ACC100_TMPL_PRI_3;
acc100_reg_write(d, address, value);
}
@@ -4584,9 +4587,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
numEngines++;
} else
acc100_reg_write(d, address, 0);
-#if RTE_ACC100_SINGLE_FEC == 1
- value = 0;
-#endif
}
printf("Number of 5GUL engines %d\n", numEngines);
/* 4GDL */
@@ -4601,9 +4601,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfQmgrGrpTmplateReg4Indx
+ ACC100_BYTES_IN_WORD * template_idx;
acc100_reg_write(d, address, value);
-#if RTE_ACC100_SINGLE_FEC == 1
- value = 0;
-#endif
}
/* 5GDL */
numQqsAcc += numQgs;
@@ -4617,13 +4614,10 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfQmgrGrpTmplateReg4Indx
+ ACC100_BYTES_IN_WORD * template_idx;
acc100_reg_write(d, address, value);
-#if RTE_ACC100_SINGLE_FEC == 1
- value = 0;
-#endif
}
/* Queue Group Function mapping */
- int qman_func_id[5] = {0, 2, 1, 3, 4};
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
address = HWPfQmgrGrpFunction0;
value = 0;
for (qg_idx = 0; qg_idx < 8; qg_idx++) {
@@ -4654,7 +4648,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
}
- /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
uint32_t aram_address = 0;
for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
@@ -4679,6 +4673,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* ==== HI Configuration ==== */
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
/* Prevent Block on Transmit Error */
address = HWPfHiBlockTransmitOnErrorEn;
value = 0;
@@ -4691,10 +4690,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfHiPfMode;
value = (conf->pf_mode_en) ? ACC100_PF_VAL : 0;
acc100_reg_write(d, address, value);
- /* Enable Error Detection in HW */
- address = HWPfDmaErrorDetectionEn;
- value = 0x3D7;
- acc100_reg_write(d, address, value);
/* QoS overflow init */
value = 1;
@@ -4704,7 +4699,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
acc100_reg_write(d, address, value);
/* HARQ DDR Configuration */
- unsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */
+ unsigned int ddrSizeInMb = ACC100_HARQ_DDR;
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
address = HWPfDmaVfDdrBaseRw + vf_idx
* 0x10;
@@ -4718,6 +4713,88 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
if (numEngines < (ACC100_SIG_UL_5G_LAST + 1))
poweron_cleanup(bbdev, d, conf);
+ uint32_t version = 0;
+ for (i = 0; i < 4; i++)
+ version += acc100_reg_read(d,
+ HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
+ if (version != ACC100_PRQ_DDR_VER) {
+ printf("* Note: Not on DDR PRQ version %8x != %08x\n",
+ version, ACC100_PRQ_DDR_VER);
+ } else if (firstCfg) {
+ /* ---- DDR configuration at boot up --- */
+ /* Read Clear Ddr training status */
+ acc100_reg_read(d, HWPfChaDdrStDoneStatus);
+ /* Reset PHY/IDTM/UMMC */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 2);
+ usleep(ACC100_MS_IN_US);
+ /* Reset WB and APB resets */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 3);
+ /* Configure PHY-IDTM */
+ acc100_reg_write(d, HWPfDdrPhyIdletimeout, 0x3e8);
+ /* IDTM timing registers */
+ acc100_reg_write(d, HWPfDdrPhyRdLatency, 0x13);
+ acc100_reg_write(d, HWPfDdrPhyRdLatencyDbi, 0x15);
+ acc100_reg_write(d, HWPfDdrPhyWrLatency, 0x10011);
+ /* Configure SDRAM MRS registers */
+ acc100_reg_write(d, HWPfDdrPhyMr01Dimm, 0x3030b70);
+ acc100_reg_write(d, HWPfDdrPhyMr01DimmDbi, 0x3030b50);
+ acc100_reg_write(d, HWPfDdrPhyMr23Dimm, 0x30);
+ acc100_reg_write(d, HWPfDdrPhyMr67Dimm, 0xc00);
+ acc100_reg_write(d, HWPfDdrPhyMr45Dimm, 0x4000000);
+ /* Configure active lanes */
+ acc100_reg_write(d, HWPfDdrPhyDqsCountMax, 0x9);
+ acc100_reg_write(d, HWPfDdrPhyDqsCountNum, 0x9);
+ /* Configure WR/RD leveling timing registers */
+ acc100_reg_write(d, HWPfDdrPhyWrlvlWwRdlvlRr, 0x101212);
+ /* Configure what trainings to execute */
+ acc100_reg_write(d, HWPfDdrPhyTrngType, 0x2d3c);
+ /* Releasing PHY reset */
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 3);
+ /* Configure Memory Controller registers */
+ acc100_reg_write(d, HWPfDdrMemInitPhyTrng0, 0x3);
+ acc100_reg_write(d, HWPfDdrBcDram, 0x3c232003);
+ acc100_reg_write(d, HWPfDdrBcAddrMap, 0x31);
+ /* Configure UMMC BC timing registers */
+ acc100_reg_write(d, HWPfDdrBcRef, 0xa22);
+ acc100_reg_write(d, HWPfDdrBcTim0, 0x4050501);
+ acc100_reg_write(d, HWPfDdrBcTim1, 0xf0b0476);
+ acc100_reg_write(d, HWPfDdrBcTim2, 0x103);
+ acc100_reg_write(d, HWPfDdrBcTim3, 0x144050a1);
+ acc100_reg_write(d, HWPfDdrBcTim4, 0x23300);
+ acc100_reg_write(d, HWPfDdrBcTim5, 0x4230276);
+ acc100_reg_write(d, HWPfDdrBcTim6, 0x857914);
+ acc100_reg_write(d, HWPfDdrBcTim7, 0x79100232);
+ acc100_reg_write(d, HWPfDdrBcTim8, 0x100007ce);
+ acc100_reg_write(d, HWPfDdrBcTim9, 0x50020);
+ acc100_reg_write(d, HWPfDdrBcTim10, 0x40ee);
+ /* Configure UMMC DFI timing registers */
+ acc100_reg_write(d, HWPfDdrDfiInit, 0x5000);
+ acc100_reg_write(d, HWPfDdrDfiTim0, 0x15030006);
+ acc100_reg_write(d, HWPfDdrDfiTim1, 0x11305);
+ acc100_reg_write(d, HWPfDdrDfiPhyUpdEn, 0x1);
+ acc100_reg_write(d, HWPfDdrUmmcIntEn, 0x1f);
+ /* Release IDTM CPU out of reset */
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 0x2);
+ /* Wait PHY-IDTM to finish static training */
+ for (i = 0; i < ACC100_DDR_TRAINING_MAX; i++) {
+ usleep(ACC100_MS_IN_US);
+ value = acc100_reg_read(d,
+ HWPfChaDdrStDoneStatus);
+ if (value & 1)
+ break;
+ }
+ printf("DDR Training completed in %d ms", i);
+ /* Enable Memory Controller */
+ acc100_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
+ /* Release AXI interface reset */
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 3);
+ }
+
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index cbcece2..071b37c 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -31,11 +31,6 @@
#define RTE_ACC100_PF_DEVICE_ID (0x0d5c)
#define RTE_ACC100_VF_DEVICE_ID (0x0d5d)
-/* Define as 1 to use only a single FEC engine */
-#ifndef RTE_ACC100_SINGLE_FEC
-#define RTE_ACC100_SINGLE_FEC 0
-#endif
-
/* Values used in filling in descriptors */
#define ACC100_DMA_DESC_TYPE 2
#define ACC100_DMA_CODE_BLK_MODE 0
@@ -153,6 +148,12 @@
#define ACC100_CFG_QMGR_HI_P 0x0F0F
#define ACC100_CFG_PCI_AXI 0xC003
#define ACC100_CFG_PCI_BRIDGE 0x40006033
+#define ACC100_QUAD_NUMS 4
+#define ACC100_LANES_PER_QUAD 4
+#define ACC100_PCIE_LANE_OFFSET 0x200
+#define ACC100_PCIE_QUAD_OFFSET 0x2000
+#define ACC100_PCS_EQ 0x6007
+#define ACC100_ADAPT 0x8400
#define ACC100_ENGINE_OFFSET 0x1000
#define ACC100_RESET_HI 0x20100
#define ACC100_RESET_LO 0x20000
@@ -160,6 +161,15 @@
#define ACC100_ENGINES_MAX 9
#define ACC100_LONG_WAIT 1000
#define ACC100_GPEX_AXIMAP_NUM 17
+#define ACC100_CLOCK_GATING_EN 0x30000
+#define ACC100_FABRIC_MODE 0xB
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC100_HARQ_DDR (512 * 1)
+#define ACC100_PRQ_DDR_VER 0x10092020
+#define ACC100_MS_IN_US (1000)
+#define ACC100_DDR_TRAINING_MAX (5000)
/* ACC100 DMA Descriptor triplet */
struct acc100_dma_triplet {
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v7 2/6] baseband/acc100: add protection for some negative scenario
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-31 22:31 ` [PATCH v7 1/6] baseband/acc100: update companion PF configure function Nicolas Chautru
@ 2022-05-31 22:31 ` Nicolas Chautru
2022-06-02 8:21 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro Nicolas Chautru
` (5 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-31 22:31 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru, stable
Catch exception in PMD in case of invalid input parameter.
Fixes: 5ad5060f8f7a ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 79bee43..32c8bc2 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1236,6 +1236,8 @@
return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
}
/* LBRM case - includes a division by N */
+ if (unlikely(z_c == 0))
+ return 0;
if (rv_index == 1)
return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
/ n) * z_c;
@@ -1764,6 +1766,10 @@
/* Soft output */
if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
+ if (op->turbo_dec.soft_output.data == 0) {
+ rte_bbdev_log(ERR, "Soft output is not defined");
+ return -1;
+ }
if (check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_EQUALIZER))
*s_out_length = e;
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-31 22:31 ` [PATCH v7 1/6] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-31 22:31 ` [PATCH v7 2/6] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-05-31 22:31 ` Nicolas Chautru
2022-06-01 14:11 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 4/6] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
` (4 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-31 22:31 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Cosmetic update to remove RTE_ prefix for a define
kept internal.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++--
drivers/baseband/acc100/rte_acc100_pmd.h | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 32c8bc2..210028b 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1133,7 +1133,7 @@
/* ACC100 PCI PF address map */
static struct rte_pci_id pci_id_acc100_pf_map[] = {
{
- RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_PF_DEVICE_ID)
+ RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_PF_DEVICE_ID)
},
{.device_id = 0},
};
@@ -1141,7 +1141,7 @@
/* ACC100 PCI VF address map */
static struct rte_pci_id pci_id_acc100_vf_map[] = {
{
- RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_VF_DEVICE_ID)
+ RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_VF_DEVICE_ID)
},
{.device_id = 0},
};
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index 071b37c..b3956e9 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -27,9 +27,9 @@
#define ACC100VF_DRIVER_NAME intel_acc100_vf
/* ACC100 PCI vendor & device IDs */
-#define RTE_ACC100_VENDOR_ID (0x8086)
-#define RTE_ACC100_PF_DEVICE_ID (0x0d5c)
-#define RTE_ACC100_VF_DEVICE_ID (0x0d5d)
+#define ACC100_VENDOR_ID (0x8086)
+#define ACC100_PF_DEVICE_ID (0x0d5c)
+#define ACC100_VF_DEVICE_ID (0x0d5d)
/* Values used in filling in descriptors */
#define ACC100_DMA_DESC_TYPE 2
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v7 4/6] baseband/acc100: introduce PMD for ACC101
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (2 preceding siblings ...)
2022-05-31 22:31 ` [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro Nicolas Chautru
@ 2022-05-31 22:31 ` Nicolas Chautru
2022-06-02 12:23 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 5/6] baseband/acc100: modify validation code " Nicolas Chautru
` (3 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-31 22:31 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Support for ACC101 as a derivative of ACC100.
Integrated in unified driver and reusing existing code when possible.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
MAINTAINERS | 1 +
doc/guides/bbdevs/acc100.rst | 37 +++++---
doc/guides/bbdevs/features/acc101.ini | 13 +++
doc/guides/rel_notes/release_22_07.rst | 3 +
drivers/baseband/acc100/acc101_pmd.h | 50 ++++++++++
drivers/baseband/acc100/rte_acc100_pmd.c | 153 +++++++++++++++++++++++++++++--
drivers/baseband/acc100/rte_acc100_pmd.h | 11 +++
7 files changed, 249 insertions(+), 19 deletions(-)
create mode 100644 doc/guides/bbdevs/features/acc101.ini
create mode 100644 drivers/baseband/acc100/acc101_pmd.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 17a0559..0610128 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1318,6 +1318,7 @@ F: doc/guides/bbdevs/features/fpga_5gnr_fec.ini
F: drivers/baseband/acc100/
F: doc/guides/bbdevs/acc100.rst
F: doc/guides/bbdevs/features/acc100.ini
+F: doc/guides/bbdevs/features/acc101.ini
Null baseband
M: Nicolas Chautru <nicolas.chautru@intel.com>
diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst
index 9fff6ab..d3a0d9b 100644
--- a/doc/guides/bbdevs/acc100.rst
+++ b/doc/guides/bbdevs/acc100.rst
@@ -1,17 +1,19 @@
.. SPDX-License-Identifier: BSD-3-Clause
Copyright(c) 2020 Intel Corporation
-Intel(R) ACC100 5G/4G FEC Poll Mode Driver
-==========================================
+Intel(R) ACC100 and ACC101 5G/4G FEC Poll Mode Drivers
+======================================================
The BBDEV ACC100 5G/4G FEC poll mode driver (PMD) supports an
implementation of a VRAN FEC wireless acceleration function.
This device is also known as Mount Bryce.
+The BBDEV ACC101, also known as Mount Cirrus, is a derivative device from Mount Bryce
+with functional and capacity improvements but still with the same exposed BBDEV capabilities.
Features
--------
-ACC100 5G/4G FEC PMD supports the following features:
+ACC100 and ACC101 5G/4G FEC PMDs support the following features:
- LDPC Encode in the DL (5GNR)
- LDPC Decode in the UL (5GNR)
@@ -23,7 +25,7 @@ ACC100 5G/4G FEC PMD supports the following features:
- MSI
- SR-IOV
-ACC100 5G/4G FEC PMD supports the following BBDEV capabilities:
+ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities:
* For the LDPC encode operation:
- ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
@@ -80,14 +82,16 @@ hugepage configuration of a server may be examined using:
Initialization
--------------
-When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+When the device first powers up, its PCI Physical Functions (PF) can be listed through these
+commands for ACC100 and ACC101 respectively:
.. code-block:: console
sudo lspci -vd8086:0d5c
+ sudo lspci -vd8086:57c4
The physical and virtual functions are compatible with Linux UIO drivers:
-``vfio`` and ``igb_uio``. However, in order to work the ACC100 5G/4G
+``vfio`` and ``igb_uio``. However, in order to work the 5G/4G
FEC device first needs to be bound to one of these linux drivers through DPDK.
@@ -97,7 +101,8 @@ Bind PF UIO driver(s)
Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
-The igb_uio driver may be bound to the PF PCI device using one of two methods:
+The igb_uio driver may be bound to the PF PCI device using one of two methods for ACC100
+(for ACC101 the device id ``57c4`` should be used in lieu of ``0d5c``):
1. PCI functions (physical or virtual, depending on the use case) can be bound to
@@ -121,7 +126,7 @@ the UIO driver by repeating this command for every function.
where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d5c
-In a similar way the ACC100 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
+In a similar way the 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.
Enable Virtual Functions
@@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and other settings necessary for the
device to perform FEC functions.
This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the function ``acc100_configure()``, which sets up the
-parameters defined in ``acc100_conf`` structure.
+be achieved by using the functions ``rte_acc10x_configure()``,
+which sets up the parameters defined in the compatible ``acc100_conf`` structure.
Test Application
----------------
BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
-the functionality of ACC100 5G/4G FEC encode and decode, depending on the device's
+the functionality of the device 5G/4G FEC encode and decode, depending on the device's
capabilities. The test application is located under app->test-bbdev folder and has the
following options:
@@ -212,7 +217,7 @@ Test Vectors
In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
a range of additional tests under the test_vectors folder, which may be useful. The results
-of these tests will depend on the ACC100 5G/4G FEC capabilities which may cause some
+of these tests will depend on the device 5G/4G FEC capabilities which may cause some
testcases to be skipped, but no failure should be reported.
@@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command below can be used:
./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg
./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
+Specifically for the BBDEV ACC101 PMD, the command below can be used:
+
+.. code-block:: console
+
+ ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg
+ ./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
+
diff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini
new file mode 100644
index 0000000..0e2c21a
--- /dev/null
+++ b/doc/guides/bbdevs/features/acc101.ini
@@ -0,0 +1,13 @@
+;
+; Supported features of the 'acc101' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G) = Y
+Turbo Encoder (4G) = Y
+LDPC Decoder (5G) = Y
+LDPC Encoder (5G) = Y
+LLR/HARQ Compression = Y
+External DDR Access = Y
+HW Accelerated = Y
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index e49cace..1803947 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -104,6 +104,9 @@ New Features
* ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
* ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
+* **Added Intel ACC101 baseband PMD.**
+
+ * Added a new baseband PMD for Intel ACC101 device.
Removed Items
-------------
diff --git a/drivers/baseband/acc100/acc101_pmd.h b/drivers/baseband/acc100/acc101_pmd.h
new file mode 100644
index 0000000..9d8862c
--- /dev/null
+++ b/drivers/baseband/acc100/acc101_pmd.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+/* ACC101 PCI vendor & device IDs */
+#define ACC101_VENDOR_ID (0x8086)
+#define ACC101_PF_DEVICE_ID (0x57c4)
+#define ACC101_VF_DEVICE_ID (0x57c5)
+
+/* Number of Virtual Functions ACC101 supports */
+#define ACC101_NUM_VFS 16
+#define ACC101_NUM_QGRPS 8
+#define ACC101_NUM_AQS 16
+/* All ACC101 Registers alignment are 32bits = 4B */
+#define ACC101_BYTES_IN_WORD 4
+
+#define ACC101_TMPL_PRI_0 0x03020100
+#define ACC101_TMPL_PRI_1 0x07060504
+#define ACC101_TMPL_PRI_2 0x0b0a0908
+#define ACC101_TMPL_PRI_3 0x0f0e0d0c
+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
+
+#define ACC101_NUM_TMPL 32
+/* Mapping of signals for the available engines */
+#define ACC101_SIG_UL_5G 0
+#define ACC101_SIG_UL_5G_LAST 8
+#define ACC101_SIG_DL_5G 13
+#define ACC101_SIG_DL_5G_LAST 15
+#define ACC101_SIG_UL_4G 16
+#define ACC101_SIG_UL_4G_LAST 19
+#define ACC101_SIG_DL_4G 27
+#define ACC101_SIG_DL_4G_LAST 31
+#define ACC101_NUM_ACCS 5
+#define ACC101_PF_VAL 2
+
+/* ACC101 Configuration */
+#define ACC101_CFG_DMA_ERROR 0x3D7
+#define ACC101_CFG_AXI_CACHE 0x11
+#define ACC101_CFG_QMGR_HI_P 0x0F0F
+#define ACC101_CFG_PCI_AXI 0xC003
+#define ACC101_CFG_PCI_BRIDGE 0x40006033
+#define ACC101_ENGINE_OFFSET 0x1000
+#define ACC101_LONG_WAIT 1000
+#define ACC101_GPEX_AXIMAP_NUM 17
+#define ACC101_CLOCK_GATING_EN 0x30000
+#define ACC101_DMA_INBOUND 0x104
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF
+ */
+#define ACC101_HARQ_DDR (512 * 1)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 210028b..31046b5 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -22,6 +22,7 @@
#include <rte_bbdev.h>
#include <rte_bbdev_pmd.h>
#include "rte_acc100_pmd.h"
+#include "acc101_pmd.h"
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
@@ -1133,7 +1134,10 @@
/* ACC100 PCI PF address map */
static struct rte_pci_id pci_id_acc100_pf_map[] = {
{
- RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_PF_DEVICE_ID)
+ RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_PF_DEVICE_ID),
+ },
+ {
+ RTE_PCI_DEVICE(ACC101_VENDOR_ID, ACC101_PF_DEVICE_ID),
},
{.device_id = 0},
};
@@ -1141,7 +1145,10 @@
/* ACC100 PCI VF address map */
static struct rte_pci_id pci_id_acc100_vf_map[] = {
{
- RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_VF_DEVICE_ID)
+ RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_VF_DEVICE_ID),
+ },
+ {
+ RTE_PCI_DEVICE(ACC101_VENDOR_ID, ACC101_VF_DEVICE_ID),
},
{.device_id = 0},
};
@@ -1290,7 +1297,7 @@
/* Fill in a frame control word for LDPC decoding. */
static inline void
-acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
union acc100_harq_layout_data *harq_layout)
{
uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
@@ -1414,6 +1421,128 @@
}
}
+/* Convert offset to harq index for harq_layout structure */
+static inline uint32_t hq_index(uint32_t offset)
+{
+ return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;
+}
+
+/* Fill in a frame control word for LDPC decoding for ACC101 */
+static inline void
+acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout)
+{
+ uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;
+ uint32_t harq_index;
+ uint32_t l;
+
+ fcw->qm = op->ldpc_dec.q_m;
+ fcw->nfiller = op->ldpc_dec.n_filler;
+ fcw->BG = (op->ldpc_dec.basegraph - 1);
+ fcw->Zc = op->ldpc_dec.z_c;
+ fcw->ncb = op->ldpc_dec.n_cb;
+ fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,
+ op->ldpc_dec.rv_index);
+ if (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)
+ fcw->rm_e = op->ldpc_dec.cb_params.e;
+ else
+ fcw->rm_e = (op->ldpc_dec.tb_params.r <
+ op->ldpc_dec.tb_params.cab) ?
+ op->ldpc_dec.tb_params.ea :
+ op->ldpc_dec.tb_params.eb;
+
+ if (unlikely(check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&
+ (op->ldpc_dec.harq_combined_input.length == 0))) {
+ rte_bbdev_log(WARNING, "Null HARQ input size provided");
+ /* Disable HARQ input in that case to carry forward */
+ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+ }
+
+ fcw->hcin_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+ fcw->hcout_en = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+ fcw->crc_select = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+ fcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DECODE_BYPASS);
+ fcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);
+ if (op->ldpc_dec.q_m == 1) {
+ fcw->bypass_intlv = 1;
+ fcw->qm = 2;
+ }
+ fcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);
+ fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_LLR_COMPRESSION);
+ harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);
+ if (fcw->hcin_en > 0) {
+ harq_in_length = op->ldpc_dec.harq_combined_input.length;
+ if (fcw->hcin_decomp_mode > 0)
+ harq_in_length = harq_in_length * 8 / 6;
+ harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb
+ - op->ldpc_dec.n_filler);
+ /* Alignment on next 64B - Already enforced from HC output */
+ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);
+ fcw->hcin_size0 = harq_in_length;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ } else {
+ fcw->hcin_size0 = 0;
+ fcw->hcin_offset = 0;
+ fcw->hcin_size1 = 0;
+ }
+
+ fcw->itmax = op->ldpc_dec.iter_max;
+ fcw->itstop = check_bit(op->ldpc_dec.op_flags,
+ RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+ fcw->synd_precoder = fcw->itstop;
+ /*
+ * These are all implicitly set
+ * fcw->synd_post = 0;
+ * fcw->so_en = 0;
+ * fcw->so_bypass_rm = 0;
+ * fcw->so_bypass_intlv = 0;
+ * fcw->dec_convllr = 0;
+ * fcw->hcout_convllr = 0;
+ * fcw->hcout_size1 = 0;
+ * fcw->so_it = 0;
+ * fcw->hcout_offset = 0;
+ * fcw->negstop_th = 0;
+ * fcw->negstop_it = 0;
+ * fcw->negstop_en = 0;
+ * fcw->gain_i = 1;
+ * fcw->gain_h = 1;
+ */
+ if (fcw->hcout_en > 0) {
+ parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)
+ * op->ldpc_dec.z_c - op->ldpc_dec.n_filler;
+ k0_p = (fcw->k0 > parity_offset) ?
+ fcw->k0 - op->ldpc_dec.n_filler : fcw->k0;
+ ncb_p = fcw->ncb - op->ldpc_dec.n_filler;
+ l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);
+ harq_out_length = (uint16_t) fcw->hcin_size0;
+ harq_out_length = RTE_MAX(harq_out_length, l);
+ /* Cannot exceed the pruned Ncb circular buffer */
+ harq_out_length = RTE_MIN(harq_out_length, ncb_p);
+ /* Alignment on next 64B */
+ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);
+ fcw->hcout_size0 = harq_out_length;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ harq_layout[harq_index].offset = fcw->hcout_offset;
+ harq_layout[harq_index].size0 = fcw->hcout_size0;
+ } else {
+ fcw->hcout_size0 = 0;
+ fcw->hcout_size1 = 0;
+ fcw->hcout_offset = 0;
+ }
+}
+
/**
* Fills descriptor with data pointers of one block type.
*
@@ -2966,7 +3095,7 @@
struct acc100_fcw_ld *fcw;
uint32_t seg_total_left;
fcw = &desc->req.fcw_ld;
- acc100_fcw_ld_fill(op, fcw, harq_layout);
+ q->d->fcw_ld_fill(op, fcw, harq_layout);
/* Special handling when overusing mbuf */
if (fcw->rm_e < ACC100_MAX_E_MBUF)
@@ -3033,7 +3162,7 @@
desc = q->ring_addr + desc_idx;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
union acc100_harq_layout_data *harq_layout = q->d->harq_layout;
- acc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
+ q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);
input = op->ldpc_dec.input.data;
h_output_head = h_output = op->ldpc_dec.hard_output.data;
@@ -4145,9 +4274,19 @@
dev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;
dev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;
+ /* Device variant specific handling */
+ if ((pci_dev->id.device_id == ACC100_PF_DEVICE_ID) ||
+ (pci_dev->id.device_id == ACC100_VF_DEVICE_ID)) {
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc100_fcw_ld_fill;
+ } else {
+ ((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;
+ ((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc101_fcw_ld_fill;
+ }
+
((struct acc100_device *) dev->data->dev_private)->pf_device =
- !strcmp(drv->driver.name,
- RTE_STR(ACC100PF_DRIVER_NAME));
+ !strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));
+
((struct acc100_device *) dev->data->dev_private)->mmio_base =
pci_dev->mem_resource[0].addr;
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index b3956e9..0c9810c 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -22,6 +22,9 @@
#define rte_bbdev_log_debug(fmt, ...)
#endif
+#define ACC100_VARIANT 0
+#define ACC101_VARIANT 1
+
/* ACC100 PF and VF driver names */
#define ACC100PF_DRIVER_NAME intel_acc100_pf
#define ACC100VF_DRIVER_NAME intel_acc100_vf
@@ -62,6 +65,8 @@
#define ACC100_HARQ_LAYOUT (64*1024*1024)
/* Assume offset for HARQ in memory */
#define ACC100_HARQ_OFFSET (32*1024)
+#define ACC100_HARQ_OFFSET_SHIFT 15
+#define ACC100_HARQ_OFFSET_MASK 0x7ffffff
/* Mask used to calculate an index in an Info Ring array (not a byte offset) */
#define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)
/* Number of Virtual Functions ACC100 supports */
@@ -569,6 +574,10 @@ struct __rte_cache_aligned acc100_queue {
struct acc100_device *d;
};
+typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,
+ struct acc100_fcw_ld *fcw,
+ union acc100_harq_layout_data *harq_layout);
+
/* Private data structure for each ACC100 device */
struct acc100_device {
void *mmio_base; /**< Base address of MMIO registers (BAR0) */
@@ -600,6 +609,8 @@ struct acc100_device {
uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
bool pf_device; /**< True if this is a PF ACC100 device */
bool configured; /**< True if this ACC100 device is configured */
+ uint16_t device_variant; /**< Device variant */
+ acc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation function */
};
/**
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v7 5/6] baseband/acc100: modify validation code for ACC101
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (3 preceding siblings ...)
2022-05-31 22:31 ` [PATCH v7 4/6] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-05-31 22:31 ` Nicolas Chautru
2022-06-03 20:23 ` Vargas, Hernan
2022-05-31 22:31 ` [PATCH v7 6/6] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
` (2 subsequent siblings)
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-31 22:31 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
The validation requirement is different for the two
devices.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 51 ++++++++++++++++++++++++--------
1 file changed, 39 insertions(+), 12 deletions(-)
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 31046b5..956bd43 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1295,6 +1295,21 @@
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+static inline bool
+is_acc100(struct acc100_queue *q)
+{
+ return (q->d->device_variant == ACC100_VARIANT);
+}
+
+static inline bool
+validate_op_required(struct acc100_queue *q)
+{
+ return is_acc100(q);
+}
+#endif
+
/* Fill in a frame control word for LDPC decoding. */
static inline void
acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,
@@ -2182,13 +2197,16 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo encoder parameters */
static inline int
-validate_enc_op(struct rte_bbdev_enc_op *op)
+validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
uint16_t kw, kw_neg, kw_pos;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2320,10 +2338,13 @@ static inline uint32_t hq_index(uint32_t offset)
}
/* Validates LDPC encoder parameters */
static inline int
-validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
+validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2373,10 +2394,13 @@ static inline uint32_t hq_index(uint32_t offset)
/* Validates LDPC decoder parameters */
static inline int
-validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
+validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2429,7 +2453,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2483,7 +2507,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(ops[0]) == -1) {
+ if (validate_ldpc_enc_op(ops[0], q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2545,7 +2569,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(op) == -1) {
+ if (validate_ldpc_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2602,7 +2626,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2675,12 +2699,15 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo decoder parameters */
static inline int
-validate_dec_op(struct rte_bbdev_dec_op *op)
+validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2822,7 +2849,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
@@ -3047,7 +3074,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3151,7 +3178,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3241,7 +3268,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH v7 6/6] baseband/acc100: configuration of ACC101 from PF
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (4 preceding siblings ...)
2022-05-31 22:31 ` [PATCH v7 5/6] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-05-31 22:31 ` Nicolas Chautru
2022-06-02 8:33 ` Maxime Coquelin
2022-06-06 14:54 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Chautru, Nicolas
2022-06-15 14:08 ` [EXT] " Akhil Goyal
7 siblings, 1 reply; 84+ messages in thread
From: Nicolas Chautru @ 2022-05-31 22:31 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, Nicolas Chautru
Adding companion function common to ACC100/ACC101 which
can be called from bbdev-test when running from PF.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 6 +-
drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
drivers/baseband/acc100/rte_acc100_pmd.c | 314 ++++++++++++++++++++++++++++++-
drivers/baseband/acc100/version.map | 3 +-
4 files changed, 318 insertions(+), 9 deletions(-)
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 0fa119a..718e5ef 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -711,11 +711,11 @@ typedef int (test_case_function)(struct active_device *ad,
#endif
#ifdef RTE_BASEBAND_ACC100
if ((get_init_device() == true) &&
- (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
+ (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {
struct rte_acc100_conf conf;
unsigned int i;
- printf("Configure ACC100 FEC Driver %s with default values\n",
+ printf("Configure ACC100/ACC101 FEC Driver %s with default values\n",
info->drv.driver_name);
/* clear default configuration before initialization */
@@ -760,7 +760,7 @@ typedef int (test_case_function)(struct active_device *ad,
conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;
/* setup PF with configuration information */
- ret = rte_acc100_configure(info->dev_name, &conf);
+ ret = rte_acc10x_configure(info->dev_name, &conf);
TEST_ASSERT_SUCCESS(ret,
"Failed to configure ACC100 PF for bbdev %s",
info->dev_name);
diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h
index d233e42..b70803d 100644
--- a/drivers/baseband/acc100/rte_acc100_cfg.h
+++ b/drivers/baseband/acc100/rte_acc100_cfg.h
@@ -90,7 +90,7 @@ struct rte_acc100_conf {
};
/**
- * Configure a ACC100 device
+ * Configure a ACC100/ACC101 device in PF mode notably for bbdev-test
*
* @param dev_name
* The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
@@ -104,7 +104,7 @@ struct rte_acc100_conf {
*/
__rte_experimental
int
-rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);
+rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf);
#ifdef __cplusplus
}
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 956bd43..15f3c11 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -4578,8 +4578,8 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Initial configuration of a ACC100 device prior to running configure() */
-int
-rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
+static int
+acc100_configure(const char *dev_name, struct rte_acc100_conf *conf)
{
rte_bbdev_log(INFO, "rte_acc100_configure");
uint32_t value, address, status;
@@ -4970,3 +4970,313 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
+
+
+/* Initial configuration of a ACC101 device prior to running configure() */
+static int
+acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc101_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc100_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+
+ /* PCIe Bridge configuration */
+ acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);
+ for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)
+ acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);
+
+ /* Prevent blocking AXI read on BRESP for AXI Write */
+ address = HwPfPcieGpexAxiPioControl;
+ value = ACC101_CFG_PCI_AXI;
+ acc100_reg_write(d, address, value);
+
+ /* Explicitly releasing AXI including a 2ms delay on ACC101 */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* Set the default 5GDL DMA configuration */
+ acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);
+
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC101_CLOCK_GATING_EN;
+ acc100_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC101_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc100_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC101_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc100_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc100_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ address = HWPfDmaConfig1Reg;
+ int alen_r = 0xF;
+ int alen_w = 0x7;
+ value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;
+ acc100_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc100_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_1;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_2;
+ acc100_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;
+ value = ACC101_TMPL_PRI_3;
+ acc100_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC101_CFG_QMGR_HI_P;
+ acc100_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC101_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_4G;
+ template_idx <= ACC101_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_UL_5G;
+ template_idx <= ACC101_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg +
+ ACC101_ENGINE_OFFSET * template_idx;
+ status = (acc100_reg_read(d, address) >> 4) & 0xF;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc100_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc100_reg_write(d, address, 0);
+ }
+ printf("Number of 5GUL engines %d\n", numEngines);
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_4G;
+ template_idx <= ACC101_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC101_SIG_DL_5G;
+ template_idx <= ACC101_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC101_BYTES_IN_WORD * template_idx;
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ address = HWPfQmgrGrpFunction0;
+ value = 0;
+ for (qg_idx = 0; qg_idx < 8; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc]<<(qg_idx * 4);
+ }
+ acc100_reg_write(d, address, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC101_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ }
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC101_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc100_reg_write(d, address, value);
+ }
+ }
+
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC101_BYTES_IN_WORD + qg_idx
+ * ACC101_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc100_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC101_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc100_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;
+ acc100_reg_write(d, address, value);
+ /* Explicitly releasing AXI after PF Mode and 2 ms */
+ usleep(2000);
+ acc100_reg_write(d, HWPfDmaAxiControl, 1);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc100_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc100_reg_write(d, address, value);
+
+ /* HARQ DDR Configuration */
+ unsigned int ddrSizeInMb = ACC101_HARQ_DDR;
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfDmaVfDdrBaseRw + vf_idx
+ * 0x10;
+ value = ((vf_idx * (ddrSizeInMb / 64)) << 16) +
+ (ddrSizeInMb - 1);
+ acc100_reg_write(d, address, value);
+ }
+ usleep(ACC101_LONG_WAIT);
+
+ rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name);
+ return 0;
+}
+
+int
+rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf)
+{
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device);
+ printf("Configure dev id %x\n", pci_dev->id.device_id);
+ if (pci_dev->id.device_id == ACC100_PF_DEVICE_ID)
+ return acc100_configure(dev_name, conf);
+ else
+ return acc101_configure(dev_name, conf);
+}
diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map
index 40604c7..13f0398 100644
--- a/drivers/baseband/acc100/version.map
+++ b/drivers/baseband/acc100/version.map
@@ -5,6 +5,5 @@ DPDK_22 {
EXPERIMENTAL {
global:
- rte_acc100_configure;
-
+ rte_acc10x_configure;
};
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro
2022-05-31 22:31 ` [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro Nicolas Chautru
@ 2022-06-01 14:11 ` Maxime Coquelin
2022-06-01 17:15 ` [EXT] " Akhil Goyal
0 siblings, 1 reply; 84+ messages in thread
From: Maxime Coquelin @ 2022-06-01 14:11 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
On 6/1/22 00:31, Nicolas Chautru wrote:
> Cosmetic update to remove RTE_ prefix for a define
> kept internal.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++--
> drivers/baseband/acc100/rte_acc100_pmd.h | 6 +++---
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index 32c8bc2..210028b 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -1133,7 +1133,7 @@
> /* ACC100 PCI PF address map */
> static struct rte_pci_id pci_id_acc100_pf_map[] = {
> {
> - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_PF_DEVICE_ID)
> + RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_PF_DEVICE_ID)
> },
> {.device_id = 0},
> };
> @@ -1141,7 +1141,7 @@
> /* ACC100 PCI VF address map */
> static struct rte_pci_id pci_id_acc100_vf_map[] = {
> {
> - RTE_PCI_DEVICE(RTE_ACC100_VENDOR_ID, RTE_ACC100_VF_DEVICE_ID)
> + RTE_PCI_DEVICE(ACC100_VENDOR_ID, ACC100_VF_DEVICE_ID)
> },
> {.device_id = 0},
> };
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
> index 071b37c..b3956e9 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.h
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.h
> @@ -27,9 +27,9 @@
> #define ACC100VF_DRIVER_NAME intel_acc100_vf
>
> /* ACC100 PCI vendor & device IDs */
> -#define RTE_ACC100_VENDOR_ID (0x8086)
> -#define RTE_ACC100_PF_DEVICE_ID (0x0d5c)
> -#define RTE_ACC100_VF_DEVICE_ID (0x0d5d)
> +#define ACC100_VENDOR_ID (0x8086)
> +#define ACC100_PF_DEVICE_ID (0x0d5c)
> +#define ACC100_VF_DEVICE_ID (0x0d5d)
>
> /* Values used in filling in descriptors */
> #define ACC100_DMA_DESC_TYPE 2
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Thanks,
Maxime
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [EXT] Re: [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro
2022-06-01 14:11 ` Maxime Coquelin
@ 2022-06-01 17:15 ` Akhil Goyal
2022-06-02 12:57 ` Maxime Coquelin
0 siblings, 1 reply; 84+ messages in thread
From: Akhil Goyal @ 2022-06-01 17:15 UTC (permalink / raw)
To: Maxime Coquelin, Nicolas Chautru, dev, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
Hi Maxime,
>
> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
>
Do you have any more comments on other patches of this series?
If not, please ack other patches as well.
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v7 2/6] baseband/acc100: add protection for some negative scenario
2022-05-31 22:31 ` [PATCH v7 2/6] baseband/acc100: add protection for some negative scenario Nicolas Chautru
@ 2022-06-02 8:21 ` Maxime Coquelin
0 siblings, 0 replies; 84+ messages in thread
From: Maxime Coquelin @ 2022-06-02 8:21 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, stable
On 6/1/22 00:31, Nicolas Chautru wrote:
> Catch exception in PMD in case of invalid input parameter.
>
> Fixes: 5ad5060f8f7a ("baseband/acc100: add LDPC processing functions")
> Cc: stable@dpdk.org
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/rte_acc100_pmd.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index 79bee43..32c8bc2 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -1236,6 +1236,8 @@
> return (bg == 1 ? ACC100_K0_3_1 : ACC100_K0_3_2) * z_c;
> }
> /* LBRM case - includes a division by N */
> + if (unlikely(z_c == 0))
> + return 0;
> if (rv_index == 1)
> return (((bg == 1 ? ACC100_K0_1_1 : ACC100_K0_1_2) * n_cb)
> / n) * z_c;
> @@ -1764,6 +1766,10 @@
>
> /* Soft output */
> if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) {
> + if (op->turbo_dec.soft_output.data == 0) {
> + rte_bbdev_log(ERR, "Soft output is not defined");
> + return -1;
> + }
> if (check_bit(op->turbo_dec.op_flags,
> RTE_BBDEV_TURBO_EQUALIZER))
> *s_out_length = e;
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Thanks,
Maxime
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v7 6/6] baseband/acc100: configuration of ACC101 from PF
2022-05-31 22:31 ` [PATCH v7 6/6] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-06-02 8:33 ` Maxime Coquelin
0 siblings, 0 replies; 84+ messages in thread
From: Maxime Coquelin @ 2022-06-02 8:33 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
On 6/1/22 00:31, Nicolas Chautru wrote:
> Adding companion function common to ACC100/ACC101 which
> can be called from bbdev-test when running from PF.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> app/test-bbdev/test_bbdev_perf.c | 6 +-
> drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> drivers/baseband/acc100/rte_acc100_pmd.c | 314 ++++++++++++++++++++++++++++++-
> drivers/baseband/acc100/version.map | 3 +-
> 4 files changed, 318 insertions(+), 9 deletions(-)
>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Thanks,
Maxime
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v7 1/6] baseband/acc100: update companion PF configure function
2022-05-31 22:31 ` [PATCH v7 1/6] baseband/acc100: update companion PF configure function Nicolas Chautru
@ 2022-06-02 9:49 ` Kevin Traynor
2022-06-02 16:52 ` Chautru, Nicolas
2022-06-03 20:25 ` Vargas, Hernan
1 sibling, 1 reply; 84+ messages in thread
From: Kevin Traynor @ 2022-06-02 9:49 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand, stable
Hi Nicolas,
On 31/05/2022 23:31, Nicolas Chautru wrote:
> Update of the device configuration function from PF used for bbdev-test
> to latest sequence for ACC199 PRQ device and matching version in
> pf_bb_config 22.03.
>
> Fixes: b17d70922d5d ("baseband/acc100: add configure function")
> Cc:stable@dpdk.org
>
Can you describe what this patch is fixing?
Is it backwards compatible to keep things working if someone only
upgrades DPDK (e.g. 21.11 to 21.11.2)? The commit log mentioning 22.03
makes think it may not be the case.
thanks,
Kevin.
> Signed-off-by: Nicolas Chautru<nicolas.chautru@intel.com>
> ---
> drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++
> drivers/baseband/acc100/rte_acc100_pmd.c | 163 +++++++++++++++++++++++--------
> drivers/baseband/acc100/rte_acc100_pmd.h | 20 +++-
> 3 files changed, 153 insertions(+), 48 deletions(-)
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v7 4/6] baseband/acc100: introduce PMD for ACC101
2022-05-31 22:31 ` [PATCH v7 4/6] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
@ 2022-06-02 12:23 ` Maxime Coquelin
0 siblings, 0 replies; 84+ messages in thread
From: Maxime Coquelin @ 2022-06-02 12:23 UTC (permalink / raw)
To: Nicolas Chautru, dev, gakhil, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
On 6/1/22 00:31, Nicolas Chautru wrote:
> Support for ACC101 as a derivative of ACC100.
> Integrated in unified driver and reusing existing code when possible.
>
> Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
> ---
> MAINTAINERS | 1 +
> doc/guides/bbdevs/acc100.rst | 37 +++++---
> doc/guides/bbdevs/features/acc101.ini | 13 +++
> doc/guides/rel_notes/release_22_07.rst | 3 +
> drivers/baseband/acc100/acc101_pmd.h | 50 ++++++++++
> drivers/baseband/acc100/rte_acc100_pmd.c | 153 +++++++++++++++++++++++++++++--
> drivers/baseband/acc100/rte_acc100_pmd.h | 11 +++
> 7 files changed, 249 insertions(+), 19 deletions(-)
> create mode 100644 doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/acc101_pmd.h
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Thanks,
Maxime
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [EXT] Re: [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro
2022-06-01 17:15 ` [EXT] " Akhil Goyal
@ 2022-06-02 12:57 ` Maxime Coquelin
0 siblings, 0 replies; 84+ messages in thread
From: Maxime Coquelin @ 2022-06-02 12:57 UTC (permalink / raw)
To: Akhil Goyal, Nicolas Chautru, dev, trix
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
Hi Akhil,
On 6/1/22 19:15, Akhil Goyal wrote:
> Hi Maxime,
>>
>> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
>>
> Do you have any more comments on other patches of this series?
> If not, please ack other patches as well.
>
I'm done with my review of the series.
Regards
Maxime
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v7 1/6] baseband/acc100: update companion PF configure function
2022-06-02 9:49 ` Kevin Traynor
@ 2022-06-02 16:52 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-06-02 16:52 UTC (permalink / raw)
To: Kevin Traynor, dev, gakhil, trix, maxime.coquelin
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand, stable
Hi Kevin,
> -----Original Message-----
> From: Kevin Traynor <ktraynor@redhat.com>
> Sent: Thursday, June 2, 2022 2:50 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> gakhil@marvell.com; trix@redhat.com; maxime.coquelin@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com; stable@dpdk.org
> Subject: Re: [PATCH v7 1/6] baseband/acc100: update companion PF
> configure function
>
> Hi Nicolas,
>
> On 31/05/2022 23:31, Nicolas Chautru wrote:
> > Update of the device configuration function from PF used for
> > bbdev-test to latest sequence for ACC199 PRQ device and matching
> > version in pf_bb_config 22.03.
> >
> > Fixes: b17d70922d5d ("baseband/acc100: add configure function")
> > Cc:stable@dpdk.org
> >
>
> Can you describe what this patch is fixing?
>
> Is it backwards compatible to keep things working if someone only upgrades
> DPDK (e.g. 21.11 to 21.11.2)? The commit log mentioning 22.03 makes think it
> may not be the case.
The companion function used by bbdev-test to configure the device from PF is updated to latest
including possible HW exception and tuning => there is no backward compatibility aspect between the PMD and that
configuration sequence, but latest is greatest hence updating now.
22.03 version is referring to another ingredient outside of DPDK (pf_bb_config) for reference only.
I hope this clarifies. There is no direct dependency or compatibility concern.
Thanks
Nic
>
> thanks,
> Kevin.
>
> > Signed-off-by: Nicolas Chautru<nicolas.chautru@intel.com>
> > ---
> > drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++
> > drivers/baseband/acc100/rte_acc100_pmd.c | 163
> +++++++++++++++++++++++--------
> > drivers/baseband/acc100/rte_acc100_pmd.h | 20 +++-
> > 3 files changed, 153 insertions(+), 48 deletions(-)
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v7 5/6] baseband/acc100: modify validation code for ACC101
2022-05-31 22:31 ` [PATCH v7 5/6] baseband/acc100: modify validation code " Nicolas Chautru
@ 2022-06-03 20:23 ` Vargas, Hernan
0 siblings, 0 replies; 84+ messages in thread
From: Vargas, Hernan @ 2022-06-03 20:23 UTC (permalink / raw)
To: Chautru, Nicolas, dev, gakhil, trix, maxime.coquelin
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, david.marchand
-----Original Message-----
From: Chautru, Nicolas <nicolas.chautru@intel.com>
Sent: Tuesday, May 31, 2022 5:32 PM
To: dev@dpdk.org; gakhil@marvell.com; trix@redhat.com; maxime.coquelin@redhat.com
Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson, Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>; david.marchand@redhat.com; Chautru, Nicolas <nicolas.chautru@intel.com>
Subject: [PATCH v7 5/6] baseband/acc100: modify validation code for ACC101
The validation requirement is different for the two devices.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/rte_acc100_pmd.c | 51 ++++++++++++++++++++++++--------
1 file changed, 39 insertions(+), 12 deletions(-)
Reviewed-by: Hernan Vargas <hernan.vargas@intel.com>
Thanks,
Hernan
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 31046b5..956bd43 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1295,6 +1295,21 @@
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+static inline bool
+is_acc100(struct acc100_queue *q)
+{
+ return (q->d->device_variant == ACC100_VARIANT); }
+
+static inline bool
+validate_op_required(struct acc100_queue *q) {
+ return is_acc100(q);
+}
+#endif
+
/* Fill in a frame control word for LDPC decoding. */ static inline void acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, @@ -2182,13 +2197,16 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo encoder parameters */ static inline int -validate_enc_op(struct rte_bbdev_enc_op *op)
+validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q)
{
struct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;
struct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;
uint16_t kw, kw_neg, kw_pos;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2320,10 +2338,13 @@ static inline uint32_t hq_index(uint32_t offset) }
/* Validates LDPC encoder parameters */ static inline int -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op)
+validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue
+*q)
{
struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2373,10 +2394,13 @@ static inline uint32_t hq_index(uint32_t offset)
/* Validates LDPC decoder parameters */ static inline int -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op)
+validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue
+*q)
{
struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2429,7 +2453,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2483,7 +2507,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(ops[0]) == -1) {
+ if (validate_ldpc_enc_op(ops[0], q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2545,7 +2569,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_enc_op(op) == -1) {
+ if (validate_ldpc_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC encoder validation failed");
return -EINVAL;
}
@@ -2602,7 +2626,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_enc_op(op) == -1) {
+ if (validate_enc_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo encoder validation failed");
return -EINVAL;
}
@@ -2675,12 +2699,15 @@ static inline uint32_t hq_index(uint32_t offset) #ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validates turbo decoder parameters */ static inline int -validate_dec_op(struct rte_bbdev_dec_op *op)
+validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q)
{
struct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;
struct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;
struct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;
+ if (!validate_op_required(q))
+ return 0;
+
if (op->mempool == NULL) {
rte_bbdev_log(ERR, "Invalid mempool pointer");
return -1;
@@ -2822,7 +2849,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
@@ -3047,7 +3074,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3151,7 +3178,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_ldpc_dec_op(op) == -1) {
+ if (validate_ldpc_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "LDPC decoder validation failed");
return -EINVAL;
}
@@ -3241,7 +3268,7 @@ static inline uint32_t hq_index(uint32_t offset)
#ifdef RTE_LIBRTE_BBDEV_DEBUG
/* Validate op structure */
- if (validate_dec_op(op) == -1) {
+ if (validate_dec_op(op, q) == -1) {
rte_bbdev_log(ERR, "Turbo decoder validation failed");
return -EINVAL;
}
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v7 1/6] baseband/acc100: update companion PF configure function
2022-05-31 22:31 ` [PATCH v7 1/6] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-06-02 9:49 ` Kevin Traynor
@ 2022-06-03 20:25 ` Vargas, Hernan
1 sibling, 0 replies; 84+ messages in thread
From: Vargas, Hernan @ 2022-06-03 20:25 UTC (permalink / raw)
To: Chautru, Nicolas, dev, gakhil, trix, maxime.coquelin
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal,
david.marchand, stable
-----Original Message-----
From: Chautru, Nicolas <nicolas.chautru@intel.com>
Sent: Tuesday, May 31, 2022 5:32 PM
To: dev@dpdk.org; gakhil@marvell.com; trix@redhat.com; maxime.coquelin@redhat.com
Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson, Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>; david.marchand@redhat.com; Chautru, Nicolas <nicolas.chautru@intel.com>; stable@dpdk.org
Subject: [PATCH v7 1/6] baseband/acc100: update companion PF configure function
Update of the device configuration function from PF used for bbdev-test to latest sequence for ACC199 PRQ device and matching version in pf_bb_config 22.03.
Fixes: b17d70922d5d ("baseband/acc100: add configure function")
Cc: stable@dpdk.org
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++ drivers/baseband/acc100/rte_acc100_pmd.c | 163 +++++++++++++++++++++++-------- drivers/baseband/acc100/rte_acc100_pmd.h | 20 +++-
3 files changed, 153 insertions(+), 48 deletions(-)
Reviewed-by: Hernan Vargas <hernan.vargas@intel.com>
Thanks,
Hernan
diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h
index a1ee416..2fba667 100644
--- a/drivers/baseband/acc100/acc100_pf_enum.h
+++ b/drivers/baseband/acc100/acc100_pf_enum.h
@@ -238,6 +238,24 @@ enum {
HWPfPermonBTotalLatLowBusMon = 0x00BAC504,
HWPfPermonBTotalLatUpperBusMon = 0x00BAC508,
HWPfPermonBTotalReqCntBusMon = 0x00BAC50C,
+ HwPfFabI2MArbCntrlReg = 0x00BB0000,
+ HWPfFabricMode = 0x00BB1000,
+ HwPfFabI2MGrp0DebugReg = 0x00BBF000,
+ HwPfFabI2MGrp1DebugReg = 0x00BBF004,
+ HwPfFabI2MGrp2DebugReg = 0x00BBF008,
+ HwPfFabI2MGrp3DebugReg = 0x00BBF00C,
+ HwPfFabI2MBuf0DebugReg = 0x00BBF010,
+ HwPfFabI2MBuf1DebugReg = 0x00BBF014,
+ HwPfFabI2MBuf2DebugReg = 0x00BBF018,
+ HwPfFabI2MBuf3DebugReg = 0x00BBF01C,
+ HwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020,
+ HwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024,
+ HwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028,
+ HwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C,
+ HwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030,
+ HwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034,
+ HwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038,
+ HwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C,
HWPfFecUl5gCntrlReg = 0x00BC0000,
HWPfFecUl5gI2MThreshReg = 0x00BC0004,
HWPfFecUl5gVersionReg = 0x00BC0100,
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index de7e4bc..79bee43 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -141,8 +141,8 @@
int acc_enum = accFromQgid(qg_idx, acc100_conf);
qtopFromAcc(&q_top, acc_enum, acc100_conf);
if (unlikely(q_top == NULL))
- return 0;
- return q_top->aq_depth_log2;
+ return 1;
+ return RTE_MAX(1, q_top->aq_depth_log2);
}
/* Return the AQ depth for a Queue Group Index */ @@ -4411,7 +4411,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) {
rte_bbdev_log(INFO, "rte_acc100_configure");
uint32_t value, address, status;
- int qg_idx, template_idx, vf_idx, acc, i;
+ int qg_idx, template_idx, vf_idx, acc, i, j;
struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
/* Compile time checks */
@@ -4431,6 +4431,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* Store configuration */
rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));
+ value = acc100_reg_read(d, HwPfPcieGpexBridgeControl);
+ bool firstCfg = (value != ACC100_CFG_PCI_BRIDGE);
+
/* PCIe Bridge configuration */
acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE);
for (i = 1; i < ACC100_GPEX_AXIMAP_NUM; i++) @@ -4451,20 +4454,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = 1;
acc100_reg_write(d, address, value);
- /* DDR Configuration */
- address = HWPfDdrBcTim6;
- value = acc100_reg_read(d, address);
- value &= 0xFFFFFFFB; /* Bit 2 */
-#ifdef ACC100_DDR_ECC_ENABLE
- value |= 0x4;
-#endif
- acc100_reg_write(d, address, value);
- address = HWPfDdrPhyDqsCountNum;
-#ifdef ACC100_DDR_ECC_ENABLE
- value = 9;
-#else
- value = 8;
-#endif
+ /* Enable granular dynamic clock gating */
+ address = HWPfHiClkGateHystReg;
+ value = ACC100_CLOCK_GATING_EN;
acc100_reg_write(d, address, value);
/* Set default descriptor signature */ @@ -4482,6 +4474,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfDmaAxcacheReg;
acc100_reg_write(d, address, value);
+ /* Adjust PCIe Lane adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ for (j = 0; j < ACC100_LANES_PER_QUAD; j++)
+ acc100_reg_write(d, HwPfPcieLnAdaptctrl + i * ACC100_PCIE_QUAD_OFFSET
+ + j * ACC100_PCIE_LANE_OFFSET, ACC100_ADAPT);
+
+ /* Enable PCIe live adaptation */
+ for (i = 0; i < ACC100_QUAD_NUMS; i++)
+ acc100_reg_write(d, HwPfPciePcsEqControl +
+ i * ACC100_PCIE_QUAD_OFFSET, ACC100_PCS_EQ);
+
/* Default DMA Configuration (Qmgr Enabled) */
address = HWPfDmaConfig0Reg;
value = 0;
@@ -4500,6 +4503,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
value = HWPfQmgrEgressQueuesTemplate;
acc100_reg_write(d, address, value);
+ /* Default Fabric Mode */
+ address = HWPfFabricMode;
+ value = ACC100_FABRIC_MODE;
+ acc100_reg_write(d, address, value);
+
/* ===== Qmgr Configuration ===== */
/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
int totalQgs = conf->q_ul_4g.num_qgroups + @@ -4518,22 +4526,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
/* Template Priority in incremental order */
- for (template_idx = 0; template_idx < ACC100_NUM_TMPL;
- template_idx++) {
- address = HWPfQmgrGrpTmplateReg0Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ for (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC100_BYTES_IN_WORD *
+template_idx;
value = ACC100_TMPL_PRI_0;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg1Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC100_BYTES_IN_WORD *
+template_idx;
value = ACC100_TMPL_PRI_1;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg2indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC100_BYTES_IN_WORD *
+template_idx;
value = ACC100_TMPL_PRI_2;
acc100_reg_write(d, address, value);
- address = HWPfQmgrGrpTmplateReg3Indx +
- ACC100_BYTES_IN_WORD * (template_idx % 8);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC100_BYTES_IN_WORD *
+template_idx;
value = ACC100_TMPL_PRI_3;
acc100_reg_write(d, address, value);
}
@@ -4584,9 +4587,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
numEngines++;
} else
acc100_reg_write(d, address, 0);
-#if RTE_ACC100_SINGLE_FEC == 1
- value = 0;
-#endif
}
printf("Number of 5GUL engines %d\n", numEngines);
/* 4GDL */
@@ -4601,9 +4601,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfQmgrGrpTmplateReg4Indx
+ ACC100_BYTES_IN_WORD * template_idx;
acc100_reg_write(d, address, value);
-#if RTE_ACC100_SINGLE_FEC == 1
- value = 0;
-#endif
}
/* 5GDL */
numQqsAcc += numQgs;
@@ -4617,13 +4614,10 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfQmgrGrpTmplateReg4Indx
+ ACC100_BYTES_IN_WORD * template_idx;
acc100_reg_write(d, address, value);
-#if RTE_ACC100_SINGLE_FEC == 1
- value = 0;
-#endif
}
/* Queue Group Function mapping */
- int qman_func_id[5] = {0, 2, 1, 3, 4};
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
address = HWPfQmgrGrpFunction0;
value = 0;
for (qg_idx = 0; qg_idx < 8; qg_idx++) { @@ -4654,7 +4648,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
}
}
- /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
+ /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */
uint32_t aram_address = 0;
for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { @@ -4679,6 +4673,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
/* ==== HI Configuration ==== */
+ /* No Info Ring/MSI by default */
+ acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);
+ acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);
+ acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);
+ acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);
/* Prevent Block on Transmit Error */
address = HWPfHiBlockTransmitOnErrorEn;
value = 0;
@@ -4691,10 +4690,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
address = HWPfHiPfMode;
value = (conf->pf_mode_en) ? ACC100_PF_VAL : 0;
acc100_reg_write(d, address, value);
- /* Enable Error Detection in HW */
- address = HWPfDmaErrorDetectionEn;
- value = 0x3D7;
- acc100_reg_write(d, address, value);
/* QoS overflow init */
value = 1;
@@ -4704,7 +4699,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
acc100_reg_write(d, address, value);
/* HARQ DDR Configuration */
- unsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */
+ unsigned int ddrSizeInMb = ACC100_HARQ_DDR;
for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
address = HWPfDmaVfDdrBaseRw + vf_idx
* 0x10;
@@ -4718,6 +4713,88 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)
if (numEngines < (ACC100_SIG_UL_5G_LAST + 1))
poweron_cleanup(bbdev, d, conf);
+ uint32_t version = 0;
+ for (i = 0; i < 4; i++)
+ version += acc100_reg_read(d,
+ HWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);
+ if (version != ACC100_PRQ_DDR_VER) {
+ printf("* Note: Not on DDR PRQ version %8x != %08x\n",
+ version, ACC100_PRQ_DDR_VER);
+ } else if (firstCfg) {
+ /* ---- DDR configuration at boot up --- */
+ /* Read Clear Ddr training status */
+ acc100_reg_read(d, HWPfChaDdrStDoneStatus);
+ /* Reset PHY/IDTM/UMMC */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 3);
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 2);
+ usleep(ACC100_MS_IN_US);
+ /* Reset WB and APB resets */
+ acc100_reg_write(d, HWPfChaDdrWbRstCfg, 2);
+ acc100_reg_write(d, HWPfChaDdrApbRstCfg, 3);
+ /* Configure PHY-IDTM */
+ acc100_reg_write(d, HWPfDdrPhyIdletimeout, 0x3e8);
+ /* IDTM timing registers */
+ acc100_reg_write(d, HWPfDdrPhyRdLatency, 0x13);
+ acc100_reg_write(d, HWPfDdrPhyRdLatencyDbi, 0x15);
+ acc100_reg_write(d, HWPfDdrPhyWrLatency, 0x10011);
+ /* Configure SDRAM MRS registers */
+ acc100_reg_write(d, HWPfDdrPhyMr01Dimm, 0x3030b70);
+ acc100_reg_write(d, HWPfDdrPhyMr01DimmDbi, 0x3030b50);
+ acc100_reg_write(d, HWPfDdrPhyMr23Dimm, 0x30);
+ acc100_reg_write(d, HWPfDdrPhyMr67Dimm, 0xc00);
+ acc100_reg_write(d, HWPfDdrPhyMr45Dimm, 0x4000000);
+ /* Configure active lanes */
+ acc100_reg_write(d, HWPfDdrPhyDqsCountMax, 0x9);
+ acc100_reg_write(d, HWPfDdrPhyDqsCountNum, 0x9);
+ /* Configure WR/RD leveling timing registers */
+ acc100_reg_write(d, HWPfDdrPhyWrlvlWwRdlvlRr, 0x101212);
+ /* Configure what trainings to execute */
+ acc100_reg_write(d, HWPfDdrPhyTrngType, 0x2d3c);
+ /* Releasing PHY reset */
+ acc100_reg_write(d, HWPfChaDdrPhyRstCfg, 3);
+ /* Configure Memory Controller registers */
+ acc100_reg_write(d, HWPfDdrMemInitPhyTrng0, 0x3);
+ acc100_reg_write(d, HWPfDdrBcDram, 0x3c232003);
+ acc100_reg_write(d, HWPfDdrBcAddrMap, 0x31);
+ /* Configure UMMC BC timing registers */
+ acc100_reg_write(d, HWPfDdrBcRef, 0xa22);
+ acc100_reg_write(d, HWPfDdrBcTim0, 0x4050501);
+ acc100_reg_write(d, HWPfDdrBcTim1, 0xf0b0476);
+ acc100_reg_write(d, HWPfDdrBcTim2, 0x103);
+ acc100_reg_write(d, HWPfDdrBcTim3, 0x144050a1);
+ acc100_reg_write(d, HWPfDdrBcTim4, 0x23300);
+ acc100_reg_write(d, HWPfDdrBcTim5, 0x4230276);
+ acc100_reg_write(d, HWPfDdrBcTim6, 0x857914);
+ acc100_reg_write(d, HWPfDdrBcTim7, 0x79100232);
+ acc100_reg_write(d, HWPfDdrBcTim8, 0x100007ce);
+ acc100_reg_write(d, HWPfDdrBcTim9, 0x50020);
+ acc100_reg_write(d, HWPfDdrBcTim10, 0x40ee);
+ /* Configure UMMC DFI timing registers */
+ acc100_reg_write(d, HWPfDdrDfiInit, 0x5000);
+ acc100_reg_write(d, HWPfDdrDfiTim0, 0x15030006);
+ acc100_reg_write(d, HWPfDdrDfiTim1, 0x11305);
+ acc100_reg_write(d, HWPfDdrDfiPhyUpdEn, 0x1);
+ acc100_reg_write(d, HWPfDdrUmmcIntEn, 0x1f);
+ /* Release IDTM CPU out of reset */
+ acc100_reg_write(d, HWPfChaDdrCpuRstCfg, 0x2);
+ /* Wait PHY-IDTM to finish static training */
+ for (i = 0; i < ACC100_DDR_TRAINING_MAX; i++) {
+ usleep(ACC100_MS_IN_US);
+ value = acc100_reg_read(d,
+ HWPfChaDdrStDoneStatus);
+ if (value & 1)
+ break;
+ }
+ printf("DDR Training completed in %d ms", i);
+ /* Enable Memory Controller */
+ acc100_reg_write(d, HWPfDdrUmmcCtrl, 0x401);
+ /* Release AXI interface reset */
+ acc100_reg_write(d, HWPfChaDdrSifRstCfg, 3);
+ }
+
rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
return 0;
}
diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index cbcece2..071b37c 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -31,11 +31,6 @@
#define RTE_ACC100_PF_DEVICE_ID (0x0d5c)
#define RTE_ACC100_VF_DEVICE_ID (0x0d5d)
-/* Define as 1 to use only a single FEC engine */ -#ifndef RTE_ACC100_SINGLE_FEC -#define RTE_ACC100_SINGLE_FEC 0 -#endif
-
/* Values used in filling in descriptors */
#define ACC100_DMA_DESC_TYPE 2
#define ACC100_DMA_CODE_BLK_MODE 0
@@ -153,6 +148,12 @@
#define ACC100_CFG_QMGR_HI_P 0x0F0F
#define ACC100_CFG_PCI_AXI 0xC003
#define ACC100_CFG_PCI_BRIDGE 0x40006033
+#define ACC100_QUAD_NUMS 4
+#define ACC100_LANES_PER_QUAD 4
+#define ACC100_PCIE_LANE_OFFSET 0x200
+#define ACC100_PCIE_QUAD_OFFSET 0x2000
+#define ACC100_PCS_EQ 0x6007
+#define ACC100_ADAPT 0x8400
#define ACC100_ENGINE_OFFSET 0x1000
#define ACC100_RESET_HI 0x20100
#define ACC100_RESET_LO 0x20000
@@ -160,6 +161,15 @@
#define ACC100_ENGINES_MAX 9
#define ACC100_LONG_WAIT 1000
#define ACC100_GPEX_AXIMAP_NUM 17
+#define ACC100_CLOCK_GATING_EN 0x30000
+#define ACC100_FABRIC_MODE 0xB
+/* DDR Size per VF - 512MB by default
+ * Can be increased up to 4 GB with single PF/VF */
+#define ACC100_HARQ_DDR (512 * 1)
+#define ACC100_PRQ_DDR_VER 0x10092020
+#define ACC100_MS_IN_US (1000)
+#define ACC100_DDR_TRAINING_MAX (5000)
/* ACC100 DMA Descriptor triplet */
struct acc100_dma_triplet {
--
1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (5 preceding siblings ...)
2022-05-31 22:31 ` [PATCH v7 6/6] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
@ 2022-06-06 14:54 ` Chautru, Nicolas
2022-06-06 15:03 ` Akhil Goyal
2022-06-15 14:08 ` [EXT] " Akhil Goyal
7 siblings, 1 reply; 84+ messages in thread
From: Chautru, Nicolas @ 2022-06-06 14:54 UTC (permalink / raw)
To: dev, gakhil, trix, maxime.coquelin
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
Hi Akhil,
Checking that this series on track to be applied. Let me know if anything required from our end.
> -----Original Message-----
> From: Chautru, Nicolas <nicolas.chautru@intel.com>
> Sent: Tuesday, May 31, 2022 3:32 PM
> To: dev@dpdk.org; gakhil@marvell.com; trix@redhat.com;
> maxime.coquelin@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com; Chautru, Nicolas
> <nicolas.chautru@intel.com>
> Subject: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101
> devices
>
> v7: updates suggested by Akhil and Maxime. Removed RTE prefix for internal
> #define, removed build-time single FEC engine configuration mode,
> documentation fix, coding guideline fix, renamed new file without rte prefix.
>
> v6: use formally an unified driver for AC100 and AC101. Exposing single
> unified function for the PF device configuration used by bbdev-test.
>
> v5: minor fix to doc and intermediate commit caught in CI
>
> v4: incremental updates based on reviews Changed order of patchset to
> include two ACC100 specific commits first: updating formally the companion
> configure function from PF and the protection adjustment.
> Then next 3 commits for the actual changes specific to ACC101: the device
> specific function for FCW 5GUL generation used as a local function,
> combined documentations into a single .rst common to both devices,
> updated comments, removed unused #defines.
>
> v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section
> calling the configure companion function for ACC100/101, taking the Pmon
> commit out which is not directly required.
>
> v2: Based on good feedback from Thomas and David, now implementing the
> ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to
> have different behaviour based on variant.
> This prevents code duplication and only rely on different functions and
> behaviour when hardware requires or support differences.
> Note that these are pending changes for ACC100 which would be specific to
> that device and not ACC101 but these can be managed based on the new
> implementation, ie. is_acc100() etc... (such incremental changes for ACC100
> trending 22.11 but confirming this is future proof).
> The serie also includes commits which were meant for ACC101 but are also
> valuable for ACC100.
>
> v1: This serie introduces the PMD for the new bbdev device ACC101 (aka
> Mount Cirrus).
> This is a derivative from previous Mount Bryce ACC100 which includes silicon
> improvement, bug fixes, capacity improvement for 5GNR and feature
> improvement.
>
>
> Nicolas Chautru (6):
> baseband/acc100: update companion PF configure function
> baseband/acc100: add protection for some negative scenario
> baseband/acc100: remove RTE prefix for internal macro
> baseband/acc100: introduce PMD for ACC101
> baseband/acc100: modify validation code for ACC101
> baseband/acc100: configuration of ACC101 from PF
>
> MAINTAINERS | 1 +
> app/test-bbdev/test_bbdev_perf.c | 6 +-
> doc/guides/bbdevs/acc100.rst | 37 +-
> doc/guides/bbdevs/features/acc101.ini | 13 +
> doc/guides/rel_notes/release_22_07.rst | 3 +
> drivers/baseband/acc100/acc100_pf_enum.h | 18 +
> drivers/baseband/acc100/acc101_pmd.h | 50 +++
> drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> drivers/baseband/acc100/rte_acc100_pmd.c | 687
> ++++++++++++++++++++++++++++---
> drivers/baseband/acc100/rte_acc100_pmd.h | 37 +-
> drivers/baseband/acc100/version.map | 3 +-
> 11 files changed, 768 insertions(+), 91 deletions(-) create mode 100644
> doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/acc101_pmd.h
>
> --
> 1.8.3.1
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-06-06 14:54 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Chautru, Nicolas
@ 2022-06-06 15:03 ` Akhil Goyal
2022-06-06 16:18 ` Chautru, Nicolas
0 siblings, 1 reply; 84+ messages in thread
From: Akhil Goyal @ 2022-06-06 15:03 UTC (permalink / raw)
To: Chautru, Nicolas, dev, trix, maxime.coquelin
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
[-- Attachment #1: Type: text/plain, Size: 4915 bytes --]
Hi Nicolas,
I wanted to take this in RC1 but I was unwell last couple of days. Can we push it to RC2? If not, please ask Thomas if he has time to pick it directly to main?
Regards,
Akhil
________________________________
From: Chautru, Nicolas <nicolas.chautru@intel.com>
Sent: Monday, 6 June, 2022, 8:24 pm
To: dev@dpdk.org <dev@dpdk.org>; Akhil Goyal <gakhil@marvell.com>; trix@redhat.com <trix@redhat.com>; maxime.coquelin@redhat.com <maxime.coquelin@redhat.com>
Cc: thomas@monjalon.net <thomas@monjalon.net>; Kinsella, Ray <ray.kinsella@intel.com>; Richardson, Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com <hemant.agrawal@nxp.com>; Vargas, Hernan <hernan.vargas@intel.com>; david.marchand@redhat.com <david.marchand@redhat.com>
Subject: [EXT] RE: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
External Email
----------------------------------------------------------------------
Hi Akhil,
Checking that this series on track to be applied. Let me know if anything required from our end.
> -----Original Message-----
> From: Chautru, Nicolas <nicolas.chautru@intel.com>
> Sent: Tuesday, May 31, 2022 3:32 PM
> To: dev@dpdk.org; gakhil@marvell.com; trix@redhat.com;
> maxime.coquelin@redhat.com
> Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>;
> Richardson, Bruce <bruce.richardson@intel.com>;
> hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>;
> david.marchand@redhat.com; Chautru, Nicolas
> <nicolas.chautru@intel.com>
> Subject: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101
> devices
>
> v7: updates suggested by Akhil and Maxime. Removed RTE prefix for internal
> #define, removed build-time single FEC engine configuration mode,
> documentation fix, coding guideline fix, renamed new file without rte prefix.
>
> v6: use formally an unified driver for AC100 and AC101. Exposing single
> unified function for the PF device configuration used by bbdev-test.
>
> v5: minor fix to doc and intermediate commit caught in CI
>
> v4: incremental updates based on reviews Changed order of patchset to
> include two ACC100 specific commits first: updating formally the companion
> configure function from PF and the protection adjustment.
> Then next 3 commits for the actual changes specific to ACC101: the device
> specific function for FCW 5GUL generation used as a local function,
> combined documentations into a single .rst common to both devices,
> updated comments, removed unused #defines.
>
> v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section
> calling the configure companion function for ACC100/101, taking the Pmon
> commit out which is not directly required.
>
> v2: Based on good feedback from Thomas and David, now implementing the
> ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to
> have different behaviour based on variant.
> This prevents code duplication and only rely on different functions and
> behaviour when hardware requires or support differences.
> Note that these are pending changes for ACC100 which would be specific to
> that device and not ACC101 but these can be managed based on the new
> implementation, ie. is_acc100() etc... (such incremental changes for ACC100
> trending 22.11 but confirming this is future proof).
> The serie also includes commits which were meant for ACC101 but are also
> valuable for ACC100.
>
> v1: This serie introduces the PMD for the new bbdev device ACC101 (aka
> Mount Cirrus).
> This is a derivative from previous Mount Bryce ACC100 which includes silicon
> improvement, bug fixes, capacity improvement for 5GNR and feature
> improvement.
>
>
> Nicolas Chautru (6):
> baseband/acc100: update companion PF configure function
> baseband/acc100: add protection for some negative scenario
> baseband/acc100: remove RTE prefix for internal macro
> baseband/acc100: introduce PMD for ACC101
> baseband/acc100: modify validation code for ACC101
> baseband/acc100: configuration of ACC101 from PF
>
> MAINTAINERS | 1 +
> app/test-bbdev/test_bbdev_perf.c | 6 +-
> doc/guides/bbdevs/acc100.rst | 37 +-
> doc/guides/bbdevs/features/acc101.ini | 13 +
> doc/guides/rel_notes/release_22_07.rst | 3 +
> drivers/baseband/acc100/acc100_pf_enum.h | 18 +
> drivers/baseband/acc100/acc101_pmd.h | 50 +++
> drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> drivers/baseband/acc100/rte_acc100_pmd.c | 687
> ++++++++++++++++++++++++++++---
> drivers/baseband/acc100/rte_acc100_pmd.h | 37 +-
> drivers/baseband/acc100/version.map | 3 +-
> 11 files changed, 768 insertions(+), 91 deletions(-) create mode 100644
> doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/acc101_pmd.h
>
> --
> 1.8.3.1
[-- Attachment #2: Type: text/html, Size: 7152 bytes --]
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-06-06 15:03 ` Akhil Goyal
@ 2022-06-06 16:18 ` Chautru, Nicolas
0 siblings, 0 replies; 84+ messages in thread
From: Chautru, Nicolas @ 2022-06-06 16:18 UTC (permalink / raw)
To: Akhil Goyal, dev, trix, maxime.coquelin
Cc: thomas, Kinsella, Ray, Richardson, Bruce, hemant.agrawal, Vargas,
Hernan, david.marchand
[-- Attachment #1: Type: text/plain, Size: 6370 bytes --]
Thanks Akhil for your reply. It should be okay to apply it after rc1 once you feel better.
Thanks
Nic
From: Akhil Goyal <gakhil@marvell.com>
Sent: Monday, June 6, 2022 8:04 AM
To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org; trix@redhat.com; maxime.coquelin@redhat.com
Cc: thomas@monjalon.net; Kinsella, Ray <ray.kinsella@intel.com>; Richardson, Bruce <bruce.richardson@intel.com>; hemant.agrawal@nxp.com; Vargas, Hernan <hernan.vargas@intel.com>; david.marchand@redhat.com
Subject: Re: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
Hi Nicolas,
I wanted to take this in RC1 but I was unwell last couple of days. Can we push it to RC2? If not, please ask Thomas if he has time to pick it directly to main?
Regards,
Akhil
________________________________
From: Chautru, Nicolas <nicolas.chautru@intel.com<mailto:nicolas.chautru@intel.com>>
Sent: Monday, 6 June, 2022, 8:24 pm
To: dev@dpdk.org<mailto:dev@dpdk.org> <dev@dpdk.org<mailto:dev@dpdk.org>>; Akhil Goyal <gakhil@marvell.com<mailto:gakhil@marvell.com>>; trix@redhat.com<mailto:trix@redhat.com> <trix@redhat.com<mailto:trix@redhat.com>>; maxime.coquelin@redhat.com<mailto:maxime.coquelin@redhat.com> <maxime.coquelin@redhat.com<mailto:maxime.coquelin@redhat.com>>
Cc: thomas@monjalon.net<mailto:thomas@monjalon.net> <thomas@monjalon.net<mailto:thomas@monjalon.net>>; Kinsella, Ray <ray.kinsella@intel.com<mailto:ray.kinsella@intel.com>>; Richardson, Bruce <bruce.richardson@intel.com<mailto:bruce.richardson@intel.com>>; hemant.agrawal@nxp.com<mailto:hemant.agrawal@nxp.com> <hemant.agrawal@nxp.com<mailto:hemant.agrawal@nxp.com>>; Vargas, Hernan <hernan.vargas@intel.com<mailto:hernan.vargas@intel.com>>; david.marchand@redhat.com<mailto:david.marchand@redhat.com> <david.marchand@redhat.com<mailto:david.marchand@redhat.com>>
Subject: [EXT] RE: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
External Email
----------------------------------------------------------------------
Hi Akhil,
Checking that this series on track to be applied. Let me know if anything required from our end.
> -----Original Message-----
> From: Chautru, Nicolas <nicolas.chautru@intel.com<mailto:nicolas.chautru@intel.com>>
> Sent: Tuesday, May 31, 2022 3:32 PM
> To: dev@dpdk.org<mailto:dev@dpdk.org>; gakhil@marvell.com<mailto:gakhil@marvell.com>; trix@redhat.com<mailto:trix@redhat.com>;
> maxime.coquelin@redhat.com<mailto:maxime.coquelin@redhat.com>
> Cc: thomas@monjalon.net<mailto:thomas@monjalon.net>; Kinsella, Ray <ray.kinsella@intel.com<mailto:ray.kinsella@intel.com>>;
> Richardson, Bruce <bruce.richardson@intel.com<mailto:bruce.richardson@intel.com>>;
> hemant.agrawal@nxp.com<mailto:hemant.agrawal@nxp.com>; Vargas, Hernan <hernan.vargas@intel.com<mailto:hernan.vargas@intel.com>>;
> david.marchand@redhat.com<mailto:david.marchand@redhat.com>; Chautru, Nicolas
> <nicolas.chautru@intel.com<mailto:nicolas.chautru@intel.com>>
> Subject: [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101
> devices
>
> v7: updates suggested by Akhil and Maxime. Removed RTE prefix for internal
> #define, removed build-time single FEC engine configuration mode,
> documentation fix, coding guideline fix, renamed new file without rte prefix.
>
> v6: use formally an unified driver for AC100 and AC101. Exposing single
> unified function for the PF device configuration used by bbdev-test.
>
> v5: minor fix to doc and intermediate commit caught in CI
>
> v4: incremental updates based on reviews Changed order of patchset to
> include two ACC100 specific commits first: updating formally the companion
> configure function from PF and the protection adjustment.
> Then next 3 commits for the actual changes specific to ACC101: the device
> specific function for FCW 5GUL generation used as a local function,
> combined documentations into a single .rst common to both devices,
> updated comments, removed unused #defines.
>
> v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section
> calling the configure companion function for ACC100/101, taking the Pmon
> commit out which is not directly required.
>
> v2: Based on good feedback from Thomas and David, now implementing the
> ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to
> have different behaviour based on variant.
> This prevents code duplication and only rely on different functions and
> behaviour when hardware requires or support differences.
> Note that these are pending changes for ACC100 which would be specific to
> that device and not ACC101 but these can be managed based on the new
> implementation, ie. is_acc100() etc... (such incremental changes for ACC100
> trending 22.11 but confirming this is future proof).
> The serie also includes commits which were meant for ACC101 but are also
> valuable for ACC100.
>
> v1: This serie introduces the PMD for the new bbdev device ACC101 (aka
> Mount Cirrus).
> This is a derivative from previous Mount Bryce ACC100 which includes silicon
> improvement, bug fixes, capacity improvement for 5GNR and feature
> improvement.
>
>
> Nicolas Chautru (6):
> baseband/acc100: update companion PF configure function
> baseband/acc100: add protection for some negative scenario
> baseband/acc100: remove RTE prefix for internal macro
> baseband/acc100: introduce PMD for ACC101
> baseband/acc100: modify validation code for ACC101
> baseband/acc100: configuration of ACC101 from PF
>
> MAINTAINERS | 1 +
> app/test-bbdev/test_bbdev_perf.c | 6 +-
> doc/guides/bbdevs/acc100.rst | 37 +-
> doc/guides/bbdevs/features/acc101.ini | 13 +
> doc/guides/rel_notes/release_22_07.rst | 3 +
> drivers/baseband/acc100/acc100_pf_enum.h | 18 +
> drivers/baseband/acc100/acc101_pmd.h | 50 +++
> drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> drivers/baseband/acc100/rte_acc100_pmd.c | 687
> ++++++++++++++++++++++++++++---
> drivers/baseband/acc100/rte_acc100_pmd.h | 37 +-
> drivers/baseband/acc100/version.map | 3 +-
> 11 files changed, 768 insertions(+), 91 deletions(-) create mode 100644
> doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/acc101_pmd.h
>
> --
> 1.8.3.1
[-- Attachment #2: Type: text/html, Size: 11517 bytes --]
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [EXT] [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
` (6 preceding siblings ...)
2022-06-06 14:54 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Chautru, Nicolas
@ 2022-06-15 14:08 ` Akhil Goyal
2022-06-22 11:50 ` Akhil Goyal
7 siblings, 1 reply; 84+ messages in thread
From: Akhil Goyal @ 2022-06-15 14:08 UTC (permalink / raw)
To: Nicolas Chautru, dev, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
> v7: updates suggested by Akhil and Maxime. Removed RTE prefix for internal
> #define, removed
> build-time single FEC engine configuration mode, documentation fix, coding
> guideline fix, renamed new file without rte prefix.
>
> v6: use formally an unified driver for AC100 and AC101. Exposing single unified
> function for the PF device configuration used by bbdev-test.
>
> v5: minor fix to doc and intermediate commit caught in CI
>
> v4: incremental updates based on reviews Changed order of patchset to include
> two ACC100 specific commits first: updating formally the companion configure
> function from PF and the protection adjustment.
> Then next 3 commits for the actual changes specific to ACC101: the device
> specific function for FCW 5GUL generation used as a local function, combined
> documentations into a single .rst common to both devices, updated comments,
> removed unused #defines.
>
> v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section
> calling the configure companion function for ACC100/101, taking the Pmon
> commit out which is not directly required.
>
> v2: Based on good feedback from Thomas and David, now implementing the
> ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to
> have different behaviour based on variant.
> This prevents code duplication and only rely on different functions and
> behaviour when hardware requires or support differences.
> Note that these are pending changes for ACC100 which would be specific to that
> device and not ACC101 but these can be managed based on the new
> implementation, ie. is_acc100() etc... (such incremental changes for ACC100
> trending 22.11 but confirming this is future proof).
> The serie also includes commits which were meant for ACC101 but are also
> valuable for ACC100.
>
> v1: This serie introduces the PMD for the new bbdev device ACC101 (aka Mount
> Cirrus).
> This is a derivative from previous Mount Bryce ACC100 which includes silicon
> improvement, bug fixes, capacity improvement for 5GNR and feature
> improvement.
>
>
> Nicolas Chautru (6):
> baseband/acc100: update companion PF configure function
> baseband/acc100: add protection for some negative scenario
> baseband/acc100: remove RTE prefix for internal macro
> baseband/acc100: introduce PMD for ACC101
> baseband/acc100: modify validation code for ACC101
> baseband/acc100: configuration of ACC101 from PF
>
> MAINTAINERS | 1 +
> app/test-bbdev/test_bbdev_perf.c | 6 +-
> doc/guides/bbdevs/acc100.rst | 37 +-
> doc/guides/bbdevs/features/acc101.ini | 13 +
> doc/guides/rel_notes/release_22_07.rst | 3 +
> drivers/baseband/acc100/acc100_pf_enum.h | 18 +
> drivers/baseband/acc100/acc101_pmd.h | 50 +++
> drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> drivers/baseband/acc100/rte_acc100_pmd.c | 687
> ++++++++++++++++++++++++++++---
> drivers/baseband/acc100/rte_acc100_pmd.h | 37 +-
> drivers/baseband/acc100/version.map | 3 +-
> 11 files changed, 768 insertions(+), 91 deletions(-)
> create mode 100644 doc/guides/bbdevs/features/acc101.ini
> create mode 100644 drivers/baseband/acc100/acc101_pmd.h
Series applied to dpdk-next-crypto
Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread
* RE: [EXT] [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices
2022-06-15 14:08 ` [EXT] " Akhil Goyal
@ 2022-06-22 11:50 ` Akhil Goyal
0 siblings, 0 replies; 84+ messages in thread
From: Akhil Goyal @ 2022-06-22 11:50 UTC (permalink / raw)
To: Akhil Goyal, Nicolas Chautru, dev, trix, maxime.coquelin
Cc: thomas, ray.kinsella, bruce.richardson, hemant.agrawal,
hernan.vargas, david.marchand
Hi Nicolas,
Please submit a patch for renaming rte_acc100_pmd.h to acc100_pmd.h
as it is an internal file.
>
> > v7: updates suggested by Akhil and Maxime. Removed RTE prefix for internal
> > #define, removed
> > build-time single FEC engine configuration mode, documentation fix, coding
> > guideline fix, renamed new file without rte prefix.
> >
> > v6: use formally an unified driver for AC100 and AC101. Exposing single unified
> > function for the PF device configuration used by bbdev-test.
> >
> > v5: minor fix to doc and intermediate commit caught in CI
> >
> > v4: incremental updates based on reviews Changed order of patchset to
> include
> > two ACC100 specific commits first: updating formally the companion configure
> > function from PF and the protection adjustment.
> > Then next 3 commits for the actual changes specific to ACC101: the device
> > specific function for FCW 5GUL generation used as a local function, combined
> > documentations into a single .rst common to both devices, updated
> comments,
> > removed unused #defines.
> >
> > v3: Feedback from Tom Rix: missing copyright, refactor bbdev-test section
> > calling the configure companion function for ACC100/101, taking the Pmon
> > commit out which is not directly required.
> >
> > v2: Based on good feedback from Thomas and David, now implementing the
> > ACC101 PMD as a close derivative from existing ACC100 PMD with hooks to
> > have different behaviour based on variant.
> > This prevents code duplication and only rely on different functions and
> > behaviour when hardware requires or support differences.
> > Note that these are pending changes for ACC100 which would be specific to
> that
> > device and not ACC101 but these can be managed based on the new
> > implementation, ie. is_acc100() etc... (such incremental changes for ACC100
> > trending 22.11 but confirming this is future proof).
> > The serie also includes commits which were meant for ACC101 but are also
> > valuable for ACC100.
> >
> > v1: This serie introduces the PMD for the new bbdev device ACC101 (aka
> Mount
> > Cirrus).
> > This is a derivative from previous Mount Bryce ACC100 which includes silicon
> > improvement, bug fixes, capacity improvement for 5GNR and feature
> > improvement.
> >
> >
> > Nicolas Chautru (6):
> > baseband/acc100: update companion PF configure function
> > baseband/acc100: add protection for some negative scenario
> > baseband/acc100: remove RTE prefix for internal macro
> > baseband/acc100: introduce PMD for ACC101
> > baseband/acc100: modify validation code for ACC101
> > baseband/acc100: configuration of ACC101 from PF
> >
> > MAINTAINERS | 1 +
> > app/test-bbdev/test_bbdev_perf.c | 6 +-
> > doc/guides/bbdevs/acc100.rst | 37 +-
> > doc/guides/bbdevs/features/acc101.ini | 13 +
> > doc/guides/rel_notes/release_22_07.rst | 3 +
> > drivers/baseband/acc100/acc100_pf_enum.h | 18 +
> > drivers/baseband/acc100/acc101_pmd.h | 50 +++
> > drivers/baseband/acc100/rte_acc100_cfg.h | 4 +-
> > drivers/baseband/acc100/rte_acc100_pmd.c | 687
> > ++++++++++++++++++++++++++++---
> > drivers/baseband/acc100/rte_acc100_pmd.h | 37 +-
> > drivers/baseband/acc100/version.map | 3 +-
> > 11 files changed, 768 insertions(+), 91 deletions(-)
> > create mode 100644 doc/guides/bbdevs/features/acc101.ini
> > create mode 100644 drivers/baseband/acc100/acc101_pmd.h
>
> Series applied to dpdk-next-crypto
>
> Thanks.
^ permalink raw reply [flat|nested] 84+ messages in thread
end of thread, other threads:[~2022-06-22 11:50 UTC | newest]
Thread overview: 84+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-27 18:16 [PATCH v2 0/5] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-04-27 18:16 ` [PATCH v2 1/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-08 13:02 ` Tom Rix
2022-05-09 21:23 ` Chautru, Nicolas
2022-05-10 8:52 ` Thomas Monjalon
2022-05-10 11:55 ` Tom Rix
2022-05-23 17:53 ` Chautru, Nicolas
2022-04-27 18:17 ` [PATCH v2 2/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-08 13:07 ` Tom Rix
2022-05-09 21:27 ` Chautru, Nicolas
2022-04-27 18:17 ` [PATCH v2 3/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-08 13:38 ` Tom Rix
2022-05-09 21:36 ` Chautru, Nicolas
2022-05-10 12:02 ` Tom Rix
2022-04-27 18:17 ` [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD Nicolas Chautru
2022-05-08 13:44 ` Tom Rix
2022-05-09 22:07 ` Chautru, Nicolas
2022-04-27 18:17 ` [PATCH v2 5/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-08 13:55 ` Tom Rix
2022-05-09 21:45 ` Chautru, Nicolas
2022-05-10 12:11 ` Tom Rix
2022-05-10 14:44 ` Thomas Monjalon
2022-05-16 20:48 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 1/4] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-19 19:55 ` Maxime Coquelin
2022-05-16 20:48 ` [PATCH v3 2/4] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-16 20:48 ` [PATCH v3 3/4] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-19 20:13 ` Maxime Coquelin
2022-05-23 17:06 ` Chautru, Nicolas
2022-05-16 20:48 ` [PATCH v3 4/4] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-19 19:51 ` [PATCH v3 0/4] drivers/baseband: PMD to support ACC101 device Tom Rix
2022-05-23 21:25 ` [PATCH v4 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-23 21:25 ` [PATCH v4 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-24 0:08 ` [PATCH v5 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-25 14:33 ` Maxime Coquelin
2022-05-25 22:15 ` Chautru, Nicolas
2022-05-31 7:59 ` Maxime Coquelin
2022-05-31 18:19 ` Chautru, Nicolas
2022-05-24 0:08 ` [PATCH v5 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-25 13:24 ` Maxime Coquelin
2022-05-25 22:09 ` Chautru, Nicolas
2022-05-26 0:49 ` [PATCH v6 0/5] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-26 0:55 ` Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 1/5] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 2/5] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-05-26 0:55 ` [PATCH v6 3/5] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-05-30 7:40 ` [EXT] " Akhil Goyal
2022-05-31 18:59 ` Chautru, Nicolas
2022-05-26 0:55 ` [PATCH v6 4/5] baseband/acc100: modify validation code " Nicolas Chautru
2022-05-31 8:02 ` Maxime Coquelin
2022-05-31 18:16 ` Chautru, Nicolas
2022-05-26 0:55 ` [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-05-31 7:35 ` Maxime Coquelin
2022-05-31 18:28 ` Chautru, Nicolas
2022-05-31 22:31 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Nicolas Chautru
2022-05-31 22:31 ` [PATCH v7 1/6] baseband/acc100: update companion PF configure function Nicolas Chautru
2022-06-02 9:49 ` Kevin Traynor
2022-06-02 16:52 ` Chautru, Nicolas
2022-06-03 20:25 ` Vargas, Hernan
2022-05-31 22:31 ` [PATCH v7 2/6] baseband/acc100: add protection for some negative scenario Nicolas Chautru
2022-06-02 8:21 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 3/6] baseband/acc100: remove RTE prefix for internal macro Nicolas Chautru
2022-06-01 14:11 ` Maxime Coquelin
2022-06-01 17:15 ` [EXT] " Akhil Goyal
2022-06-02 12:57 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 4/6] baseband/acc100: introduce PMD for ACC101 Nicolas Chautru
2022-06-02 12:23 ` Maxime Coquelin
2022-05-31 22:31 ` [PATCH v7 5/6] baseband/acc100: modify validation code " Nicolas Chautru
2022-06-03 20:23 ` Vargas, Hernan
2022-05-31 22:31 ` [PATCH v7 6/6] baseband/acc100: configuration of ACC101 from PF Nicolas Chautru
2022-06-02 8:33 ` Maxime Coquelin
2022-06-06 14:54 ` [PATCH v7 0/6] drivers/baseband: PMD to support ACC100/ACC101 devices Chautru, Nicolas
2022-06-06 15:03 ` Akhil Goyal
2022-06-06 16:18 ` Chautru, Nicolas
2022-06-15 14:08 ` [EXT] " Akhil Goyal
2022-06-22 11:50 ` Akhil Goyal
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