From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC6BB4401D; Mon, 13 May 2024 20:12:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 83BF4402F1; Mon, 13 May 2024 20:12:39 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by mails.dpdk.org (Postfix) with ESMTP id 98830402CD for ; Mon, 13 May 2024 20:12:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715623957; x=1747159957; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=losr4jg/8BuIoekd4C5IhnI2fVw1/EML3EEgZ619DEQ=; b=P0hZXV7Epo9Q+iRWmAJo/4fOmZgaOjxq/b0ejXBNTvUChK0kOA7sKREd a504h9DsiOXLjqJe+yw2IvPYY7BMC+o8EuJCftdQ7nSQebWvo3onxHebV GcOdbUiWa9QQIKg4QDnKXHFbD6bFloqAlvsR/6TcVU4SipaKLfegFzA0Q nfz2D8PPhZ3C7X9Te3fU0yKIaUqP39erMF36E4wiPgcYEo8s8My8GYd4Q grDEVEUy+0jMhr8qzV5EKnsT3AhRjBR08LJrGBqsMgBXuYSF5tuzw/t6t PQkHrG5RWn5/V/FOe7JWAUFMkHHSfscqvCRgI420uyCK1UXNMqBNbyjkD w==; X-CSE-ConnectionGUID: 2T5GwLFZT8KYLUC54Di9gQ== X-CSE-MsgGUID: 5yMYUhIbQ/OaDck0gfMW3w== X-IronPort-AV: E=McAfee;i="6600,9927,11072"; a="11502452" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="11502452" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2024 11:12:36 -0700 X-CSE-ConnectionGUID: INChcynzSp2S0djaOvKKUg== X-CSE-MsgGUID: sURsSM7ETZmVCnCBV4xJHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="67888963" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by orviesa001.jf.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 13 May 2024 11:12:35 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 13 May 2024 11:12:35 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 13 May 2024 11:12:35 -0700 Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Mon, 13 May 2024 11:12:35 -0700 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.101) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Mon, 13 May 2024 11:12:35 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A0j/9sW7OlSzum0kLIwnd06kxBJakfvu6IM+KmrQiy5bMUUYSgeusw55nIv5TNx25mTHZLnQeOqg0In+ldQlP+b5+hAIeQFrgzbWtVhePtkMpioVUFfuFDkM9CX9GAyQLQt5X+CQJAElWz1Q1ZN6qMoEpuJPXceQ3P5CeFTq85KH3RrEBuDCuW2Dw8oY8TecJua8c7F9f4XNd/ow62qPgKUm9kdvUXO3Q/bDFojnDJKtOV4rPh7FLe6F4WZ73B2mkEPnmzRCwbbX93VRkopBKXCCxJVhzxi4SafQv6nIjSW/filqUKQjeaCBB77wMxj+bloWaEiON9e8ama/PwWHxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vD4tFd3V3yKnAV6imDV84l2HkGkfwWbVNol/J53gzrc=; b=JViSaiTheVUJuaQ/SZOISuvv2JLxXia8afj2oPu6umQYCGduAkptei6G3y6Oy9EsWiiP5dAmyt0IyejNe2FLCe8hvYLzYaXsnyBZECpeSWRK3epW1liggSIJ9ld4QllxNGejSxKw7EZ4szT2TsgpnNeK6TAwzhkgq4PmZextUCUAFZ6nI7XOlO8TMmI6m/dUxAoN4gqcaS+45nDDnjfanPSam4zKjilIOtIjiwg5D0ZYc+B+ARmOaE3UCGIRdfrkDsY/vyfepE9g/aTYAAGZAwyuLkn3u1RdZApTSJJUQ6DNvxa8PEOrtMIwwcMI97jkhegiUF+VSHhKRBYZSzl4kQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from BY5PR11MB4451.namprd11.prod.outlook.com (2603:10b6:a03:1cb::30) by IA1PR11MB6171.namprd11.prod.outlook.com (2603:10b6:208:3e9::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.55; Mon, 13 May 2024 18:12:30 +0000 Received: from BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::c72:a3ac:7e77:c14a]) by BY5PR11MB4451.namprd11.prod.outlook.com ([fe80::c72:a3ac:7e77:c14a%4]) with mapi id 15.20.7544.052; Mon, 13 May 2024 18:12:30 +0000 From: "Chautru, Nicolas" To: Tyler Retzlaff , "dev@dpdk.org" CC: =?iso-8859-1?Q?Mattias_R=F6nnblom?= , =?iso-8859-1?Q?Morten_Br=F8rup?= , "Sevincer, Abdullah" , Ajit Khaparde , Alok Prasad , "Burakov, Anatoly" , Andrew Rybchenko , Anoob Joseph , "Richardson, Bruce" , "Marohn, Byron" , Chenbo Xia , Chengwen Feng , "Loftus, Ciara" , "Power, Ciara" , Dariusz Sosnowski , "Hunt, David" , Devendra Singh Rawat , "Carrillo, Erik G" , Guoyang Zhou , Harman Kalra , "Van Haaren, Harry" , "Nagarahalli, Honnappa" , Jakub Grajciar , "Jerin Jacob" , Jeroen de Borst , Jian Wang , Jiawen Wu , Jie Hai , "Wu, Jingjing" , "Joshua Washington" , Joyce Kong , "Guo, Junfeng" , "Laatz, Kevin" , Konstantin Ananyev , Liang Ma , Long Li , Maciej Czekaj , Matan Azrad , Maxime Coquelin , Ori Kam , Pavan Nikhilesh , "Mccarthy, Peter" , Rahul Lakkireddy , "Pattan, Reshma" , "Xu, Rosen" , Ruifeng Wang , Rushil Gupta , "Gobriel, Sameh" , Sivaprasad Tummala , Somnath Kotur , Stephen Hemminger , Suanming Mou , "Sunil Kumar Kori" , Sunil Uttarwar , Tetsuya Mukawa , Vamsi Attunuru , Viacheslav Ovsiienko , "Medvedkin, Vladimir" , Xiaoyun Wang , "Wang, Yipeng1" , Yisen Zhuang , Ziyang Xuan Subject: RE: [PATCH v5 31/45] baseband/acc: use rte stdatomic API Thread-Topic: [PATCH v5 31/45] baseband/acc: use rte stdatomic API Thread-Index: AQHan98O9+9QGg6ilkCIPbiM/aXLcrGVgcBA Date: Mon, 13 May 2024 18:12:30 +0000 Message-ID: References: <1710967892-7046-1-git-send-email-roretzla@linux.microsoft.com> <1715018306-13741-1-git-send-email-roretzla@linux.microsoft.com> <1715018306-13741-32-git-send-email-roretzla@linux.microsoft.com> In-Reply-To: <1715018306-13741-32-git-send-email-roretzla@linux.microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BY5PR11MB4451:EE_|IA1PR11MB6171:EE_ x-ms-office365-filtering-correlation-id: 8c963433-55b1-410a-e271-08dc73784102 x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230031|7416005|1800799015|366007|376005|38070700009; x-microsoft-antispam-message-info: =?iso-8859-1?Q?HcctktY3WRRBCOcYM9HgtfAzT1LHxu0JAQ7vhfanpMXPTOAuNGpIXrqJ6g?= =?iso-8859-1?Q?LYcg0YdHwW5pVK+TYsYnLYh1Boj5Sepy9AcT5p0liOasMiRwNUoSnPCSkt?= =?iso-8859-1?Q?HixGt/r9SZE2NICnvETSNGQzpd74dQee08La1uGOqLaFSNidQre8vcosia?= =?iso-8859-1?Q?RIYkrex3iSvX7IDq+1ssG5Dcec6rI1htThNal//mDRHDXvWQ65vml8g3Hl?= =?iso-8859-1?Q?FRePcufJNj+ltdKRFadJhazsjvLNLcCN9DTyAL7ELxPb6NnivM0fhAFscH?= =?iso-8859-1?Q?ZlWvssNA2MLvpjCH2t6TJHQERBN86e6pyig5RRAdowWa9VvIv1Xhuwavtu?= =?iso-8859-1?Q?TK+qYMWgue/doczTlcXsc/f8DobBHMer6CkMno9qioP08bxpQGNyUZA8JV?= =?iso-8859-1?Q?HCjx7QOkZEfsSqf68JlqYS5YovjYQ/OxiGNLx9a99ni3LEyxTrjPy7Nqrw?= =?iso-8859-1?Q?P9Qsatu9eJrJxjMOPzgKMeaiaNDaY82vdZXHWx4UZo16mzEJ0OMCJAF1G+?= =?iso-8859-1?Q?aOjBvY3NyqVaXlLGcP/9wn6UGRsQA441rVbxIUatC153fJwHwLXdZTwYGh?= =?iso-8859-1?Q?f/h2Y+Fxk/bJvnmUbPntm2ufub3nnBw9OL2N3B6TF2OV/pBdnjwrQDT9y/?= =?iso-8859-1?Q?savVYYOt82486+P/PKW8imgqyW2pdQ3QfM5kqOkI/jNM1/2d6Q1HXyF9tY?= =?iso-8859-1?Q?icZnXVV+dNEAPmZRFS142cp810D/8b/VFL7Ds5A0YiF0hWC36ukHybg1GW?= =?iso-8859-1?Q?I8lH9ig/DhAC9Yq4D9KsYy7qHNS1I/qqaVAY/k/nogICUUsDl4wmtbzjTk?= =?iso-8859-1?Q?o0J/gChuB82np6PqJxdWWMLc0v8OnVmzsGFNPeNDDscwpug6vEVwLDUqA+?= =?iso-8859-1?Q?q+jVqZxWXgmQhvo/o+KAAD7qJhSPSa92BmOMK6jLFtSkznukxTBxsz+gNG?= =?iso-8859-1?Q?uyQ3ihwUtXSUzL7iFb+lTUKcY3abBWFNqLDT5p+q0txhwcl0vC3ByNwdJs?= =?iso-8859-1?Q?XX3TMdfZ72V2FB9rDrhrJtE6dULKRHtCjpUUYkhywoh/H7ozU9oXqyFnzT?= =?iso-8859-1?Q?rGF+Sy/mAE0+D00iFUpniDJJ8RdJgdTocNd4KK7Cdq39RPqWOCwXuE0JAp?= =?iso-8859-1?Q?8LOAmbCcPYvKNu9BCrQzX2w+pGtRYqxMPbV/wh910j0tpnkVPlK/7WzWA5?= =?iso-8859-1?Q?8cX+kI7KRSpMYiyVT8JCV2x3F6hut54C8ufyonesQiU0C3uxNw81whSCNR?= =?iso-8859-1?Q?0W3tgpT+QH0z3fCsTbASmf3o+VJMAoWuWgiDFIIcVN/W9CKp3423AnQ6x5?= =?iso-8859-1?Q?61LgmqaWgr85t2isKzbFNljkIdXHH0ZQ2kTkQzymRAHBan37SXJ38NB97S?= =?iso-8859-1?Q?V0MgjlB0ZWg8v6NnBD6zPywhgan+GBwQ=3D=3D?= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BY5PR11MB4451.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(7416005)(1800799015)(366007)(376005)(38070700009); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?Q?yRXWmU3ushK+RdGULs+ed3Jq09lUWSU6DBhrAdlyl723zlNCvwpW93BLF3?= =?iso-8859-1?Q?PkBESuR2AEbBxzD0EdP27XcBob/tHF38p8NYJDj89Rn3yUoEiFeZtMJsHP?= =?iso-8859-1?Q?HAshQDJxls2GQrrlThYhTxDwIYCU9a8YITH8suxqG4NX4auGtZ0DXAuDFg?= =?iso-8859-1?Q?5mj0NN9yEwDGcEsvCR4k7x4qjX7bpdQBW6+bIkU0JWfqvhcMnqEKXOmIxw?= =?iso-8859-1?Q?5zOUIJ10w2CYQbjMtnn3sUtLtNJgdd8rXNFtKwhKi0xYjOrfYRLvGVSLiq?= =?iso-8859-1?Q?5dSseCrncFNqbrF83yljR0KZsuWePP7/Zi3lnnNqOo/mgi7Yb6r7jKc43z?= =?iso-8859-1?Q?lfceMRPkecBHqqma2C/X8kjnErJl7Ci8EC5vAlf3DzZ27afpOhNodZlwwx?= =?iso-8859-1?Q?aYUiITsOdIZ2cfT1DjRueubWxvZOr1V43yXB/B9LbISV2nndW229YE7tNl?= =?iso-8859-1?Q?tIrB/u0kocT7FbEMujv2ubgYWcWHDdiPWq1nF4CWf1Xwf3TLW3iXmYuu3R?= =?iso-8859-1?Q?6RWGHb/ukO9a5iXdQqQKJG1bvq9V+oPxT4JkNv7l6M2p1tUMIg2MuXYiYT?= =?iso-8859-1?Q?mAE2NrelsVFaNsHMyP+1wMb453JRAoIekEN31U37hADoLaYJjwdW8owR48?= =?iso-8859-1?Q?f//1G71yYSITRN6/i0DOxFA4Smx7COE6mEZpur0U7HSJKE5oRfnq8gn4lW?= =?iso-8859-1?Q?j9LP4K9dOi0zJQuE6vVZ0DxOQJjv3pAPjGeoP7qSj00Pc++EwrfttZqlZI?= =?iso-8859-1?Q?9bWGuf4xaxsX7gEq86v5z2PzMyl9IbuipLESzp4xRDtfWQ8dW0PJYZnZrg?= =?iso-8859-1?Q?xjwHWmeTUVTCMSQzhl8cvwDrT/qkmJySaYG6iYmI5z/eNC0quuEZEAAG3W?= =?iso-8859-1?Q?9+OSjtt3d37rL6WRMMBZjRgOlf7iyl8RNnDwmGmxIZUYBoGPn0u8UuskTM?= =?iso-8859-1?Q?O7Dv/QmTBi9kHf9eWz4zXUT0uZYuyMw8Mb17TSehKwSrVv0jAaVk5ir+Yp?= =?iso-8859-1?Q?Wp6rNInq6BrdRxcBLYH5w9HeodCQeT6qtz2dKw1iS46VZtS6xhgdO1DjCC?= =?iso-8859-1?Q?Yq80Nf1wOKBVzH+soAAkOvYI1p2CsE8AYTPvOsZ2FFFS+alFMQ+RbWMQ4/?= =?iso-8859-1?Q?LEjMkz+OApIWcG7496hX1L1QcL8poVwJDb8YFu+l79CJzb60Ori4aDOVII?= =?iso-8859-1?Q?XYB0yN/L8SK0/saqyxGc8BfpV+URyqZOf4ABl8MNzbJ2LPIDkY0K5oX+SP?= =?iso-8859-1?Q?6e5KgVLrozNb1Dhak88OHxQ/RvAmCNsHIOVJQyfRzSE0+iwJ7/9Q3GtH67?= =?iso-8859-1?Q?d0FIOqW6ibS2W7tgRT9pxDjGhLBafQFWvDjV2++9R7/Go0mniFNUmlc8eX?= =?iso-8859-1?Q?Ow5881ywPii8vGYBx1TfnQ2KBmp0i1pOKHKAv/6h0pFyxk3wMZQANttxtR?= =?iso-8859-1?Q?hD7od/dnAyt06bpzscoTQVNjBJ3pns7Voaxy/qOjd5y26ADX9btOaUJhPQ?= =?iso-8859-1?Q?cbVwaSei2kcUFhxCKQXTeTWaQVM2m72U7Uu4Pgq3dhgziYyAhiaJivD3r7?= =?iso-8859-1?Q?EKVaMxSlJCCwRmNFYPj5sXD0sNBjCCWn4MKq1LpXbG4sODZVrhZEyPICHT?= =?iso-8859-1?Q?Km1Be4fASxWLS9pSjXnuY2kzii4lGwz2/v?= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4451.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8c963433-55b1-410a-e271-08dc73784102 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 May 2024 18:12:30.3513 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +c363STOTtcuudVBDjWPq0d10RrG+7JeDo/t2H+TzBOH9DwXnG8xwNDfSmKsDhc1lVqwRoCfaXqqRqgJ13SIHxlJBJLbz8CrVBZeKh12XMk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB6171 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Tyler,=20 Still some issues with indentation when the sed is causing split across 2 l= ines.=20 Please fix indentation, nack like that.=20 Thanks Nic > -----Original Message----- > From: Tyler Retzlaff > Sent: Monday, May 6, 2024 10:58 AM > To: dev@dpdk.org > Cc: Mattias R=F6nnblom ; Morten Br=F8rup > ; Sevincer, Abdullah > ; Ajit Khaparde > ; Alok Prasad ; > Burakov, Anatoly ; Andrew Rybchenko > ; Anoob Joseph ; > Richardson, Bruce ; Marohn, Byron > ; Chenbo Xia ; > Chengwen Feng ; Loftus, Ciara > ; Power, Ciara ; Dariusz > Sosnowski ; Hunt, David ; > Devendra Singh Rawat ; Carrillo, Erik G > ; Guoyang Zhou ; > Harman Kalra ; Van Haaren, Harry > ; Nagarahalli, Honnappa > ; Jakub Grajciar ; > Jerin Jacob ; Jeroen de Borst ; > Jian Wang ; Jiawen Wu > ; Jie Hai ; Wu, Jingjing > ; Joshua Washington ; > Joyce Kong ; Guo, Junfeng ; > Laatz, Kevin ; Konstantin Ananyev > ; Liang Ma ; > Long Li ; Maciej Czekaj ; > Matan Azrad ; Maxime Coquelin > ; Chautru, Nicolas > ; Ori Kam ; Pavan Nikhilesh > ; Mccarthy, Peter > ; Rahul Lakkireddy > ; Pattan, Reshma > ; Xu, Rosen ; Ruifeng > Wang ; Rushil Gupta ; > Gobriel, Sameh ; Sivaprasad Tummala > ; Somnath Kotur > ; Stephen Hemminger > ; Suanming Mou > ; Sunil Kumar Kori ; Sunil > Uttarwar ; Tetsuya Mukawa > ; Vamsi Attunuru ; > Viacheslav Ovsiienko ; Medvedkin, Vladimir > ; Xiaoyun Wang > ; Wang, Yipeng1 > ; Yisen Zhuang ; > Ziyang Xuan ; Tyler Retzlaff > > Subject: [PATCH v5 31/45] baseband/acc: use rte stdatomic API >=20 > Replace the use of gcc builtin __atomic_xxx intrinsics with corresponding > rte_atomic_xxx optional rte stdatomic API. >=20 > Signed-off-by: Tyler Retzlaff > Acked-by: Stephen Hemminger > --- > drivers/baseband/acc/rte_acc100_pmd.c | 36 +++++++++++++-------------- > drivers/baseband/acc/rte_vrb_pmd.c | 46 +++++++++++++++++++++++----- > ------- > 2 files changed, 48 insertions(+), 34 deletions(-) >=20 > diff --git a/drivers/baseband/acc/rte_acc100_pmd.c > b/drivers/baseband/acc/rte_acc100_pmd.c > index 4f666e5..ee50b9c 100644 > --- a/drivers/baseband/acc/rte_acc100_pmd.c > +++ b/drivers/baseband/acc/rte_acc100_pmd.c > @@ -3673,8 +3673,8 @@ >=20 > desc_idx =3D acc_desc_idx_tail(q, *dequeued_descs); > desc =3D q->ring_addr + desc_idx; > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3728,8 +3728,8 @@ > uint16_t current_dequeued_descs =3D 0, descs_in_tb; >=20 > desc =3D acc_desc_tail(q, *dequeued_descs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3742,8 +3742,8 @@ > /* Check if last CB in TB is ready to dequeue (and thus > * the whole TB) - checking sdone bit. If not return. > */ > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)last_desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)last_desc, > + rte_memory_order_relaxed); > if (!(atom_desc.rsp.val & ACC_SDONE)) > return -1; >=20 > @@ -3755,8 +3755,8 @@ >=20 > while (i < descs_in_tb) { > desc =3D acc_desc_tail(q, *dequeued_descs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); > rsp.val =3D atom_desc.rsp.val; > rte_bbdev_log_debug("Resp. desc %p: %x descs %d cbs > %d\n", > desc, rsp.val, descs_in_tb, desc- > >req.numCBs); @@ -3793,8 +3793,8 @@ > struct rte_bbdev_dec_op *op; >=20 > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3846,8 +3846,8 @@ > struct rte_bbdev_dec_op *op; >=20 > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3902,8 +3902,8 @@ > uint8_t cbs_in_tb =3D 1, cb_idx =3D 0; >=20 > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3919,8 +3919,8 @@ > /* Check if last CB in TB is ready to dequeue (and thus > * the whole TB) - checking sdone bit. If not return. > */ > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)last_desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)last_desc, > + rte_memory_order_relaxed); > if (!(atom_desc.rsp.val & ACC_SDONE)) > return -1; >=20 > @@ -3930,8 +3930,8 @@ > /* Read remaining CBs if exists */ > while (cb_idx < cbs_in_tb) { > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); > rsp.val =3D atom_desc.rsp.val; > rte_bbdev_log_debug("Resp. desc %p: %x r %d c %d\n", > desc, rsp.val, cb_idx, > cbs_in_tb); diff --git a/drivers/baseband/acc/rte_vrb_pmd.c > b/drivers/baseband/acc/rte_vrb_pmd.c > index 88b1104..f7c54be 100644 > --- a/drivers/baseband/acc/rte_vrb_pmd.c > +++ b/drivers/baseband/acc/rte_vrb_pmd.c > @@ -3119,7 +3119,8 @@ >=20 > desc_idx =3D acc_desc_idx_tail(q, *dequeued_descs); > desc =3D q->ring_addr + desc_idx; > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > if (*dequeued_ops + desc->req.numCBs > max_requested_ops) > return -1; > @@ -3157,7 +3158,8 @@ > struct rte_bbdev_enc_op *op; >=20 > desc =3D acc_desc_tail(q, *dequeued_descs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit. */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3192,7 +3194,8 @@ > uint16_t current_dequeued_descs =3D 0, descs_in_tb; >=20 > desc =3D acc_desc_tail(q, *dequeued_descs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > if (*dequeued_ops + 1 > max_requested_ops) > return -1; > @@ -3208,7 +3211,8 @@ > /* Check if last CB in TB is ready to dequeue (and thus > * the whole TB) - checking sdone bit. If not return. > */ > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)last_desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)last_desc, > + rte_memory_order_relaxed); > if (!(atom_desc.rsp.val & ACC_SDONE)) > return -1; >=20 > @@ -3220,7 +3224,8 @@ >=20 > while (i < descs_in_tb) { > desc =3D acc_desc_tail(q, *dequeued_descs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); > rsp.val =3D atom_desc.rsp.val; >=20 > vrb_update_dequeued_operation(desc, rsp, &op->status, > aq_dequeued, true, false); @@ -3246,7 +3251,8 @@ > struct rte_bbdev_dec_op *op; >=20 > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit. */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3290,7 +3296,8 @@ > struct rte_bbdev_dec_op *op; >=20 > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit. */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3346,7 +3353,8 @@ > uint32_t tb_crc_check =3D 0; >=20 > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit. */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -3362,7 +3370,8 @@ > /* Check if last CB in TB is ready to dequeue (and thus the whole TB) - > checking sdone bit. > * If not return. > */ > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)last_desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)last_desc, > + rte_memory_order_relaxed); > if (!(atom_desc.rsp.val & ACC_SDONE)) > return -1; >=20 > @@ -3372,7 +3381,8 @@ > /* Read remaining CBs if exists. */ > while (cb_idx < cbs_in_tb) { > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); > rsp.val =3D atom_desc.rsp.val; > rte_bbdev_log_debug("Resp. desc %p: %x %x %x", desc, > rsp.val, desc->rsp.add_info_0, > @@ -3790,7 +3800,8 @@ > struct rte_bbdev_fft_op *op; >=20 > desc =3D acc_desc_tail(q, dequeued_cbs); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -4116,7 +4127,8 @@ > uint8_t descs_in_op, i; >=20 > desc =3D acc_desc_tail(q, dequeued_ops); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); >=20 > /* Check fdone bit. */ > if (!(atom_desc.rsp.val & ACC_FDONE)) > @@ -4127,7 +4139,8 @@ > /* Get last CB. */ > last_desc =3D acc_desc_tail(q, dequeued_ops + descs_in_op - > 1); > /* Check if last op is ready to dequeue by checking fdone bit. > If not exit. */ > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t > *)last_desc, __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)last_desc, > + rte_memory_order_relaxed); > if (!(atom_desc.rsp.val & ACC_FDONE)) > return -1; > #ifdef RTE_LIBRTE_BBDEV_DEBUG > @@ -4137,8 +4150,8 @@ > for (i =3D 1; i < descs_in_op - 1; i++) { > last_desc =3D q->ring_addr + ((q->sw_ring_tail + > dequeued_ops + i) > & q->sw_ring_wrap_mask); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t > *)last_desc, > - __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit( > + (uint64_t __rte_atomic *)last_desc, > rte_memory_order_relaxed); > if (!(atom_desc.rsp.val & ACC_FDONE)) > return -1; > } > @@ -4154,7 +4167,8 @@ >=20 > for (i =3D 0; i < descs_in_op; i++) { > desc =3D q->ring_addr + ((q->sw_ring_tail + dequeued_ops + i) > & q->sw_ring_wrap_mask); > - atom_desc.atom_hdr =3D __atomic_load_n((uint64_t *)desc, > __ATOMIC_RELAXED); > + atom_desc.atom_hdr =3D rte_atomic_load_explicit((uint64_t > __rte_atomic *)desc, > + rte_memory_order_relaxed); > rsp.val =3D atom_desc.rsp.val; >=20 > vrb_update_dequeued_operation(desc, rsp, &op->status, > aq_dequeued, true, false); > -- > 1.8.3.1