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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR11MB4451.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 02c79e4b-e523-49e3-4748-08da3d1b60ec X-MS-Exchange-CrossTenant-originalarrivaltime: 24 May 2022 00:21:42.5230 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: H/yvaT2UkBy3YXkVrO2obl5jSfb31AwyjX4wf6g/W9Wlg0TYWZAmwklZw9et6VsLZ+oG5H/gX0ghaIdIRS0uTTjXaWDV1HnHucY9Ti44KDQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR11MB3108 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Thanks Hernan > -----Original Message----- > From: Vargas, Hernan > Sent: Thursday, May 19, 2022 8:06 PM > To: dev@dpdk.org; gakhil@marvell.com; trix@redhat.com > Cc: Chautru, Nicolas ; Zhang, Qi Z > ; Vargas, Hernan > Subject: [PATCH v2 5/5] baseband/fpga_5gnr_fec: remove filler from HARQ >=20 > From: Hernan >=20 > Removed filler bits from HARQ calculation on the N3000 FPGA since these a= re > already taken out by the deratematching step. > The change is only an optimization with no functional impact, no change > required on stable branches. >=20 > Signed-off-by: Hernan Reviewed-by: Nicolas Chautru > --- > drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > index d678695a3c..82ae6ba678 100644 > --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > @@ -1844,7 +1844,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue > *q, struct rte_bbdev_dec_op *op, > else > l =3D k0 + e + dec->n_filler; > harq_out_length =3D RTE_MIN(RTE_MAX(harq_in_length, l), > - dec->n_cb - dec->n_filler); > + dec->n_cb); > dec->harq_combined_output.length =3D harq_out_length; > } >=20 > -- > 2.25.1