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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB2901.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dc62b299-576b-4577-d441-08d828b135dd X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jul 2020 11:21:24.8539 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DWEIPkeCsugqbwFATPjyVgCYqD5H5vb4/S4RC5uKCXivPYdETAT09NJO/PCbMZwQGH761uvozwdCcgV/KeJo2Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2808 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" -----Original Message----- From: Zhang, Tianfei =20 Sent: Wednesday, July 15, 2020 5:35 AM To: dev@dpdk.org; Xu, Rosen Cc: Zhang, Tianfei ; stable@dpdk.org Subject: [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial From: Tianfei Zhang Add fecmode setting on NIOS SPI primary initialization. this SPI is shared by NIOS core inside FPGA, NIOS will use this SPI primary= to do some one-time initialization after power up, and then release the co= ntrol to DPDK. Fix the timeout initialization for polling the NIOS_INIT_DONE. Fixes: bc44402f ("raw/ifpga/base: configure FEC mode") Cc: stable@dpdk.org Signed-off-by: Tianfei Zhang --- v3: resend the patch with threaded option for git send-email v2: fix coding style issue --- drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++------- drive= rs/raw/ifpga/base/opae_spi.h | 1 + 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/if= pga_fme.c index c31a94cf8..9057087b5 100644 --- a/drivers/raw/ifpga/base/ifpga_fme.c +++ b/drivers/raw/ifpga/base/ifpga_fme.c @@ -979,28 +979,32 @@ struct ifpga_feature_ops fme_spi_master_ops =3D { st= atic int nios_spi_wait_init_done(struct altera_spi_device *dev) { u32 val =3D 0; - unsigned long timeout =3D msecs_to_timer_cycles(10000); + unsigned long timeout =3D rte_get_timer_cycles() + + msecs_to_timer_cycles(10000); unsigned long ticks; int major_version; + int fecmode =3D FEC_MODE_NO; =20 if (spi_reg_read(dev, NIOS_VERSION, &val)) return -EIO; =20 - major_version =3D (val >> NIOS_VERSION_MAJOR_SHIFT) & - NIOS_VERSION_MAJOR; - dev_debug(dev, "A10 NIOS FW version %d\n", major_version); + major_version =3D + (val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT; + dev_info(dev, "A10 NIOS FW version %d\n", major_version); =20 if (major_version >=3D 3) { /* read NIOS_INIT to check if PKVL INIT done or not */ if (spi_reg_read(dev, NIOS_INIT, &val)) return -EIO; =20 + dev_debug(dev, "read NIOS_INIT: 0x%x\n", val); + /* check if PKVLs are initialized already */ if (val & NIOS_INIT_DONE || val & NIOS_INIT_START) goto nios_init_done; =20 /* start to config the default FEC mode */ - val =3D NIOS_INIT_START; + val =3D fecmode | NIOS_INIT_START; =20 if (spi_reg_write(dev, NIOS_INIT, val)) return -EIO; @@ -1010,14 +1014,23 @@ static int nios_spi_wait_init_done(struct altera_sp= i_device *dev) do { if (spi_reg_read(dev, NIOS_INIT, &val)) return -EIO; - if (val) + if (val & NIOS_INIT_DONE) break; =20 ticks =3D rte_get_timer_cycles(); if (time_after(ticks, timeout)) return -ETIMEDOUT; msleep(100); - } while (!val); + } while (1); + + /* get the fecmode */ + if (spi_reg_read(dev, NIOS_INIT, &val)) + return -EIO; + dev_debug(dev, "read NIOS_INIT: 0x%x\n", val); + fecmode =3D (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT; + dev_info(dev, "fecmode: 0x%x, %s\n", fecmode, + (fecmode =3D=3D FEC_MODE_KR) ? "kr" : + ((fecmode =3D=3D FEC_MODE_RS) ? "rs" : "no")); =20 return 0; } diff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opa= e_spi.h index d20a4c3ed..73a227673 100644 --- a/drivers/raw/ifpga/base/opae_spi.h +++ b/drivers/raw/ifpga/base/opae_spi.h @@ -153,6 +153,7 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg= , u32 *val); =20 #define NIOS_INIT 0x1000 #define REQ_FEC_MODE GENMASK(23, 8) +#define REQ_FEC_MODE_SHIFT 8 #define FEC_MODE_NO 0x0 #define FEC_MODE_KR 0x5555 #define FEC_MODE_RS 0xaaaa -- 2.17.1 Acked-by: Rosen Xu