* Re: [dpdk-dev] [PATCH v2] net/ixgbe: fix flow ctrl mode setting
@ 2020-01-28 8:57 Konieczny, TomaszX
0 siblings, 0 replies; 3+ messages in thread
From: Konieczny, TomaszX @ 2020-01-28 8:57 UTC (permalink / raw)
To: dev
Patch fixes reported issue.
Tested-by: Tomasz Konieczny <tomaszx.konieczny@intel.com>
Regards
Tomasz Konieczny
---------------------------------------------------------------------
Intel Corporation (UK) Ltd.
Co. Reg. #1134945
Pipers Way, Swindon SN3 1RJ
>Date: Thu, 19 Dec 2019 10:17:58 +0000
>From: Guinan Sun <guinanx.sun@intel.com>
>To: dev@dpdk.org
>Cc: Wenzhuo Lu <wenzhuo.lu@intel.com>, Qiming Yang
> <qiming.yang@intel.com>, Qi Zhang <qi.z.zhang@intel.com>, Guinan Sun
> <guinanx.sun@intel.com>, stable@dpdk.org
>Subject: [dpdk-dev] [PATCH v2] net/ixgbe: fix flow ctrl mode setting
>Message-ID: <20191219101758.24608-1-guinanx.sun@intel.com>
>
>When the port starts, the hw register is reset first,
>and then the required parameters are set again.
>If the parameters to be used are not set after resetting the register,
>a read register error will occur. This patch is used to fix the problem.
>
>Fixes: af75078fece3 ("first public release")
>Cc: stable@dpdk.org
>
>Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
>---
>v2: changes
>* Modify the initial value of requested_mode and current_mode
>---
> drivers/net/ixgbe/ixgbe_ethdev.c | 24 ++++++++++++++++++++++--
> drivers/net/ixgbe/ixgbe_ethdev.h | 1 +
> 2 files changed, 23 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
>index 2c6fd0f13..573117e3a 100644
>--- a/drivers/net/ixgbe/ixgbe_ethdev.c
>+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
>@@ -1170,8 +1170,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void
>*init_params __rte_unused)
> memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
> ixgbe_dcb_init(hw, dcb_config);
> /* Get Hardware Flow Control setting */
>- hw->fc.requested_mode = ixgbe_fc_full;
>- hw->fc.current_mode = ixgbe_fc_full;
>+ hw->fc.requested_mode = ixgbe_fc_none;
>+ hw->fc.current_mode = ixgbe_fc_none;
> hw->fc.pause_time = IXGBE_FC_PAUSE;
> for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
> hw->fc.low_water[i] = IXGBE_FC_LO;
>@@ -2539,6 +2539,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
> {
> struct ixgbe_hw *hw =
> IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
>+ struct ixgbe_adapter *adapter = dev->data->dev_private;
> struct ixgbe_vf_info *vfinfo =
> *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
> struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
>@@ -2555,6 +2556,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
> IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
> struct ixgbe_macsec_setting *macsec_setting =
> IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data-
>>dev_private);
>+ uint32_t mflcn;
>
> PMD_INIT_FUNC_TRACE();
>
>@@ -2665,6 +2667,20 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
> }
>
> ixgbe_restore_statistics_mapping(dev);
>+ err = ixgbe_fc_enable(hw);
>+ if ((err == IXGBE_SUCCESS) || (err ==
>IXGBE_ERR_FC_NOT_NEGOTIATED)) {
>+
>+ mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
>+
>+ /* set or clear MFLCN.PMCF bit depending on configuration */
>+ if (adapter->mac_ctrl_frame_fwd != 0)
>+ mflcn |= IXGBE_MFLCN_PMCF;
>+ else
>+ mflcn &= ~IXGBE_MFLCN_PMCF;
>+
>+ IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
>+ IXGBE_WRITE_FLUSH(hw);
>+ }
>
> err = ixgbe_dev_rxtx_start(dev);
> if (err < 0) {
>@@ -2893,6 +2909,8 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
>
> adapter->rss_reta_updated = 0;
>
>+ adapter->mac_ctrl_frame_fwd = 0;
>+
> hw->adapter_stopped = true;
> }
>
>@@ -4646,6 +4664,7 @@ static int
> ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
> {
> struct ixgbe_hw *hw;
>+ struct ixgbe_adapter *adapter = dev->data->dev_private;
> int err;
> uint32_t rx_buf_size;
> uint32_t max_high_water;
>@@ -4682,6 +4701,7 @@ ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct
>rte_eth_fc_conf *fc_conf)
> hw->fc.low_water[0] = fc_conf->low_water;
> hw->fc.send_xon = fc_conf->send_xon;
> hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
>+ adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
>
> err = ixgbe_fc_enable(hw);
>
>diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h
>index 76a1b9d18..5af584f9e 100644
>--- a/drivers/net/ixgbe/ixgbe_ethdev.h
>+++ b/drivers/net/ixgbe/ixgbe_ethdev.h
>@@ -510,6 +510,7 @@ struct ixgbe_adapter {
> * mailbox status) link status.
> */
> uint8_t pflink_fullchk;
>+ uint8_t mac_ctrl_frame_fwd;
> };
>
> struct ixgbe_vf_representor {
>--
>2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread* [dpdk-dev] [PATCH] net/ixgbe: fix flow ctrl mode setting
@ 2019-12-19 4:43 Sun GuinanX
2019-12-19 10:17 ` [dpdk-dev] [PATCH v2] " Guinan Sun
0 siblings, 1 reply; 3+ messages in thread
From: Sun GuinanX @ 2019-12-19 4:43 UTC (permalink / raw)
To: dev; +Cc: Wenzhuo Lu, Qiming Yang, Qi Zhang, Sun GuinanX, stable
When the port starts, the hw register is reset first,
and then the required parameters are set again.
If the parameters to be used are not set after resetting the register,
a read register error will occur. This patch is used to fix the problem.
Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org
Signed-off-by: Sun GuinanX <guinanx.sun@intel.com>
---
drivers/net/ixgbe/ixgbe_ethdev.c | 20 ++++++++++++++++++++
drivers/net/ixgbe/ixgbe_ethdev.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 2c6fd0f13..e602df02b 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -2539,6 +2539,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
{
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct ixgbe_adapter *adapter = dev->data->dev_private;
struct ixgbe_vf_info *vfinfo =
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
@@ -2555,6 +2556,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
struct ixgbe_macsec_setting *macsec_setting =
IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
+ uint32_t mflcn;
PMD_INIT_FUNC_TRACE();
@@ -2665,6 +2667,20 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
}
ixgbe_restore_statistics_mapping(dev);
+ err = ixgbe_fc_enable(hw);
+ if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
+
+ mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
+
+ /* set or clear MFLCN.PMCF bit depending on configuration */
+ if (adapter->mac_ctrl_frame_fwd != 0)
+ mflcn |= IXGBE_MFLCN_PMCF;
+ else
+ mflcn &= ~IXGBE_MFLCN_PMCF;
+
+ IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
+ IXGBE_WRITE_FLUSH(hw);
+ }
err = ixgbe_dev_rxtx_start(dev);
if (err < 0) {
@@ -2893,6 +2909,8 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
adapter->rss_reta_updated = 0;
+ adapter->mac_ctrl_frame_fwd = 0;
+
hw->adapter_stopped = true;
}
@@ -4646,6 +4664,7 @@ static int
ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
{
struct ixgbe_hw *hw;
+ struct ixgbe_adapter *adapter = dev->data->dev_private;
int err;
uint32_t rx_buf_size;
uint32_t max_high_water;
@@ -4682,6 +4701,7 @@ ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
hw->fc.low_water[0] = fc_conf->low_water;
hw->fc.send_xon = fc_conf->send_xon;
hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
+ adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
err = ixgbe_fc_enable(hw);
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h
index 76a1b9d18..5af584f9e 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.h
+++ b/drivers/net/ixgbe/ixgbe_ethdev.h
@@ -510,6 +510,7 @@ struct ixgbe_adapter {
* mailbox status) link status.
*/
uint8_t pflink_fullchk;
+ uint8_t mac_ctrl_frame_fwd;
};
struct ixgbe_vf_representor {
--
2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread* [dpdk-dev] [PATCH v2] net/ixgbe: fix flow ctrl mode setting
2019-12-19 4:43 [dpdk-dev] [PATCH] " Sun GuinanX
@ 2019-12-19 10:17 ` Guinan Sun
2020-02-01 13:12 ` Ye Xiaolong
0 siblings, 1 reply; 3+ messages in thread
From: Guinan Sun @ 2019-12-19 10:17 UTC (permalink / raw)
To: dev; +Cc: Wenzhuo Lu, Qiming Yang, Qi Zhang, Guinan Sun, stable
When the port starts, the hw register is reset first,
and then the required parameters are set again.
If the parameters to be used are not set after resetting the register,
a read register error will occur. This patch is used to fix the problem.
Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
---
v2: changes
* Modify the initial value of requested_mode and current_mode
---
drivers/net/ixgbe/ixgbe_ethdev.c | 24 ++++++++++++++++++++++--
drivers/net/ixgbe/ixgbe_ethdev.h | 1 +
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index 2c6fd0f13..573117e3a 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -1170,8 +1170,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
ixgbe_dcb_init(hw, dcb_config);
/* Get Hardware Flow Control setting */
- hw->fc.requested_mode = ixgbe_fc_full;
- hw->fc.current_mode = ixgbe_fc_full;
+ hw->fc.requested_mode = ixgbe_fc_none;
+ hw->fc.current_mode = ixgbe_fc_none;
hw->fc.pause_time = IXGBE_FC_PAUSE;
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
hw->fc.low_water[i] = IXGBE_FC_LO;
@@ -2539,6 +2539,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
{
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct ixgbe_adapter *adapter = dev->data->dev_private;
struct ixgbe_vf_info *vfinfo =
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
@@ -2555,6 +2556,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
struct ixgbe_macsec_setting *macsec_setting =
IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
+ uint32_t mflcn;
PMD_INIT_FUNC_TRACE();
@@ -2665,6 +2667,20 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
}
ixgbe_restore_statistics_mapping(dev);
+ err = ixgbe_fc_enable(hw);
+ if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
+
+ mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
+
+ /* set or clear MFLCN.PMCF bit depending on configuration */
+ if (adapter->mac_ctrl_frame_fwd != 0)
+ mflcn |= IXGBE_MFLCN_PMCF;
+ else
+ mflcn &= ~IXGBE_MFLCN_PMCF;
+
+ IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
+ IXGBE_WRITE_FLUSH(hw);
+ }
err = ixgbe_dev_rxtx_start(dev);
if (err < 0) {
@@ -2893,6 +2909,8 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
adapter->rss_reta_updated = 0;
+ adapter->mac_ctrl_frame_fwd = 0;
+
hw->adapter_stopped = true;
}
@@ -4646,6 +4664,7 @@ static int
ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
{
struct ixgbe_hw *hw;
+ struct ixgbe_adapter *adapter = dev->data->dev_private;
int err;
uint32_t rx_buf_size;
uint32_t max_high_water;
@@ -4682,6 +4701,7 @@ ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
hw->fc.low_water[0] = fc_conf->low_water;
hw->fc.send_xon = fc_conf->send_xon;
hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
+ adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
err = ixgbe_fc_enable(hw);
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h
index 76a1b9d18..5af584f9e 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.h
+++ b/drivers/net/ixgbe/ixgbe_ethdev.h
@@ -510,6 +510,7 @@ struct ixgbe_adapter {
* mailbox status) link status.
*/
uint8_t pflink_fullchk;
+ uint8_t mac_ctrl_frame_fwd;
};
struct ixgbe_vf_representor {
--
2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [dpdk-dev] [PATCH v2] net/ixgbe: fix flow ctrl mode setting
2019-12-19 10:17 ` [dpdk-dev] [PATCH v2] " Guinan Sun
@ 2020-02-01 13:12 ` Ye Xiaolong
0 siblings, 0 replies; 3+ messages in thread
From: Ye Xiaolong @ 2020-02-01 13:12 UTC (permalink / raw)
To: Guinan Sun; +Cc: dev, Wenzhuo Lu, Qiming Yang, Qi Zhang, stable
Hi, Guinan
On 12/19, Guinan Sun wrote:
>When the port starts, the hw register is reset first,
>and then the required parameters are set again.
>If the parameters to be used are not set after resetting the register,
>a read register error will occur. This patch is used to fix the problem.
>
>Fixes: af75078fece3 ("first public release")
>Cc: stable@dpdk.org
>
>Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
>---
>v2: changes
>* Modify the initial value of requested_mode and current_mode
>---
> drivers/net/ixgbe/ixgbe_ethdev.c | 24 ++++++++++++++++++++++--
> drivers/net/ixgbe/ixgbe_ethdev.h | 1 +
> 2 files changed, 23 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
>index 2c6fd0f13..573117e3a 100644
>--- a/drivers/net/ixgbe/ixgbe_ethdev.c
>+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
>@@ -1170,8 +1170,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
> memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
> ixgbe_dcb_init(hw, dcb_config);
> /* Get Hardware Flow Control setting */
>- hw->fc.requested_mode = ixgbe_fc_full;
>- hw->fc.current_mode = ixgbe_fc_full;
>+ hw->fc.requested_mode = ixgbe_fc_none;
>+ hw->fc.current_mode = ixgbe_fc_none;
> hw->fc.pause_time = IXGBE_FC_PAUSE;
> for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
> hw->fc.low_water[i] = IXGBE_FC_LO;
>@@ -2539,6 +2539,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
> {
> struct ixgbe_hw *hw =
> IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
>+ struct ixgbe_adapter *adapter = dev->data->dev_private;
> struct ixgbe_vf_info *vfinfo =
> *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
> struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
>@@ -2555,6 +2556,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
> IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
> struct ixgbe_macsec_setting *macsec_setting =
> IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
>+ uint32_t mflcn;
>
> PMD_INIT_FUNC_TRACE();
>
>@@ -2665,6 +2667,20 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
> }
>
> ixgbe_restore_statistics_mapping(dev);
>+ err = ixgbe_fc_enable(hw);
>+ if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
>+
>+ mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
>+
>+ /* set or clear MFLCN.PMCF bit depending on configuration */
>+ if (adapter->mac_ctrl_frame_fwd != 0)
>+ mflcn |= IXGBE_MFLCN_PMCF;
>+ else
>+ mflcn &= ~IXGBE_MFLCN_PMCF;
>+
>+ IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
>+ IXGBE_WRITE_FLUSH(hw);
>+ }
It'd be better to wrap above lines of code into a function to avoid duplication.
Thanks,
Xiaolong
>
> err = ixgbe_dev_rxtx_start(dev);
> if (err < 0) {
>@@ -2893,6 +2909,8 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
>
> adapter->rss_reta_updated = 0;
>
>+ adapter->mac_ctrl_frame_fwd = 0;
>+
> hw->adapter_stopped = true;
> }
>
>@@ -4646,6 +4664,7 @@ static int
> ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
> {
> struct ixgbe_hw *hw;
>+ struct ixgbe_adapter *adapter = dev->data->dev_private;
> int err;
> uint32_t rx_buf_size;
> uint32_t max_high_water;
>@@ -4682,6 +4701,7 @@ ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
> hw->fc.low_water[0] = fc_conf->low_water;
> hw->fc.send_xon = fc_conf->send_xon;
> hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
>+ adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
>
> err = ixgbe_fc_enable(hw);
>
>diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h
>index 76a1b9d18..5af584f9e 100644
>--- a/drivers/net/ixgbe/ixgbe_ethdev.h
>+++ b/drivers/net/ixgbe/ixgbe_ethdev.h
>@@ -510,6 +510,7 @@ struct ixgbe_adapter {
> * mailbox status) link status.
> */
> uint8_t pflink_fullchk;
>+ uint8_t mac_ctrl_frame_fwd;
> };
>
> struct ixgbe_vf_representor {
>--
>2.17.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-02-01 13:13 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2020-01-28 8:57 [dpdk-dev] [PATCH v2] net/ixgbe: fix flow ctrl mode setting Konieczny, TomaszX
-- strict thread matches above, loose matches on Subject: below --
2019-12-19 4:43 [dpdk-dev] [PATCH] " Sun GuinanX
2019-12-19 10:17 ` [dpdk-dev] [PATCH v2] " Guinan Sun
2020-02-01 13:12 ` Ye Xiaolong
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