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Mon, 14 Sep 2020 15:10:16 +0000 Received: from BYAPR11MB3143.namprd11.prod.outlook.com ([fe80::25c7:1828:b871:bb8]) by BYAPR11MB3143.namprd11.prod.outlook.com ([fe80::25c7:1828:b871:bb8%6]) with mapi id 15.20.3370.019; Mon, 14 Sep 2020 15:10:16 +0000 From: "Van Haaren, Harry" To: Pavan Nikhilesh Bhagavatula , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant Thread-Index: AQHWiBx431Rywk96Y0Wlfep4uWMH0KlnA88AgADEyVCAAC20AIAAQsBA Date: Mon, 14 Sep 2020 15:10:16 +0000 Message-ID: References: <20200911091919.62167-1-harry.van.haaren@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [87.198.126.230] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ff20109d-28b7-4e4a-b94f-08d858c04967 x-ms-traffictypediagnostic: BY5PR11MB3864: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1148; 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x-ms-exchange-antispam-messagedata: MQLEZ2AwA1U7hcOdakzBjK/f8ldljZGwXGwewjAKVXc/AqQnpH565ZHzlS4S/cH7h7eIwe7KTSAvnTxldxoN0JEPUoctVSEB6CDIqCl+ugK1iM1KKfu+2lfOuihG2WRCaawBQ9bijbX2fN5r38R5fGf5adJVsPrD6+V31aemtigKc1J6ZDVEhEMe/AbEtnj332dEXqT4Oj07qROyq3YrdSEnkTogSNMAnSb9G5bFzoK2xk4fUC2QR0P08JGqwVczK0tf+B7avBdB0O9d6RXKelfmYS9b+qmiQ+fGy5hwiKxH0G7VcDq/e69TaHHDu8CGYdSE/CPpde9ROqFal8qyA+JCHqo4niDp5CVwjpOV9jQVEGEOSG5w5QAeKQ82ZZgeoviDeAb3Vc92Ul82JzMw6jG/vVDBtMF2RGKnlLZhPbfTr8DLkJZWss4qmcqgb9u6q+OCOuE9XqyTQqtNoMbBJLupB5QTX4jcktLyKoiug1hoTg5u4aXzTs7CeBheZxVLVsEKoJy8S02UXjtrFH2ObTxcVHvf5vJXRsqglx3nEoh8KppPg8Ixl51q99WolCkEcg+hPF1Se4gnfG4EREms+Ic9d2FvCW00L2QWoGb2wu46V34XG8Yb8p4g0ruH/kArrngXRUTaRTqILmcpQmaRAA== x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3143.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ff20109d-28b7-4e4a-b94f-08d858c04967 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Sep 2020 15:10:16.0395 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AlIyXnccvFS1TDyobdtvgbGWysZnNSA+tiYXoApmohA5epflThJzgFqJhC6Xqv0RRNgmoEvfJNr7tkX3okWFxCbnJHF5p27ERHUfI7yb6Ig= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB3864 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Pavan Nikhilesh Bhagavatula > Sent: Monday, September 14, 2020 11:39 AM > To: Van Haaren, Harry ; dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant >=20 > >> >This commit adds a new rte_prefetch0_write() variant, suggests to > >the > >> >compiler to use a prefetch instruction with intention to write. As a > >> >compiler builtin, the compiler can choose based on compilation > >target > >> >what the best implementation for this instruction is. > >> > >> Why not have the other variants too i.e. l2/l3/temporal store > >prefetches too? > > > >Hi Pavan, > > > Hi Harry, > (LTNS) >=20 > >Are there architectures that actually implement those? Usually for a WB > >mem store to complete, > >the data must be present in L1 cache (on x86 at least), and that's what > >the patch below with write0 achieves. >=20 > ARM64 does supports all modes of store prefetch > " > is one of: > PLD Prefetch for load, encoded in the "Rt<4:3>" field as 0b00. > PLI Preload instructions, encoded in the "Rt<4:3>" field as 0b01. > PST Prefetch for store, encoded in the "Rt<4:3>" field as 0b10. > is one of: > L1 Level 1 cache, encoded in the "Rt<2:1>" field as 0b00. > L2 Level 2 cache, encoded in the "Rt<2:1>" field as 0b01. > L3 Level 3 cache, encoded in the "Rt<2:1>" field as 0b10. > is one of: > KEEP Retained or temporal prefetch, allocated in the cache normally. Enco= ded in > the "Rt<0>" > field as 0. > STRM Streaming or non-temporal prefetch, for data that is used only once.= Encoded > in the > "Rt<0>" field as 1. > For more information on these prefetch > " >=20 > > > >I'm against adding all the variants "just in case", it leads to API bloa= t, > >and increases > >cognitive load on the programmer. My expectation is that in 99% of > >usage the prefetch > >write instruction should target L1. > > >=20 > There is a use case when cache mode is write through and application is > pipelining work across cores sharing same L2 cluster. OK - v2 sent: http://patches.dpdk.org/patch/77632/ APIs matching the existing prefetch APIs: rte_prefetch0_write() L1 and all below rte_prefetch1_write() L2 and all below rte_prefetch2_write() L3 Cheers, -Harry