Re: [dpdk-dev] [PATCH v3] eal/cpuflags: add x86 based cpu flags

["Van Haaren, Harry" <harry.van.haaren@intel.com>]

> -----Original Message-----
> From: Laatz, Kevin <kevin.laatz@intel.com>
> Sent: Monday, March 30, 2020 1:15 PM
> To: dev@dpdk.org
> Cc: Richardson, Bruce <bruce.richardson@intel.com>; Van Haaren, Harry
> <harry.van.haaren@intel.com>; thomas@monjalon.net; Kinsella, Ray
> <ray.kinsella@intel.com>; nhorman@tuxdriver.com;
> david.marchand@redhat.com; Laatz, Kevin <kevin.laatz@intel.com>
> Subject: [PATCH v3] eal/cpuflags: add x86 based cpu flags
> 
> This patch adds CPU flags which will enable the detection of ISA
> features available on more recent x86 based CPUs.
> 
> The CPUID leaf information can be found in Section 1.7 of this
> document:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> instruction-set-extensions-programming-reference.pdf

Section numbering has been updated, and there doesn't seem to be a stable
link to a specific version of the doc, recommend to refer to table name instead?
Table 1-2. "Information Returned by CPUID Instruction"


> The following CPU flags are added in this patch:
>     - AVX-512 doubleword and quadword instructions.
>     - AVX-512 integer fused multiply-add instructions.
>     - AVX-512 conflict detection instructions.
>     - AVX-512 byte and word instructions.
>     - AVX-512 vector length instructions.
>     - AVX-512 vector bit manipulation instructions.
>     - AVX-512 vector bit manipulation 2 instructions.
>     - Galois field new instructions.
>     - Vector AES instructions.
>     - Vector carry-less multiply instructions.
>     - AVX-512 vector neural network instructions.
>     - AVX-512 for bit algorithm instructions.
>     - AVX-512 vector popcount instructions.
>     - Cache line demote instructions.
>     - Direct store instructions.
>     - Direct store 64B instructions.
>     - AVX-512 two register intersection instructions.
> 
> Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>

Required a git am --3way due to some file movements in master, but applied
cleanly on auto-merge.

Add a VNNI documentation line wrap on new line:
RTE_CPU_FLAG_AVX512VNNI,
/**< AVX512 Vector ...  */

With the above changes/updates;
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>