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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 815c145f-9566-432a-91e9-08d7e1ee18bf X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Apr 2020 10:08:22.8789 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fDjY6r0CqujfxJ7L0qxT7zpxMtQO5HAd65AI4YLp/cxQY7eWrQrpfcK5YHM9rAAyDDbWKZc3Lq3DdQP4PUYk5yk+C4lvCOAkNnHfe3tQ6SM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2629 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3] eal/cpuflags: add x86 based cpu flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Laatz, Kevin > Sent: Monday, March 30, 2020 1:15 PM > To: dev@dpdk.org > Cc: Richardson, Bruce ; Van Haaren, Harry > ; thomas@monjalon.net; Kinsella, Ray > ; nhorman@tuxdriver.com; > david.marchand@redhat.com; Laatz, Kevin > Subject: [PATCH v3] eal/cpuflags: add x86 based cpu flags >=20 > This patch adds CPU flags which will enable the detection of ISA > features available on more recent x86 based CPUs. >=20 > The CPUID leaf information can be found in Section 1.7 of this > document: > https://software.intel.com/sites/default/files/managed/c5/15/architecture= - > instruction-set-extensions-programming-reference.pdf Section numbering has been updated, and there doesn't seem to be a stable link to a specific version of the doc, recommend to refer to table name ins= tead? Table 1-2. "Information Returned by CPUID Instruction" > The following CPU flags are added in this patch: > - AVX-512 doubleword and quadword instructions. > - AVX-512 integer fused multiply-add instructions. > - AVX-512 conflict detection instructions. > - AVX-512 byte and word instructions. > - AVX-512 vector length instructions. > - AVX-512 vector bit manipulation instructions. > - AVX-512 vector bit manipulation 2 instructions. > - Galois field new instructions. > - Vector AES instructions. > - Vector carry-less multiply instructions. > - AVX-512 vector neural network instructions. > - AVX-512 for bit algorithm instructions. > - AVX-512 vector popcount instructions. > - Cache line demote instructions. > - Direct store instructions. > - Direct store 64B instructions. > - AVX-512 two register intersection instructions. >=20 > Signed-off-by: Kevin Laatz Required a git am --3way due to some file movements in master, but applied cleanly on auto-merge. Add a VNNI documentation line wrap on new line: RTE_CPU_FLAG_AVX512VNNI, /**< AVX512 Vector ... */ With the above changes/updates; Acked-by: Harry van Haaren