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Fri, 3 Apr 2020 11:58:34 +0000 Received: from BYAPR11MB3143.namprd11.prod.outlook.com ([fe80::5917:9757:49b0:3c49]) by BYAPR11MB3143.namprd11.prod.outlook.com ([fe80::5917:9757:49b0:3c49%5]) with mapi id 15.20.2878.014; Fri, 3 Apr 2020 11:58:34 +0000 From: "Van Haaren, Harry" To: Phil Yang , "thomas@monjalon.net" , "Ananyev, Konstantin" , "stephen@networkplumber.org" , "maxime.coquelin@redhat.com" , "dev@dpdk.org" CC: "david.marchand@redhat.com" , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , "Honnappa.Nagarahalli@arm.com" , "gavin.hu@arm.com" , "ruifeng.wang@arm.com" , "joyce.kong@arm.com" , "nd@arm.com" Thread-Topic: [PATCH v3 12/12] service: relax barriers with C11 atomic operations Thread-Index: AQHV+/omNUSP5Ua9ZE6XZhRVe3IM2qhnXyCw Date: Fri, 3 Apr 2020 11:58:34 +0000 Message-ID: References: <1583999071-22872-1-git-send-email-phil.yang@arm.com> <1584407863-774-1-git-send-email-phil.yang@arm.com> <1584407863-774-13-git-send-email-phil.yang@arm.com> In-Reply-To: <1584407863-774-13-git-send-email-phil.yang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=harry.van.haaren@intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 92fd9c49-eba9-43b9-f5ea-08d7d7c6564c X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Apr 2020 11:58:34.5726 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NshoHU9Isondbgq6eFU/ekj8Soph5bsq5zM3++6NZC3AGWMiYpyQOUoWzXW/Zv+H1Riv1ZJLxfu91aSPGiZOUq4Wff2gFMiTcT8MWjL0CPU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB3541 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 12/12] service: relax barriers with C11 atomic operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > From: Phil Yang > Sent: Tuesday, March 17, 2020 1:18 AM > To: thomas@monjalon.net; Van Haaren, Harry ; > Ananyev, Konstantin ; > stephen@networkplumber.org; maxime.coquelin@redhat.com; dev@dpdk.org > Cc: david.marchand@redhat.com; jerinj@marvell.com; hemant.agrawal@nxp.com= ; > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; ruifeng.wang@arm.com; > joyce.kong@arm.com; nd@arm.com > Subject: [PATCH v3 12/12] service: relax barriers with C11 atomic operati= ons >=20 > To guarantee the inter-threads visibility of the shareable domain, it > uses a lot of rte_smp_r/wmb in the service library. This patch relaxed > these barriers for service by using c11 atomic one-way barrier operations= . >=20 > Signed-off-by: Phil Yang > Reviewed-by: Ruifeng Wang > Reviewed-by: Gavin Hu > --- > lib/librte_eal/common/rte_service.c | 45 ++++++++++++++++++++-----------= ----- > - > 1 file changed, 25 insertions(+), 20 deletions(-) >=20 > diff --git a/lib/librte_eal/common/rte_service.c > b/lib/librte_eal/common/rte_service.c > index c033224..d31663e 100644 > --- a/lib/librte_eal/common/rte_service.c > +++ b/lib/librte_eal/common/rte_service.c > @@ -179,9 +179,11 @@ rte_service_set_stats_enable(uint32_t id, int32_t > enabled) > SERVICE_VALID_GET_OR_ERR_RET(id, s, 0); >=20 > if (enabled) > - s->internal_flags |=3D SERVICE_F_STATS_ENABLED; > + __atomic_or_fetch(&s->internal_flags, SERVICE_F_STATS_ENABLED, > + __ATOMIC_RELEASE); > else > - s->internal_flags &=3D ~(SERVICE_F_STATS_ENABLED); > + __atomic_and_fetch(&s->internal_flags, > + ~(SERVICE_F_STATS_ENABLED), __ATOMIC_RELEASE); Not sure why these have to become stores with RELEASE memory ordering? (More occurances of same Q below, just answer here?) > return 0; > } > @@ -193,9 +195,11 @@ rte_service_set_runstate_mapped_check(uint32_t id, > int32_t enabled) > SERVICE_VALID_GET_OR_ERR_RET(id, s, 0); >=20 > if (enabled) > - s->internal_flags |=3D SERVICE_F_START_CHECK; > + __atomic_or_fetch(&s->internal_flags, SERVICE_F_START_CHECK, > + __ATOMIC_RELEASE); > else > - s->internal_flags &=3D ~(SERVICE_F_START_CHECK); > + __atomic_and_fetch(&s->internal_flags, ~(SERVICE_F_START_CHECK), > + __ATOMIC_RELEASE); Same as above, why do these require RELEASE? Remainder of patch below seems to make sense - there's a wmb() involved hen= ce RELEASE m/o. > return 0; > } > @@ -264,8 +268,8 @@ rte_service_component_register(const struct > rte_service_spec *spec, > s->spec =3D *spec; > s->internal_flags |=3D SERVICE_F_REGISTERED | SERVICE_F_START_CHECK; >=20 > - rte_smp_wmb(); > - rte_service_count++; > + /* make sure the counter update after the state change. */ > + __atomic_add_fetch(&rte_service_count, 1, __ATOMIC_RELEASE); This makes sense to me - the RELEASE ensures that previous stores to the s->internal_flags are visible to other cores before rte_service_count increments atomically. > if (id_ptr) > *id_ptr =3D free_slot; > @@ -281,9 +285,10 @@ rte_service_component_unregister(uint32_t id) > SERVICE_VALID_GET_OR_ERR_RET(id, s, -EINVAL); >=20 > rte_service_count--; > - rte_smp_wmb(); >=20 > - s->internal_flags &=3D ~(SERVICE_F_REGISTERED); > + /* make sure the counter update before the state change. */ > + __atomic_and_fetch(&s->internal_flags, ~(SERVICE_F_REGISTERED), > + __ATOMIC_RELEASE); >=20 > /* clear the run-bit in all cores */ > for (i =3D 0; i < RTE_MAX_LCORE; i++) > @@ -301,11 +306,12 @@ rte_service_component_runstate_set(uint32_t id, uin= t32_t > runstate) > SERVICE_VALID_GET_OR_ERR_RET(id, s, -EINVAL); >=20 > if (runstate) > - s->comp_runstate =3D RUNSTATE_RUNNING; > + __atomic_store_n(&s->comp_runstate, RUNSTATE_RUNNING, > + __ATOMIC_RELEASE); > else > - s->comp_runstate =3D RUNSTATE_STOPPED; > + __atomic_store_n(&s->comp_runstate, RUNSTATE_STOPPED, > + __ATOMIC_RELEASE); >=20 > - rte_smp_wmb(); > return 0; > } > >=20 > @@ -316,11 +322,12 @@ rte_service_runstate_set(uint32_t id, uint32_t runs= tate) > SERVICE_VALID_GET_OR_ERR_RET(id, s, -EINVAL); >=20 > if (runstate) > - s->app_runstate =3D RUNSTATE_RUNNING; > + __atomic_store_n(&s->app_runstate, RUNSTATE_RUNNING, > + __ATOMIC_RELEASE); > else > - s->app_runstate =3D RUNSTATE_STOPPED; > + __atomic_store_n(&s->app_runstate, RUNSTATE_STOPPED, > + __ATOMIC_RELEASE); >=20 > - rte_smp_wmb(); > return 0; > } >=20 > @@ -442,7 +449,8 @@ service_runner_func(void *arg) > const int lcore =3D rte_lcore_id(); > struct core_state *cs =3D &lcore_states[lcore]; >=20 > - while (lcore_states[lcore].runstate =3D=3D RUNSTATE_RUNNING) { > + while (__atomic_load_n(&cs->runstate, > + __ATOMIC_ACQUIRE) =3D=3D RUNSTATE_RUNNING) { > const uint64_t service_mask =3D cs->service_mask; >=20 > for (i =3D 0; i < RTE_SERVICE_NUM_MAX; i++) { > @@ -453,8 +461,6 @@ service_runner_func(void *arg) > } >=20 > cs->loops++; > - > - rte_smp_rmb(); > } >=20 > lcore_config[lcore].state =3D WAIT; > @@ -663,9 +669,8 @@ rte_service_lcore_add(uint32_t lcore) >=20 > /* ensure that after adding a core the mask and state are defaults */ > lcore_states[lcore].service_mask =3D 0; > - lcore_states[lcore].runstate =3D RUNSTATE_STOPPED; > - > - rte_smp_wmb(); > + __atomic_store_n(&lcore_states[lcore].runstate, RUNSTATE_STOPPED, > + __ATOMIC_RELEASE); >=20 > return rte_eal_wait_lcore(lcore); > } > -- > 2.7.4