From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C4E92A04DB; Thu, 15 Oct 2020 14:31:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A9C521C039; Thu, 15 Oct 2020 14:31:55 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 3005E1BAE5 for ; Thu, 15 Oct 2020 14:31:53 +0200 (CEST) IronPort-SDR: 3opHo/6NU9cp4Z/QUm2jrAcFrMDeFiOt2eYKiFPX29CMimNYCJqJ0L1sl36rSYquf0QgkhzOPB XX/zIprinvWw== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="146192368" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="146192368" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 05:31:49 -0700 IronPort-SDR: RFjPy8xPS4dinBS+KFioXFuswiNz/Q/XlDd0T96O9pk7anZK4PzrfimY9bWTAbLjGjCxjmPhxk QDZWvKBPahwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="531239189" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga005.jf.intel.com with ESMTP; 15 Oct 2020 05:31:49 -0700 Received: from fmsmsx608.amr.corp.intel.com (10.18.126.88) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 15 Oct 2020 05:31:49 -0700 Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by fmsmsx608.amr.corp.intel.com (10.18.126.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 15 Oct 2020 05:31:48 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 15 Oct 2020 05:31:42 -0700 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (104.47.58.105) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Thu, 15 Oct 2020 05:31:42 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=F/X98M6ko1Rvc6o4iRNy6qeHTTMG7d58ZOwaS7vEkRfVbTdyeRVMyqDuleZP0JS3XDxapw9sfp2ob4/xpGuANd9UgNdrhdrPcowyuHGCV0o0M51pVcytia1IpwN33nQZnGIMQgALKxlSgw6z7m5l8N2bJ299OCGYHqSADrhE2crYfNsI/YTCFIRzLAN64VL1PQXwItWCNzKvgqwT/KWdnSZ+opDkqWIwBTzal0qggBUxJq+VcW/DXKfG6wGUkKo6s/m4m0KoSd+uN+iuDJd/hEab5RlJORtZSvtuItQa1ObvvI21BZvuHbM+EjHi94dkKAG7zAHBcM9LJWrrHS9//g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HDT3xVdrA33MzkJ2sJXBQje3kLyM0xSR8otQDvH7IRA=; b=K6zW2GijQzQJ9oufCKGGD3L05qFKyRX0xxDbarz5VEPmiGCWw9aSEu7TrulL0RSVOCJEgYAtLBz3Ek9Q89EkFCnAgrrvdqDQoVt6NLkAhCOobWIGsSAdQmY43lcTmk/Auiy39ZvJrTO1mb7tCHJigPB7Bnk4jKhNzbn51FOukxEozofkDxhXj1EtU46GtMihAga+l8MRr2TOzKZEsgNonvmO8ZQs17+Od+C9bshYlYR4ho6ZRjLVSP+lP5cVlaf59VEt+YLWljFijJhUdV4WaLymtD5ktgRJYGlXeMkgjOrvKZ6nh+yjv1tPDL9NTRWlCDTL5pHJfY4x0KMKtjSo7Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HDT3xVdrA33MzkJ2sJXBQje3kLyM0xSR8otQDvH7IRA=; b=ESmT9voY0W9Lrj0JazPdapApc3y1VgfTfULHlIpaI4uCifjiqomEUHbXlzUF1pw8bWONdc0WtFWOMF+XyAk1Y63ovoVADEizDJVHBtYs70Z6aKYqRVjTs5FESkPdQvoFyFsJ135gKsKy7f4IfBk7+H9AINrxturZpjLaTF/E6do= Received: from BYAPR11MB3301.namprd11.prod.outlook.com (2603:10b6:a03:7f::26) by BYAPR11MB2680.namprd11.prod.outlook.com (2603:10b6:a02:c9::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.21; Thu, 15 Oct 2020 12:31:40 +0000 Received: from BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f5a4:3f6b:ade3:296b]) by BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f5a4:3f6b:ade3:296b%3]) with mapi id 15.20.3477.021; Thu, 15 Oct 2020 12:31:40 +0000 From: "Ananyev, Konstantin" To: "Power, Ciara" , "dev@dpdk.org" CC: "viktorin@rehivetech.com" , "ruifeng.wang@arm.com" , "jerinj@marvell.com" , "drc@linux.vnet.ibm.com" , "Richardson, Bruce" Thread-Topic: [PATCH v6 18/18] acl: add checks for max SIMD bitwidth Thread-Index: AQHWot9tzfxtga/1Yku1tryQozcSJqmYj5hw Date: Thu, 15 Oct 2020 12:31:40 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> <20201015103814.253636-19-ciara.power@intel.com> In-Reply-To: <20201015103814.253636-19-ciara.power@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [46.7.39.127] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9a5a6efb-fd2f-4460-32dd-08d87106447d x-ms-traffictypediagnostic: BYAPR11MB2680: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 9yjmYoBOmtss47wiIecB3LbMJafgfnLy3bH+dTWLjbpa9DKzxmqsljn+2HRs69g4p0SbTQ5g6Ko7KVGzL/iEPD48NN6PP2Pz77h5C9wrr26oO9sMmc36zGUB9SC/y3o7APnimahjIJdrYy0Qeu9lo1zlwphRDFMqR/zdweFMXcgPexZ0vxGN0xssaeuYcWBtFkw4T/bBcAcZXFnvufDxbRSgnRNmqJ+chmj/mneAmnBv0Kx90Bpjn8c0fh36af2H/UYRskkdHk13lqSf+z0jup88edwMIfuRV14J3phc/04R9nEK8qqX4u58hagTkQmvmJcqQzBksXt2Nwwo8JyfDQ== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BYAPR11MB3301.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(396003)(346002)(376002)(39860400002)(366004)(136003)(83380400001)(107886003)(86362001)(186003)(66556008)(478600001)(55016002)(26005)(33656002)(66476007)(66446008)(66946007)(64756008)(76116006)(2906002)(8676002)(71200400001)(4326008)(110136005)(7696005)(316002)(54906003)(6506007)(9686003)(5660300002)(8936002)(52536014); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: YA7ZDrJeRb6QhbfIdAUUaGcdyo9KFB+hOWP45D5KqG0mOnvW5ouq8l7aX/7jX3I1zqg604/mwXswn/bBpbpHQ3KOcApJ0gH8Mb9IvNzQP4sdIzlg4fc0Q9nbqnHLq4KB1SdmQhBeZrly0J1EWxFliLjTFdB/xRpP8faMsWqVGT4sirGsFw+sGhwTY+o13e3COGcEdSRlqhb9Y635teCxWdKirVyLmcuxzRAtEMGtmqaZBxtLIH6lUn6sd9G5kUvmMaB8Q1Hb9/11y8ZD4+GUki3XI7/s8OsKQisXsVP3xrKu/MEHlejI9ytXBzNOQlHejIXus960lgVP4GyXxRZarGROUwBLQORMX2H8Vglg1fJ//73tHrnKqNJ+ACBVoeu0shJAMeyfogrrBsgnEndqmT3QC7Y56GnfYHAbdL3a1T5To9n8Dv0kxIqWL57FnbUmptbbzR+hBz5RibM2zjqqHhRxPAg389UheiVLtzHSpM7zljdaDk5IdF6860i5WTN2RCVjTZVg/3C8SZq0eYzlSuted21rQwPWURvXzc4gEKRsc+ZMc1g9eyEjb7YqF6wgd6FzbcUi+sWD1lHR90xui+dgL9ehL5zdgTRT4OGWjZlweIzKhSNYcBFLC+IhqM7uO4I0YQif3MTsQZuHBDjZLQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9a5a6efb-fd2f-4460-32dd-08d87106447d X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Oct 2020 12:31:40.4374 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: olHThFcFLDX6Z+RQ4pDxV1Oq29jXGZ13D7XV5qMyXJ6+YeYgAKWG0hgVOQCkFu+KKaMn/6wV8Nn0iF0XQD9PZH7pgZ+QTzenmJ0Yxk/Q8bk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2680 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v6 18/18] acl: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > When choosing a vector path to take, an extra condition must be > satisfied to ensure the max SIMD bitwidth allows for the CPU enabled > path. These checks are added in the check alg helper functions. >=20 > Cc: Konstantin Ananyev >=20 > Signed-off-by: Ciara Power > --- > lib/librte_acl/rte_acl.c | 27 +++++++++++++++++++++------ > 1 file changed, 21 insertions(+), 6 deletions(-) I think we need to update PG for ACL (section " Classification methods") to reflect these changes.=20 And probably doxygen comments for rte_acl_set_ctx_classify() too. =20 > diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c > index 7c2f60b2d6..4ec6c982c9 100644 > --- a/lib/librte_acl/rte_acl.c > +++ b/lib/librte_acl/rte_acl.c > @@ -16,6 +16,8 @@ static struct rte_tailq_elem rte_acl_tailq =3D { > }; > EAL_REGISTER_TAILQ(rte_acl_tailq) >=20 > +uint16_t max_simd_bitwidth; > + > #ifndef CC_AVX512_SUPPORT > /* > * If the compiler doesn't support AVX512 instructions, > @@ -114,9 +116,13 @@ acl_check_alg_arm(enum rte_acl_classify_alg alg) > { > if (alg =3D=3D RTE_ACL_CLASSIFY_NEON) { > #if defined(RTE_ARCH_ARM64) > - return 0; > + if (max_simd_bitwidth >=3D RTE_SIMD_128) All these are control path functions. So no point to have local copy of max_simd_bitwidth. Here and in all other places within that file we can just call rte_get_max_simd_bitwidth() straightway. > + return 0; > + else > + return -ENOTSUP; > #elif defined(RTE_ARCH_ARM) > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && > + max_simd_bitwidth >=3D RTE_SIMD_128) > return 0; > return -ENOTSUP; > #else > @@ -136,7 +142,10 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg) > { > if (alg =3D=3D RTE_ACL_CLASSIFY_ALTIVEC) { > #if defined(RTE_ARCH_PPC_64) > - return 0; > + if (max_simd_bitwidth >=3D RTE_SIMD_128) > + return 0; > + else > + return -ENOTSUP; > #else > return -ENOTSUP; > #endif > @@ -158,7 +167,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) && > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW)) > + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) && > + max_simd_bitwidth >=3D RTE_SIMD_512) That's not exactly correct, as we have two algs (256 and 512 bit-width) for= avx512. So we have to check different max-simd valued for different algorithms. Something like that: static int acl_check_avx512_cpu_flags(void) { return (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW)); } =20 static int acl_check_alg_x86(enum rte_acl_classify_alg alg) { if (alg =3D=3D RTE_ACL_CLASSIFY_AVX512X32) { #ifdef CC_AVX512_SUPPORT if (acl_check_avx512_cpu_flags) !=3D 0 && rte_get_max_simd_bitwidth() >=3D RTE_SIMD_512) return 0; #endif return -ENOTSUP; if (alg =3D=3D RTE_ACL_CLASSIFY_AVX512X16) { #ifdef CC_AVX512_SUPPORT if (acl_check_avx512_cpu_flags) !=3D 0 && rte_get_max_simd_bitwidth() >=3D RTE_SIMD_256) return 0; #endif return -ENOTSUP; if (alg =3D=3D RTE_ACL_CLASSIFY_AVX2) {=09 .... > return 0; > #endif > return -ENOTSUP; > @@ -166,7 +176,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) >=20 > if (alg =3D=3D RTE_ACL_CLASSIFY_AVX2) { > #ifdef CC_AVX2_SUPPORT > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && > + max_simd_bitwidth >=3D RTE_SIMD_256) > return 0; > #endif > return -ENOTSUP; > @@ -174,7 +185,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) >=20 > if (alg =3D=3D RTE_ACL_CLASSIFY_SSE) { > #ifdef RTE_ARCH_X86 > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1)) > + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) && > + max_simd_bitwidth >=3D RTE_SIMD_128) > return 0; > #endif > return -ENOTSUP; > @@ -406,6 +418,9 @@ rte_acl_create(const struct rte_acl_param *param) > TAILQ_INSERT_TAIL(acl_list, te, next); > } >=20 > + if (max_simd_bitwidth =3D=3D 0) > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); > + > exit: > rte_mcfg_tailq_write_unlock(); > return ctx; > -- > 2.22.0