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Sun, 11 Oct 2020 22:31:23 +0000 From: "Ananyev, Konstantin" To: "Wang, Haiyue" , "Power, Ciara" , "dev@dpdk.org" CC: "Zhao1, Wei" , "Guo, Jia" Thread-Topic: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth Thread-Index: AQHWnwcwUZM2Ls0kRU2K6Ml7fI6vaamS/SrA Date: Sun, 11 Oct 2020 22:31:23 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-12-ciara.power@intel.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [46.7.39.127] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8a52cb7c-09b0-426c-7b3b-08d86e35622b x-ms-traffictypediagnostic: SJ0PR11MB4813: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8a52cb7c-09b0-426c-7b3b-08d86e35622b X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Oct 2020 22:31:23.0435 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ABO52h6KOIYZtwK6vTYvx+SnRuK498RyGfIaaNaz5w3SDBJP+WgrumLppLIm0UpnKrg6ddrr0XkT/HK0uC+8wHWz+rIf192xzLLF1mpP/K0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB4813 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > From: Power, Ciara > > Sent: Wednesday, September 30, 2020 21:04 > > To: dev@dpdk.org > > Cc: Power, Ciara ; Zhao1, Wei ; Guo, Jia > > ; Wang, Haiyue > > Subject: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth > > > > When choosing a vector path to take, an extra condition must be > > satisfied to ensure the max SIMD bitwidth allows for the CPU enabled > > path. > > > > Cc: Wei Zhao > > Cc: Jeff Guo > > > > Signed-off-by: Ciara Power > > --- > > drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_r= xtx.c > > index 977ecf5137..eadc7183f2 100644 > > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > > @@ -2503,7 +2503,9 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, st= ruct ixgbe_tx_queue *txq) > > dev->tx_pkt_prepare =3D NULL; > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > - ixgbe_txq_vec_setup(txq) =3D=3D 0)) { > > + ixgbe_txq_vec_setup(txq) =3D=3D 0) && > > + rte_get_max_simd_bitwidth() >=20 > As Konstantin mentioned: " I think it is a bit safer to do all checks fir= st before > doing txq_vec_setup()." >=20 > Fox x86 & arm platforms, the setup is always 0, since 'sw_ring_v' is unio= n with > 'sw_ring' which is initialize at 'ixgbe_dev_tx_queue_setup'. >=20 > union { > struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scalar PMD.= */ > struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector = PMD */ > }; >=20 > static inline int > ixgbe_txq_vec_setup_default(struct ixgbe_tx_queue *txq, > const struct ixgbe_txq_ops *txq_ops) > { > if (txq->sw_ring_v =3D=3D NULL) > return -1; >=20 > /* leave the first one for overflow */ > txq->sw_ring_v =3D txq->sw_ring_v + 1; > txq->ops =3D txq_ops; >=20 > return 0; > } >=20 > So we need check the SIMD bitwidth firstly to avoid changing the sw_ring*= pointer address. >=20 >=20 > Also, looks like we need to add check on: >=20 > int > ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) > { > struct ixgbe_tx_queue *txq =3D (struct ixgbe_tx_queue *)tx_queue; > if (txq->offloads =3D=3D 0 && > #ifdef RTE_LIBRTE_SECURITY > !(txq->using_ipsec) && > #endif > txq->tx_rs_thresh >=3D RTE_PMD_IXGBE_TX_MAX_BURST) { > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > <-------------------= Add the same check > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > txq->sw_ring_v !=3D NULL)) { > return ixgbe_tx_done_cleanup_vec(txq, free_cnt); Could you probably explain a bit more why it is needed? > } else { > return ixgbe_tx_done_cleanup_simple(txq, free_cnt); > } > } >=20 > > + >=3D RTE_MAX_128_SIMD) { > > PMD_INIT_LOG(DEBUG, "Vector tx enabled."); > > dev->tx_pkt_burst =3D ixgbe_xmit_pkts_vec; > > } else > > @@ -4743,7 +4745,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev) > > * conditions to be met and Rx Bulk Allocation should be allowed. > > */ > > if (ixgbe_rx_vec_dev_conf_condition_check(dev) || > > - !adapter->rx_bulk_alloc_allowed) { > > + !adapter->rx_bulk_alloc_allowed || > > + rte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) { > > PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx " > > "preconditions", > > dev->data->port_id); > > -- > > 2.17.1