From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5446A04B5; Tue, 12 Jan 2021 16:56:51 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7A6A6140E0A; Tue, 12 Jan 2021 16:56:51 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id B60BE140DF2 for ; Tue, 12 Jan 2021 16:56:49 +0100 (CET) IronPort-SDR: GIj8Mfa3/P69He3bt4htrbTYUb5qw5aApRagZIfhvSZqNWeQ9EQ/WaQqGAtMiZmaMbQ/sQcxVB jEx50IPVRiYQ== X-IronPort-AV: E=McAfee;i="6000,8403,9862"; a="242129390" X-IronPort-AV: E=Sophos;i="5.79,341,1602572400"; d="scan'208";a="242129390" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2021 07:56:48 -0800 IronPort-SDR: 6Ob8QH3CavCRAxKD/fcJhMU8/hnISiH/31jeeGv9PGTFHu8Fj3M59Ezf4CenLHwleWWCb93OVG rR8m6M8T4gUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,341,1602572400"; d="scan'208";a="363539043" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by orsmga002.jf.intel.com with ESMTP; 12 Jan 2021 07:56:48 -0800 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 12 Jan 2021 07:56:48 -0800 Received: from orsmsx606.amr.corp.intel.com (10.22.229.19) by ORSMSX611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 12 Jan 2021 07:56:47 -0800 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx606.amr.corp.intel.com (10.22.229.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Tue, 12 Jan 2021 07:56:47 -0800 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.174) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Tue, 12 Jan 2021 07:56:46 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z8TxldNCkc2FtUiuCNzvPMpm9ExTfbQE371Eh/Vi9edLXwBhYOht3r3lkxe8TRm7EoAoy5oLx97VlgeWemt4MaIaUMfp9UHU9XRf00Ue3QGbnF5VWoU8ZFnyLDQ+S0LS9ILBkEqtzjmS0IwmGw4UrwzWASxYRLZQP0M6jypDDebsNx1rwBP3w2qdrzEncW2L6ZC6RHE0RZwaGrWTXIwOzVDT/vZK139I66JF2i8DOLb+92XmTnOvbR0whVD9Ar+s0qKpboWvSbqAcizmz0lPGHw/RyI+18usmnSp0r+Xg+6VjNqo9T/0yptkL1qfrLpkg5WBj2hgTAWZw3X1j1qyFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S8j4QHqxUA/A4TKVqiK7i+vyxdP1miUl4EnwspIONiE=; b=b6L8p9nAetZ1GFPk9/AEyWi1LxF20lf+NVPj1KNQ29g3606XWl1PC/oKrcMMMFa4EWPZbuQFohL5bbE3LWgfq4qKk/ytiyPk2h/GJOw6XUIRPU3y7WZ54b/WoqqfJVfq4mbVUfbC253L9pq8GF8SFgdnelzmSJOqCch/rv3UiyobPk/+IvePCzKaQ5SI67fvG7s6cGpFTVj0ByMYWwK3jMCNEnyNJ5W9dkFJsubje7obxxAHFhvLEiH4RUTU2xkcVS7kkPLQpiAUis6WvTcutHWs83JMVlpmf/+aHoFpFc43JJfwTf80eFuhRaiFKdXiKRD7mbqBzCRvlbnLkxtDaA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S8j4QHqxUA/A4TKVqiK7i+vyxdP1miUl4EnwspIONiE=; b=ORbPntb0lB9wbjKUeFDxMb5HCszcpGPL66suyCBgnnSGHJT/INPSOuwZiRYoGJunkj7yYLszAbzwfHBz8tdbbwC7fyJPYPOTy/hnfBAKGpGIlQjyNTcopmxcl+SrcGxrvDsCjWbrp8/bdTfATnFZpU3CAlIeXcwBurLzku+3jJU= Received: from BYAPR11MB3301.namprd11.prod.outlook.com (2603:10b6:a03:7f::26) by BY5PR11MB4308.namprd11.prod.outlook.com (2603:10b6:a03:1b9::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3742.8; Tue, 12 Jan 2021 15:56:22 +0000 Received: from BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::1152:1426:8a4f:c755]) by BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::1152:1426:8a4f:c755%4]) with mapi id 15.20.3742.012; Tue, 12 Jan 2021 15:56:22 +0000 From: "Ananyev, Konstantin" To: "Burakov, Anatoly" , "dev@dpdk.org" CC: "Richardson, Bruce" , "thomas@monjalon.net" , "gage.eads@intel.com" , "McDaniel, Timothy" , "Hunt, David" , "Macnamara, Chris" Thread-Topic: [PATCH v13 02/11] eal: avoid invalid API usage in power intrinsics Thread-Index: AQHW5eWkj1bEfAaGd0mbbByM4D0CKqokKv3w Date: Tue, 12 Jan 2021 15:56:22 +0000 Message-ID: References: <9e0c326baaa662afc224449699d7068ca9a6790d.1610127361.git.anatoly.burakov@intel.com> In-Reply-To: <9e0c326baaa662afc224449699d7068ca9a6790d.1610127361.git.anatoly.burakov@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [46.7.39.127] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5f4bbf65-4d37-410e-05f9-08d8b7129c0f x-ms-traffictypediagnostic: BY5PR11MB4308: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: osGUSqCYGwJbeeVlr1midGLX8MXd+UzKe4lzMHuz6ILMh7QeNKGDBfBwfu9lB/NKfntkusCu9gUJaFWSRiUNtFAhzZthyGxxFZ4S5TPy8NL0967xV4D89RjX942WD5C33z44S9f3GzlHmwfPE4z78qDHjsAT+TkzOYhAcwxx//EQaqu+Rpv2GN5vcq13UzNljc0GxUqKVxWZRUunlHCVhFmeqkSluuAUPh7Ne1axRyWGwDPEpyP7RIpCNYXFUY2WSG/Y7x/2NI9H7pKrNMGeB16mhKGjIY6f64LqKBYiyv9I7S/+LxpkHV+XZTEzgLe5tJvaxPvdGGWWRWzvEDqHnJn21rlfZg/ce4vLxBGrfYVd9LNMEj9rNFeXmyxmF4/0zDCaBzlJnmPI4u1AfTrRfQ== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BYAPR11MB3301.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(346002)(366004)(396003)(376002)(136003)(39860400002)(66446008)(66556008)(64756008)(66476007)(66946007)(2906002)(9686003)(5660300002)(478600001)(107886003)(52536014)(4326008)(8676002)(7696005)(76116006)(86362001)(71200400001)(83380400001)(6506007)(186003)(316002)(110136005)(8936002)(33656002)(26005)(54906003)(55016002); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: =?us-ascii?Q?36J5QQk+WLRrLFoeHxlDOaWbsxAZCGM52MWjY/UpanDXcqhYZkIMMfYocpO+?= =?us-ascii?Q?lCiu9nyns/kyS7QXPvv1S/BnrF1SOLzEbm+v4OPLGJo4hZJHJ/SQ3iXA0BCy?= =?us-ascii?Q?ZQ1ALUw895qaPY6mtqTMgWZkWOnMZaqA9LCR7sOxpdAsBSYRB5gF4H6W2uoI?= =?us-ascii?Q?+LMzbZ+p7dUaLwkGI8T52d3n/cKddDzHDQhaJ6U5G6JCVoyRZ9NGZcH7QNlf?= =?us-ascii?Q?TEcGagBDlUs6qV8rs1YxUsftKhkrE2nG97bqk59Wdt4uTSSsSuCqTSOV3Kjv?= =?us-ascii?Q?3Jg2+5NGkxUNPIpnBao93egzLTcGj0JfhR5hpG9QQFuPtTpCLvhmSVMV5Ern?= =?us-ascii?Q?VbGL6n5SMQfcz1WacmVNsErwW5GEfu+tKAdSiyxq4lVg810Yk+3xGBO84i8B?= =?us-ascii?Q?YVWQSrBV7gH7hTZt3Qxfyc3rrosh5OGkHmO/atnjtJMmsJZWGuKy7vZiE1Vs?= =?us-ascii?Q?+UYO2q9XchiXhr5yRItTfbIPdXQK7if24U38aBTNzAkP7Q5WzoGIRj3ykVmY?= =?us-ascii?Q?dXnTg4OCEzCRx2AQEpaWqiLjEeVmuCAxP2pydHroANBBt5NrOT4n48jVatVE?= =?us-ascii?Q?I04GnOMPDyDCqCyl2oQCRocLVLaqWKeNL56lEMPy77i63bmFaOLkYmHBYN8k?= =?us-ascii?Q?GXUNA9pWfR2g1+gfN6RmcMGzW1GjUmseMETbg2nSFjLaHS875w6PeRYCpEle?= =?us-ascii?Q?MMpGUOB7qsJUvwVNRR7EB3i7ZarhwVMzx6AvCLYKLccoed7f+fSjL1Ps+cpV?= =?us-ascii?Q?T2PXeo7xuR/FLMo8QbykvTkURzxXmDD8MXlzxNkq3GL6Y8vyMe1gGcmc6UwW?= =?us-ascii?Q?3jq3kb36pZQKrdxWx4hWnFnzOMb2zROwfbTjwA+x7sliJpgIBOb4YtO3j3ul?= =?us-ascii?Q?UoWeDwvGFrnvTmdj8GpCf1yPjM9fm2w6c1HhuBMk2a9Akfln52NTjN3tMWG3?= =?us-ascii?Q?OQGibVms612LZjCJv5ba7tiah5qxUaPWKfmHETMmHIU=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5f4bbf65-4d37-410e-05f9-08d8b7129c0f X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jan 2021 15:56:22.7180 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9PDHvGraEPN52+5XmI5KKAX6+PEVajFpaTheUfaIlttVPC05ZscT/kIOmi3HgQbVVRBIPGFrVwdk8KhcMaMQtUQNVSr2peNeo1QibFyybSc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4308 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v13 02/11] eal: avoid invalid API usage in power intrinsics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > Currently, the API documentation mandates that if the user wants to use > the power management intrinsics, they need to call the > `rte_cpu_get_intrinsics_support` API and check support for specific > intrinsics. >=20 > However, if the user does not do that, it is possible to get illegal > instruction error because we're using raw instruction opcodes, which may > or may not be supported at runtime. >=20 > Now that we have everything in a C file, we can check for support at > startup and prevent the user from possibly encountering illegal > instruction errors. >=20 > Signed-off-by: Anatoly Burakov > --- > .../include/generic/rte_power_intrinsics.h | 3 -- > lib/librte_eal/x86/rte_power_intrinsics.c | 31 +++++++++++++++++-- > 2 files changed, 28 insertions(+), 6 deletions(-) >=20 > diff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/= librte_eal/include/generic/rte_power_intrinsics.h > index 67977bd511..ffa72f7578 100644 > --- a/lib/librte_eal/include/generic/rte_power_intrinsics.h > +++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h > @@ -34,7 +34,6 @@ > * > * @warning It is responsibility of the user to check if this function i= s > * supported at runtime using `rte_cpu_get_intrinsics_support()` API c= all. > - * Failing to do so may result in an illegal CPU instruction error. > * > * @param p > * Address to monitor for changes. > @@ -75,7 +74,6 @@ void rte_power_monitor(const volatile void *p, > * > * @warning It is responsibility of the user to check if this function i= s > * supported at runtime using `rte_cpu_get_intrinsics_support()` API c= all. > - * Failing to do so may result in an illegal CPU instruction error. > * > * @param p > * Address to monitor for changes. > @@ -111,7 +109,6 @@ void rte_power_monitor_sync(const volatile void *p, > * > * @warning It is responsibility of the user to check if this function i= s > * supported at runtime using `rte_cpu_get_intrinsics_support()` API c= all. > - * Failing to do so may result in an illegal CPU instruction error. > * > * @param tsc_timestamp > * Maximum TSC timestamp to wait for. Note that the wait behavior is > diff --git a/lib/librte_eal/x86/rte_power_intrinsics.c b/lib/librte_eal/x= 86/rte_power_intrinsics.c > index 34c5fd9c3e..b48a54ec7f 100644 > --- a/lib/librte_eal/x86/rte_power_intrinsics.c > +++ b/lib/librte_eal/x86/rte_power_intrinsics.c > @@ -4,6 +4,8 @@ >=20 > #include "rte_power_intrinsics.h" >=20 > +static uint8_t wait_supported; > + > static inline uint64_t > __get_umwait_val(const volatile void *p, const uint8_t sz) > { > @@ -35,6 +37,11 @@ rte_power_monitor(const volatile void *p, const uint64= _t expected_value, > { > const uint32_t tsc_l =3D (uint32_t)tsc_timestamp; > const uint32_t tsc_h =3D (uint32_t)(tsc_timestamp >> 32); > + > + /* prevent user from running this instruction if it's not supported */ > + if (!wait_supported) > + return; > + > /* > * we're using raw byte codes for now as only the newest compiler > * versions support this instruction natively. > @@ -72,6 +79,11 @@ rte_power_monitor_sync(const volatile void *p, const u= int64_t expected_value, > { > const uint32_t tsc_l =3D (uint32_t)tsc_timestamp; > const uint32_t tsc_h =3D (uint32_t)(tsc_timestamp >> 32); > + > + /* prevent user from running this instruction if it's not supported */ > + if (!wait_supported) > + return; > + > /* > * we're using raw byte codes for now as only the newest compiler > * versions support this instruction natively. > @@ -112,9 +124,22 @@ rte_power_pause(const uint64_t tsc_timestamp) > const uint32_t tsc_l =3D (uint32_t)tsc_timestamp; > const uint32_t tsc_h =3D (uint32_t)(tsc_timestamp >> 32); >=20 > + /* prevent user from running this instruction if it's not supported */ > + if (!wait_supported) > + return; > + > /* execute TPAUSE */ > asm volatile(".byte 0x66, 0x0f, 0xae, 0xf7;" > - : /* ignore rflags */ > - : "D"(0), /* enter C0.2 */ > - "a"(tsc_l), "d"(tsc_h)); > + : /* ignore rflags */ > + : "D"(0), /* enter C0.2 */ > + "a"(tsc_l), "d"(tsc_h)); > +} > + > +RTE_INIT(rte_power_intrinsics_init) { > + struct rte_cpu_intrinsics i; > + > + rte_cpu_get_intrinsics_support(&i); > + > + if (i.power_monitor && i.power_pause) > + wait_supported =3D 1; > } > -- Acked-by: Konstantin Ananyev > 2.25.1