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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a81ca965-7088-427d-3f2a-08d81c1492e6 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jun 2020 10:09:56.0143 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: IbZbIGPqFJgG3jmIIir4i4ilnjgiMEXsT9Hxt4TsVQ71EHpk/CXRVqEMx2ahZ9v2DprYLcCJ7x9ZjHJz318s0V2JpmPURukpAzho50L2pHY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB3973 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v5 4/4] eal/atomic: add wrapper for c11 atomic thread fence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > >=20 > > Subject: [PATCH v5 4/4] eal/atomic: add wrapper for c11 atomic thread f= ence > > > > Provide a wrapper for __atomic_thread_fence built-in to support optimiz= ed > > code for __ATOMIC_SEQ_CST memory order for x86 platforms. > > > > Suggested-by: Honnappa Nagarahalli > > Signed-off-by: Phil Yang > > Reviewed-by: Ola Liljedahl > > --- > > lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++++ > > lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++++ > > lib/librte_eal/include/generic/rte_atomic.h | 6 ++++++ > > lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++++ > > lib/librte_eal/x86/include/rte_atomic.h | 17 +++++++++++++++++ > > 5 files changed, 41 insertions(+) > > > > diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h > > b/lib/librte_eal/arm/include/rte_atomic_32.h > > index 7dc0d06..dbe7cc6 100644 > > --- a/lib/librte_eal/arm/include/rte_atomic_32.h > > +++ b/lib/librte_eal/arm/include/rte_atomic_32.h > > @@ -37,6 +37,12 @@ extern "C" { > > > > #define rte_cio_rmb() rte_rmb() > > > > +static __rte_always_inline void > > +rte_atomic_thread_fence(int mo) > > +{ > > + __atomic_thread_fence(mo); > > +} > > + > > #ifdef __cplusplus > > } > > #endif > > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h > > b/lib/librte_eal/arm/include/rte_atomic_64.h > > index 7b7099c..22ff8ec 100644 > > --- a/lib/librte_eal/arm/include/rte_atomic_64.h > > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h > > @@ -41,6 +41,12 @@ extern "C" { > > > > #define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory") > > > > +static __rte_always_inline void > > +rte_atomic_thread_fence(int mo) > > +{ > > + __atomic_thread_fence(mo); > > +} > > + > > /*------------------------ 128 bit atomic operations -----------------= --------*/ > > > > #if defined(__ARM_FEATURE_ATOMICS) || > > defined(RTE_ARM_FEATURE_ATOMICS) diff --git > > a/lib/librte_eal/include/generic/rte_atomic.h > > b/lib/librte_eal/include/generic/rte_atomic.h > > index e6ab15a..5b941db 100644 > > --- a/lib/librte_eal/include/generic/rte_atomic.h > > +++ b/lib/librte_eal/include/generic/rte_atomic.h > > @@ -158,6 +158,12 @@ static inline void rte_cio_rmb(void); > > asm volatile ("" : : : "memory"); \ > > } while(0) > > > > +/** > > + * Synchronization fence between threads based on the specified > > + * memory order. > > + */ > > +static inline void rte_atomic_thread_fence(int mo); > > + > > /*------------------------- 16 bit atomic operations -----------------= --------*/ > > > > /** > > diff --git a/lib/librte_eal/ppc/include/rte_atomic.h > > b/lib/librte_eal/ppc/include/rte_atomic.h > > index 7e3e131..91c5f30 100644 > > --- a/lib/librte_eal/ppc/include/rte_atomic.h > > +++ b/lib/librte_eal/ppc/include/rte_atomic.h > > @@ -40,6 +40,12 @@ extern "C" { > > > > #define rte_cio_rmb() rte_rmb() > > > > +static __rte_always_inline void > > +rte_atomic_thread_fence(int mo) > > +{ > > + __atomic_thread_fence(mo); > > +} > > + > > /*------------------------- 16 bit atomic operations -----------------= --------*/ > > /* To be compatible with Power7, use GCC built-in functions for 16 bit > > * operations */ > > diff --git a/lib/librte_eal/x86/include/rte_atomic.h > > b/lib/librte_eal/x86/include/rte_atomic.h > > index b9dcd30..bd256e7 100644 > > --- a/lib/librte_eal/x86/include/rte_atomic.h > > +++ b/lib/librte_eal/x86/include/rte_atomic.h > > @@ -83,6 +83,23 @@ rte_smp_mb(void) > > > > #define rte_cio_rmb() rte_compiler_barrier() > > > > +/** > > + * Synchronization fence between threads based on the specified > > + * memory order. > > + * > > + * On x86 the __atomic_thread_fence(__ATOMIC_SEQ_CST) generates > > + * full 'mfence' which is quite expensive. The optimized > > + * implementation of rte_smp_mb is used instead. > > + */ > > +static __rte_always_inline void > > +rte_atomic_thread_fence(int mo) > > +{ > > + if (mo =3D=3D __ATOMIC_SEQ_CST) > > + rte_smp_mb(); > > + else > > + __atomic_thread_fence(mo); > > +} > I think __ATOMIC_SEQ_CST needs to be used rarely. IMO, rte_atomic_thread_= fence should be called only for __ATOMIC_SEQ_CST memory > order. For all others the __atomic_thread_fence can be used directly. Thi= s will help us to stick to using the atomic built-ins in most of the > cases. >=20 > Konstantin, is this ok for you? My preference is to have one generic rte_atomic_thread_fence() for all case= s (I.E - current Phil implementation looks good to me). I think it is more consistent approach and would help to avoid confusion. Konstantin