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Mon, 29 Jun 2020 10:13:53 +0000 From: "Ananyev, Konstantin" To: Phil Yang , "dev@dpdk.org" CC: "mattias.ronnblom@ericsson.com" , "mb@smartsharesystems.com" , "stephen@networkplumber.org" , "thomas@monjalon.net" , "Richardson, Bruce" , "Yigit, Ferruh" , "hemant.agrawal@nxp.com" , "jerinj@marvell.com" , "ktraynor@redhat.com" , "maxime.coquelin@redhat.com" , "olivier.matz@6wind.com" , "Van Haaren, Harry" , "Carrillo, Erik G" , "drc@linux.vnet.ibm.com" , "david.marchand@redhat.com" , "Chen, Zhaoyan" , "ola.liljedahl@arm.com" , "honnappa.nagarahalli@arm.com" , "ruifeng.wang@arm.com" , "nd@arm.com" Thread-Topic: [PATCH v5 4/4] eal/atomic: add wrapper for c11 atomic thread fence Thread-Index: AQHWMzxzR+3Hct8b4UODZRKPbe5xi6jvlVrQ Date: Mon, 29 Jun 2020 10:13:53 +0000 Message-ID: References: <1589270586-4480-1-git-send-email-phil.yang@arm.com> <1590483667-10318-1-git-send-email-phil.yang@arm.com> <1590483667-10318-5-git-send-email-phil.yang@arm.com> In-Reply-To: <1590483667-10318-5-git-send-email-phil.yang@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: arm.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1f551ef0-3799-4efd-0376-08d81c152058 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jun 2020 10:13:53.4195 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fivwA6HsxjbT3tQUWLBTqhsbP8kTvaG3In6lFn+3CPk5sYu4TZMF6pNcw2Kynxu7HShgTBGIjR6mbRwzz0CxCStwXVqmLGE5CjbYJwH9kRI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB3973 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v5 4/4] eal/atomic: add wrapper for c11 atomic thread fence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > Provide a wrapper for __atomic_thread_fence built-in to support > optimized code for __ATOMIC_SEQ_CST memory order for x86 platforms. >=20 > Suggested-by: Honnappa Nagarahalli > Signed-off-by: Phil Yang > Reviewed-by: Ola Liljedahl > --- > lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++++ > lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++++ > lib/librte_eal/include/generic/rte_atomic.h | 6 ++++++ > lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++++ > lib/librte_eal/x86/include/rte_atomic.h | 17 +++++++++++++++++ > 5 files changed, 41 insertions(+) >=20 > diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h b/lib/librte_eal/= arm/include/rte_atomic_32.h > index 7dc0d06..dbe7cc6 100644 > --- a/lib/librte_eal/arm/include/rte_atomic_32.h > +++ b/lib/librte_eal/arm/include/rte_atomic_32.h > @@ -37,6 +37,12 @@ extern "C" { >=20 > #define rte_cio_rmb() rte_rmb() >=20 > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + __atomic_thread_fence(mo); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/= arm/include/rte_atomic_64.h > index 7b7099c..22ff8ec 100644 > --- a/lib/librte_eal/arm/include/rte_atomic_64.h > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h > @@ -41,6 +41,12 @@ extern "C" { >=20 > #define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory") >=20 > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + __atomic_thread_fence(mo); > +} > + > /*------------------------ 128 bit atomic operations -------------------= ------*/ >=20 > #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS) > diff --git a/lib/librte_eal/include/generic/rte_atomic.h b/lib/librte_eal= /include/generic/rte_atomic.h > index e6ab15a..5b941db 100644 > --- a/lib/librte_eal/include/generic/rte_atomic.h > +++ b/lib/librte_eal/include/generic/rte_atomic.h > @@ -158,6 +158,12 @@ static inline void rte_cio_rmb(void); > asm volatile ("" : : : "memory"); \ > } while(0) >=20 > +/** > + * Synchronization fence between threads based on the specified > + * memory order. > + */ > +static inline void rte_atomic_thread_fence(int mo); > + > /*------------------------- 16 bit atomic operations -------------------= ------*/ >=20 > /** > diff --git a/lib/librte_eal/ppc/include/rte_atomic.h b/lib/librte_eal/ppc= /include/rte_atomic.h > index 7e3e131..91c5f30 100644 > --- a/lib/librte_eal/ppc/include/rte_atomic.h > +++ b/lib/librte_eal/ppc/include/rte_atomic.h > @@ -40,6 +40,12 @@ extern "C" { >=20 > #define rte_cio_rmb() rte_rmb() >=20 > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + __atomic_thread_fence(mo); > +} > + > /*------------------------- 16 bit atomic operations -------------------= ------*/ > /* To be compatible with Power7, use GCC built-in functions for 16 bit > * operations */ > diff --git a/lib/librte_eal/x86/include/rte_atomic.h b/lib/librte_eal/x86= /include/rte_atomic.h > index b9dcd30..bd256e7 100644 > --- a/lib/librte_eal/x86/include/rte_atomic.h > +++ b/lib/librte_eal/x86/include/rte_atomic.h > @@ -83,6 +83,23 @@ rte_smp_mb(void) >=20 > #define rte_cio_rmb() rte_compiler_barrier() >=20 > +/** > + * Synchronization fence between threads based on the specified > + * memory order. > + * > + * On x86 the __atomic_thread_fence(__ATOMIC_SEQ_CST) generates > + * full 'mfence' which is quite expensive. The optimized > + * implementation of rte_smp_mb is used instead. > + */ > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + if (mo =3D=3D __ATOMIC_SEQ_CST) > + rte_smp_mb(); > + else > + __atomic_thread_fence(mo); > +} > + > /*------------------------- 16 bit atomic operations -------------------= ------*/ >=20 > #ifndef RTE_FORCE_INTRINSICS > -- Acked-by: Konstantin Ananyev > 2.7.4