From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5FF60A04B6; Mon, 12 Oct 2020 18:25:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3F00C1D938; Mon, 12 Oct 2020 18:25:13 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 037351D938 for ; Mon, 12 Oct 2020 18:25:09 +0200 (CEST) IronPort-SDR: q9Jn1bnQCUCRFb9CWgSJX5DH5z7Py+RPw+U7Nd+eWQU1X4PVkusxLS+YiLiemCUEwmPu+b6UBX EjPKmr7hAF+w== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="229945941" X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="229945941" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2020 09:25:02 -0700 IronPort-SDR: +m3nWrcQPO741/L6FeVnWiw7GTi83Ii6cDMmk50Uhy5RSZQ6IKLkZlHX/XKHgjifwMZlisYOSa +wh/R7OfBnxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="463163313" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by orsmga004.jf.intel.com with ESMTP; 12 Oct 2020 09:25:00 -0700 Received: from fmsmsx608.amr.corp.intel.com (10.18.126.88) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 12 Oct 2020 09:25:00 -0700 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx608.amr.corp.intel.com (10.18.126.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 12 Oct 2020 09:25:00 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Mon, 12 Oct 2020 09:25:00 -0700 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (104.47.58.104) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Mon, 12 Oct 2020 09:24:58 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IkCnTtPs/1C/jVMEWJYwO2Z7FtIBqZ9eRni8vW66R/9grF8XScmfEwdjdpJOb+jIr9wCXWDa79DLybwsfP31V/oAGcVD4ZnU6i7nQx8dg/nMX8OlyLNQfxyIBKH82C0pCQ8WOMliY0qTvl3T6DsKDBecu2EiFS7pnc3piq5OW46GHYfMi1hccgSmb2bwWRRoi64Edv5y6NObRJrge1jMKS+V/c3NpyDh1blY0Nsirz62OwW9z9gdP8GSWexkgDOUqROLdzBVtLgbmZrTzoY2SVNqv6pX+rxxapLTRIlWY84+pfvaD8IXq/UZzl9wFWb8jwI1CfdA3ffo8j0EmUK3ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=L/WL7Ta1omhN0TaknV+IRPxFlUNwv+qHwbElBiujrx8=; b=ShjvbyrAHYcwthoFhPWvuaaiSg8XmK4kagI0mLXwgSURR/a4N2ep96hom69rGGQA+qEBKFJMpNikSks5cW7pdJGWjr+AQgrkvPYx+SJ5+Lz9CCx7u5FVDltov86WD4+cg1YUAT3ybM7nTubJWr7n/Lam0O6sHa6lon8RL7VtSoRHNEycKOKb1PQ1vY8elEkwB2HtMf/yt8EwW8LzHAF63lA1G5VT+mE+FxuSGcfUE95HfMGE6lZG+OjlTR7f2w489lRPsL9DzaMw8G8CMhWuwbJia9lK4cvwDOZLxaB6plhGWQX/GkVft8EeTtyb4dIVyQyPwVRZKstUybRm4TeceA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=L/WL7Ta1omhN0TaknV+IRPxFlUNwv+qHwbElBiujrx8=; b=u3wfsAOazEHXPP2mpXIJzNNkGBBAFfivMCdHzwJwgSYb8SHQJWhnFkGj7BOvTvCq+Txxo+qqJs077thfdrw7cfF6GsjrPosUjbUG3sPj2dUBbBDhGUwgkUvj1QQckWh5H8SvyP7sl+b4LpfHWvc5PdJuREFOmLsjLZgNvg5XPqc= Received: from BYAPR11MB3301.namprd11.prod.outlook.com (2603:10b6:a03:7f::26) by BYAPR11MB2725.namprd11.prod.outlook.com (2603:10b6:a02:c5::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.24; Mon, 12 Oct 2020 16:24:53 +0000 Received: from BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f5a4:3f6b:ade3:296b]) by BYAPR11MB3301.namprd11.prod.outlook.com ([fe80::f5a4:3f6b:ade3:296b%3]) with mapi id 15.20.3455.029; Mon, 12 Oct 2020 16:24:53 +0000 From: "Ananyev, Konstantin" To: "Wang, Haiyue" , "Power, Ciara" , "dev@dpdk.org" CC: "Zhao1, Wei" , "Guo, Jia" Thread-Topic: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth Thread-Index: AQHWnwcwUZM2Ls0kRU2K6Ml7fI6vaamS/SrAgAAzIACAAHaLMIAAfdeAgAAFEjA= Date: Mon, 12 Oct 2020 16:24:53 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> <20200930130415.11211-12-ciara.power@intel.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [46.7.39.127] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 847a34c9-378d-4d85-9033-08d86ecb59ac x-ms-traffictypediagnostic: BYAPR11MB2725: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: GPxtgjywLy56g4iP36rgf2sfCr4jpBGQbV81vbHIqOQXkQpmYZSjH5paJ/HRMj17rv1n/RHuAEZElNs7PDLdMZJ1Jk7/8uBhFklOIYQXl1heYfK0dFrpMV+2fQuLopyDZvpdb+R8CDvCwqAasODp1mkdtpV53J0aMAS5eF5JloAACAFsqV0gRZrNfNoGOtBjcMqole2JZAyZN6FH6hvvLDz3tSBa/Qkasduoa+XljELO7Tayz8MPuyR3Iu4ENMP6ss/fSS1QfgpZwgeBFzV3ME3g4tNBsi3EY+eFH19QTu7JIMZnIUX4NxmqQYZKbIkpKYTMWZrig2Ahn9/iiQMZyA== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BYAPR11MB3301.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(39860400002)(346002)(136003)(366004)(396003)(86362001)(8676002)(6506007)(33656002)(478600001)(2906002)(4326008)(107886003)(83380400001)(53546011)(9686003)(55016002)(8936002)(54906003)(64756008)(26005)(186003)(316002)(110136005)(66446008)(52536014)(76116006)(66946007)(71200400001)(66476007)(7696005)(5660300002)(66556008); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: 7pyH6HtX3HQCk14vayPVWgtlIMhlOtB4QvVGtXDApLAykSziyNJMBZ5uo3QakBm6g5+u7Xb/B+ZJwQF+SMtMlUYG9zbcCBEfVoCylN3tOymrSPeOtA2dJlITpx+Ss6MzL9TGKUC4wlpWzlmCXr+tt+uoLpkqt88i0dcEv45M0qve8UTNRo596ygRh7iWiNOLqbNNv27t8iGp8K9X+jkKFqAKtP+6zBXLvIi8NTIOayCzvhUK2PcYnXPSgK38bEwD6zPZaNGg8ssueum9wf+XyTm20qA/BDDOa+1HhL7fWVks3EHtGPWIBwJXH1gdmdx7jq9VIXCNFoYqVatZ7lJkiLovDCL+2WHdqIfPJPzIH6gYbJx3zEHEoEm6BbGSZMLzctQpmYxEhyEJnC15duvYJIWJkWGAxVxmzDAeGfV+NisICmYRznuGezt4rBeTiPL+Zq4YNY3Lt5mzs+WKMWzeSGAJSX8rEmQiS0WIYWrghhbKbLQ7S+kUgEM7jRMTMamoeeSVnXs5V7DdDNtMa87CnPs1zBUtduMQV6oOdAHS3+80U5V1tLIr1atS+k6shTEaFi3dhOxACifyG8OiGkdTY7BsCJHI3Sz4U7I/onMspK/M+q3TzZ/8HsqDj1onru2KK1JMHGD4BNw7h3YOSMcnDw== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3301.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 847a34c9-378d-4d85-9033-08d86ecb59ac X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2020 16:24:53.3503 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 08PHZme9l0z+GX9Brqhyp/qfoV/E933/CC6ES2tlorGLd/zWkjvnTad1AhQ8ZpoI90uc4Tfmqc8TyxYyK9IFgqaka4fRjLE5gzS26r0ZyZ4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2725 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > -----Original Message----- > > From: Ananyev, Konstantin > > Sent: Monday, October 12, 2020 17:09 > > To: Wang, Haiyue ; Power, Ciara ; dev@dpdk.org > > Cc: Zhao1, Wei ; Guo, Jia > > Subject: RE: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bitwid= th > > > > > > > > From: Power, Ciara > > > > > > Sent: Wednesday, September 30, 2020 21:04 > > > > > > To: dev@dpdk.org > > > > > > Cc: Power, Ciara ; Zhao1, Wei ; Guo, Jia > > > > > > ; Wang, Haiyue > > > > > > Subject: [PATCH v3 11/18] net/ixgbe: add checks for max SIMD bi= twidth > > > > > > > > > > > > When choosing a vector path to take, an extra condition must be > > > > > > satisfied to ensure the max SIMD bitwidth allows for the CPU en= abled > > > > > > path. > > > > > > > > > > > > Cc: Wei Zhao > > > > > > Cc: Jeff Guo > > > > > > > > > > > > Signed-off-by: Ciara Power > > > > > > --- > > > > > > drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++-- > > > > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe= /ixgbe_rxtx.c > > > > > > index 977ecf5137..eadc7183f2 100644 > > > > > > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > > > > > > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > > > > > > @@ -2503,7 +2503,9 @@ ixgbe_set_tx_function(struct rte_eth_dev = *dev, struct ixgbe_tx_queue > > *txq) > > > > > > dev->tx_pkt_prepare =3D NULL; > > > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > > > > - ixgbe_txq_vec_setup(txq) =3D=3D 0)) { > > > > > > + ixgbe_txq_vec_setup(txq) =3D=3D 0) && > > > > > > + rte_get_max_simd_bitwidth() > > > > > > > > > > As Konstantin mentioned: " I think it is a bit safer to do all ch= ecks first before > > > > > doing txq_vec_setup()." > > > > > > > > > > Fox x86 & arm platforms, the setup is always 0, since 'sw_ring_v'= is union with > > > > > 'sw_ring' which is initialize at 'ixgbe_dev_tx_queue_setup'. > > > > > > > > > > union { > > > > > struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for sca= lar PMD. */ > > > > > struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for= vector PMD */ > > > > > }; > > > > > > > > > > static inline int > > > > > ixgbe_txq_vec_setup_default(struct ixgbe_tx_queue *txq, > > > > > const struct ixgbe_txq_ops *txq_ops) > > > > > { > > > > > if (txq->sw_ring_v =3D=3D NULL) > > > > > return -1; > > > > > > > > > > /* leave the first one for overflow */ > > > > > txq->sw_ring_v =3D txq->sw_ring_v + 1; > > > > > txq->ops =3D txq_ops; > > > > > > > > > > return 0; > > > > > } > > > > > > > > > > So we need check the SIMD bitwidth firstly to avoid changing the = sw_ring* pointer address. > > > > > > > > > > > > > > > Also, looks like we need to add check on: > > > > > > > > > > int > > > > > ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) > > > > > { > > > > > struct ixgbe_tx_queue *txq =3D (struct ixgbe_tx_queue *)tx_queue= ; > > > > > if (txq->offloads =3D=3D 0 && > > > > > #ifdef RTE_LIBRTE_SECURITY > > > > > !(txq->using_ipsec) && > > > > > #endif > > > > > txq->tx_rs_thresh >=3D RTE_PMD_IXGBE_TX_MAX_BURST) { > > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > > > <-----------= -------- Add the same check > > > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > > > txq->sw_ring_v !=3D NULL)) { > > > > > return ixgbe_tx_done_cleanup_vec(txq, free_cnt); > > > > > > > > Could you probably explain a bit more why it is needed? > > > > > > To align with the vector selection path: > > > > > > if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && > > > (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || > > > ixgbe_txq_vec_setup(txq) =3D=3D 0)) > > > > > > Ok, so to make sure that TX is running in vector mode? >=20 > That's right, since no variable to save the vector mode selection, > then the check condition should be the same. What I am saying, that here instead of conditions we should check was vector mode already selected or not. Probably the easiest way to do it - check what tx function is setup.=20 >=20 > > If so, then doesn't txq->sw_ring_v !=3D NULL was intended to do so? > > BTW, is it a valid check? Considering that sw_ring and sw_ring_v > > is a union? >=20 > Yes, sw_ring_v should always be !NULL ;-) >=20 > > > > > > > > > > > > > > > > > } else { > > > > > return ixgbe_tx_done_cleanup_simple(txq, free_cnt); > > > > > } > > > > > > > > > > > > 2.17.1