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Wed, 2 Sep 2020 11:02:31 +0000 From: "Singh, Jasvinder" To: "Power, Ciara" , "dev@dpdk.org" CC: Olivier Matz Thread-Topic: [PATCH v2 17/17] net: add checks for max SIMD bitwidth Thread-Index: AQHWfI19hO0nlPFKt0SZ19Utf0F+wKlVM5bg Date: Wed, 2 Sep 2020 11:02:30 +0000 Message-ID: References: <20200807155859.63888-1-ciara.power@intel.com> <20200827161304.32300-1-ciara.power@intel.com> <20200827161304.32300-18-ciara.power@intel.com> In-Reply-To: <20200827161304.32300-18-ciara.power@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-reaction: no-action dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [109.76.57.40] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 62869a3a-b1b0-4469-46c5-08d84f2fb038 x-ms-traffictypediagnostic: BYAPR11MB2630: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3352.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 62869a3a-b1b0-4469-46c5-08d84f2fb038 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Sep 2020 11:02:31.0331 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fBQ0oc+ZBl1z9iSkm4pSUq3dAbaMJiqnzpwIospswnjNA/pnt8QgXWKjoUZDlMBvX2C55QR8XQwL0D0SbvngdUWOetQIt9nFKHaDz2Sptfg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2630 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 17/17] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: > -----Original Message----- > From: Power, Ciara > Sent: Thursday, August 27, 2020 5:13 PM > To: dev@dpdk.org > Cc: Power, Ciara ; Singh, Jasvinder > ; Olivier Matz > Subject: [PATCH v2 17/17] net: add checks for max SIMD bitwidth >=20 > When choosing a vector path to take, an extra condition must be satisfied= to > ensure the max SIMD bitwidth allows for the CPU enabled path. This check = is > done just before the handler is called, it cannot be done when setting th= e > handlers initially as the EAL max simd bitwidth value has not yet been se= t. >=20 > Cc: Jasvinder Singh >=20 > Signed-off-by: Ciara Power > --- > lib/librte_net/rte_net_crc.c | 8 ++++++++ > 1 file changed, 8 insertions(+) >=20 > diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c = index > 9fd4794a9d..d3d3206919 100644 > --- a/lib/librte_net/rte_net_crc.c > +++ b/lib/librte_net/rte_net_crc.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include >=20 > #if defined(RTE_ARCH_X86_64) && > defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ) > #define X86_64_SSE42_PCLMULQDQ 1 > @@ -60,6 +61,8 @@ static rte_net_crc_handler handlers_neon[] =3D { }; > #endif >=20 > +static uint16_t max_simd_bitwidth; > + > /** > * Reflect the bits about the middle > * > @@ -175,6 +178,11 @@ rte_net_crc_calc(const void *data, > uint32_t ret; > rte_net_crc_handler f_handle; >=20 > + if (max_simd_bitwidth =3D=3D 0) > + max_simd_bitwidth =3D rte_get_max_simd_bitwidth(); > + if (max_simd_bitwidth < RTE_MAX_128_SIMD && > + handlers !=3D handlers_scalar) > + rte_net_crc_set_alg(RTE_NET_CRC_SCALAR); Above change doesn't seem right as rte_net_crc_set_alg () is invoked everyt= ime when crc is computed. It potentially adds branches in runtime. In my o= pinion, bit width should be checked inside rte_net_crc_set_alg () function= which is supposed to be used during initialization stage after eal sets th= e max simd bit width.=20 > f_handle =3D handlers[type]; > ret =3D f_handle(data, data_len); >=20 > -- > 2.17.1