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From: "Singh, Jasvinder" <jasvinder.singh@intel.com>
To: "Power, Ciara" <ciara.power@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
CC: Olivier Matz <olivier.matz@6wind.com>
Thread-Topic: [PATCH v2 17/17] net: add checks for max SIMD bitwidth
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Subject: Re: [dpdk-dev] [PATCH v2 17/17] net: add checks for max SIMD
bitwidth
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Sender: "dev" <dev-bounces@dpdk.org>
> -----Original Message-----
> From: Power, Ciara <ciara.power@intel.com>
> Sent: Thursday, August 27, 2020 5:13 PM
> To: dev@dpdk.org
> Cc: Power, Ciara <ciara.power@intel.com>; Singh, Jasvinder
> <jasvinder.singh@intel.com>; Olivier Matz <olivier.matz@6wind.com>
> Subject: [PATCH v2 17/17] net: add checks for max SIMD bitwidth
>=20
> When choosing a vector path to take, an extra condition must be satisfied=
to
> ensure the max SIMD bitwidth allows for the CPU enabled path. This check =
is
> done just before the handler is called, it cannot be done when setting th=
e
> handlers initially as the EAL max simd bitwidth value has not yet been se=
t.
>=20
> Cc: Jasvinder Singh <jasvinder.singh@intel.com>
>=20
> Signed-off-by: Ciara Power <ciara.power@intel.com>
> ---
> lib/librte_net/rte_net_crc.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>=20
> diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c =
index
> 9fd4794a9d..d3d3206919 100644
> --- a/lib/librte_net/rte_net_crc.c
> +++ b/lib/librte_net/rte_net_crc.c
> @@ -9,6 +9,7 @@
> #include <rte_cpuflags.h>
> #include <rte_common.h>
> #include <rte_net_crc.h>
> +#include <rte_eal.h>
>=20
> #if defined(RTE_ARCH_X86_64) &&
> defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
> #define X86_64_SSE42_PCLMULQDQ 1
> @@ -60,6 +61,8 @@ static rte_net_crc_handler handlers_neon[] =3D { };
> #endif
>=20
> +static uint16_t max_simd_bitwidth;
> +
> /**
> * Reflect the bits about the middle
> *
> @@ -175,6 +178,11 @@ rte_net_crc_calc(const void *data,
> uint32_t ret;
> rte_net_crc_handler f_handle;
>=20
> + if (max_simd_bitwidth =3D=3D 0)
> + max_simd_bitwidth =3D rte_get_max_simd_bitwidth();
> + if (max_simd_bitwidth < RTE_MAX_128_SIMD &&
> + handlers !=3D handlers_scalar)
> + rte_net_crc_set_alg(RTE_NET_CRC_SCALAR);
Above change doesn't seem right as rte_net_crc_set_alg () is invoked everyt=
ime when crc is computed. It potentially adds branches in runtime. In my o=
pinion, bit width should be checked inside rte_net_crc_set_alg () function=
which is supposed to be used during initialization stage after eal sets th=
e max simd bit width.=20
> f_handle =3D handlers[type];
> ret =3D f_handle(data, data_len);
>=20
> --
> 2.17.1