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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: SMbb8l6uhWdDw/ZTJmcQ415UJiDNqvkTnjUn4l/YfevN0EPFPTDmQ+oFJtPm+XdqfJYjo8JNWCygJxSOdE2504IU9/WzQl1E2iRz6BidQljWTSHQpgdcHJBYx2qW7SIQrTh2wzr3UxWUJenJcLFay+ji2JVrGRl/a+4Tndjdg+e/MyOH7m8ceiUrHTWFdv/7wddhspcIEDKMSAsEq4p6CanpzaQ93GBpOMQcqM3apVgdu8U8pRoBiUktsWmjjtXvLeHt2C4YEEzWS2HmIoOORb5vVH/nSG7Dw78LPU9etg0sTJFmJSzOmo44aCF66o3d+xbkqLnFti39AjITLq7nb0cPy/JKdC7MohO1TAmIWztgQDaaY3F7z9He5Rzf+o2TUEeC3pA3luuFM+bATsVN8EeRM3ciBEYsVGhhsc4c6BhimgLVPY+rp6CzU7J1v/Ygh+ejAkvIlvcnickf6EvX8CsQk40FIZkggZ7Sxa2eIaft1Cpmw+wlEGFA2T7WnCWKOhXtkmRP2ve2TQyvan+3ul76ZXTa2uCCqCLBKcaOHcZR6AfC1EgwiNdTcPRlAQtGazjX6msGUyphhI73fLxvAwX9x6JXeLoj2n+ABD/2yEZRrcQd55P3eW7bRNXXRfT4W/HhjSBxpYbOMbHXrAmKRQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR11MB3494.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc689fe8-18ed-44e0-cd85-08d86a5b2b01 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Oct 2020 00:51:46.7172 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: b5n41sW/yLvtbgZ7YToJwIB0ko00cfl2JlEOfEJICST4EJBmMKf8Rsc3rYiD4gSxFtCIgkBQ6gluNa5EFKq85Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR11MB2984 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 15/18] member: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: > -----Original Message----- > From: Power, Ciara > Sent: Wednesday, September 30, 2020 6:04 AM > To: dev@dpdk.org > Cc: Power, Ciara ; Wang, Yipeng1 > ; Gobriel, Sameh > Subject: [PATCH v3 15/18] member: add checks for max SIMD bitwidth >=20 > When choosing a vector path to take, an extra condition must be satisfied= to > ensure the max SIMD bitwidth allows for the CPU enabled path. >=20 > Cc: Yipeng Wang > Cc: Sameh Gobriel >=20 > Signed-off-by: Ciara Power > --- > lib/librte_member/rte_member_ht.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/lib/librte_member/rte_member_ht.c > b/lib/librte_member/rte_member_ht.c > index cbcd0d4407..71e3cf7b52 100644 > --- a/lib/librte_member/rte_member_ht.c > +++ b/lib/librte_member/rte_member_ht.c > @@ -113,7 +113,8 @@ rte_member_create_ht(struct rte_member_setsum > *ss, > } > #if defined(RTE_ARCH_X86) > if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && > - RTE_MEMBER_BUCKET_ENTRIES =3D=3D 16) > + RTE_MEMBER_BUCKET_ENTRIES =3D=3D 16 && > + rte_get_max_simd_bitwidth() >=3D > RTE_MAX_256_SIMD) > ss->sig_cmp_fn =3D RTE_MEMBER_COMPARE_AVX2; > else > #endif > -- > 2.17.1 [Wang, Yipeng]=20 Acked-by: Yipeng Wang