* [dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads disablement
2021-04-21 16:34 [dpdk-dev] [PATCH 0/3] mlx5 - support checksum offloads on Windows Tal Shnaiderman
@ 2021-04-21 16:34 ` Tal Shnaiderman
2021-04-22 10:17 ` Odi Assli
2021-04-21 16:34 ` [dpdk-dev] [PATCH 2/3] common/mlx5: read checksum capability from DevX Tal Shnaiderman
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Tal Shnaiderman @ 2021-04-21 16:34 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, odia, stable
mlx5 offloads which are unsupported on Windows
are currently disabled by checks with IBV/DV flags
which are irrelevant to Windows.
The checks are removed until they are fully available.
Fixes: 93f4ece91a1f ("net/mlx5: spawn ethdev ports on Windows")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/windows/mlx5_os.c | 15 +--------------
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 814063b5ce..5e53042b85 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -359,11 +359,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->swp = 0;
config->ind_table_max_size =
sh->device_attr.max_rwq_indirection_table_size;
- if (RTE_CACHE_LINE_SIZE == 128 &&
- !(device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
- cqe_comp = 0;
- else
- cqe_comp = 1;
+ cqe_comp = 0;
config->cqe_comp = cqe_comp;
DRV_LOG(DEBUG, "tunnel offloading is not supported");
config->tunnel_en = 0;
@@ -424,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
err = mlx5_dev_check_sibling_config(priv, config);
if (err)
goto error;
- config->hw_csum = !!(sh->device_attr.device_cap_flags_ex &
- IBV_DEVICE_RAW_IP_CSUM);
DRV_LOG(DEBUG, "checksum offloading is %ssupported",
(config->hw_csum ? "" : "not "));
DRV_LOG(DEBUG, "counters are not supported");
@@ -439,19 +433,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
config->ind_table_max_size);
- config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
- IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
(config->hw_vlan_strip ? "" : "not "));
- config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
- IBV_RAW_PACKET_CAP_SCATTER_FCS);
if (config->hw_padding) {
DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
config->hw_padding = 0;
}
- config->tso = (sh->device_attr.max_tso > 0 &&
- (sh->device_attr.tso_supported_qpts &
- (1 << IBV_QPT_RAW_PACKET)));
if (config->tso)
config->tso_max_payload_sz = sh->device_attr.max_tso;
DRV_LOG(DEBUG, "%sMPS is %s.",
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads disablement
2021-04-21 16:34 ` [dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads disablement Tal Shnaiderman
@ 2021-04-22 10:17 ` Odi Assli
0 siblings, 0 replies; 8+ messages in thread
From: Odi Assli @ 2021-04-22 10:17 UTC (permalink / raw)
To: Tal Shnaiderman, dev
Cc: NBU-Contact-Thomas Monjalon, Matan Azrad, Raslan Darawsheh,
Asaf Penso, stable
> Subject: [PATCH 1/3] net/mlx5: fix unsupported offloads disablement
>
> mlx5 offloads which are unsupported on Windows are currently disabled by
> checks with IBV/DV flags which are irrelevant to Windows.
>
> The checks are removed until they are fully available.
>
> Fixes: 93f4ece91a1f ("net/mlx5: spawn ethdev ports on Windows")
> Cc: stable@dpdk.org
>
> Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
> drivers/net/mlx5/windows/mlx5_os.c | 15 +--------------
> 1 file changed, 1 insertion(+), 14 deletions(-)
>
> diff --git a/drivers/net/mlx5/windows/mlx5_os.c
> b/drivers/net/mlx5/windows/mlx5_os.c
> index 814063b5ce..5e53042b85 100644
> --- a/drivers/net/mlx5/windows/mlx5_os.c
> +++ b/drivers/net/mlx5/windows/mlx5_os.c
> @@ -359,11 +359,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> config->swp = 0;
> config->ind_table_max_size =
> sh->device_attr.max_rwq_indirection_table_size;
> - if (RTE_CACHE_LINE_SIZE == 128 &&
> - !(device_attr.flags &
> MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
> - cqe_comp = 0;
> - else
> - cqe_comp = 1;
> + cqe_comp = 0;
> config->cqe_comp = cqe_comp;
> DRV_LOG(DEBUG, "tunnel offloading is not supported");
> config->tunnel_en = 0;
> @@ -424,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> err = mlx5_dev_check_sibling_config(priv, config);
> if (err)
> goto error;
> - config->hw_csum = !!(sh->device_attr.device_cap_flags_ex &
> - IBV_DEVICE_RAW_IP_CSUM);
> DRV_LOG(DEBUG, "checksum offloading is %ssupported",
> (config->hw_csum ? "" : "not "));
> DRV_LOG(DEBUG, "counters are not supported"); @@ -439,19
> +433,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
> DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
> config->ind_table_max_size);
> - config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
> -
> IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
> DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
> (config->hw_vlan_strip ? "" : "not "));
> - config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
> - IBV_RAW_PACKET_CAP_SCATTER_FCS);
> if (config->hw_padding) {
> DRV_LOG(DEBUG, "Rx end alignment padding isn't
> supported");
> config->hw_padding = 0;
> }
> - config->tso = (sh->device_attr.max_tso > 0 &&
> - (sh->device_attr.tso_supported_qpts &
> - (1 << IBV_QPT_RAW_PACKET)));
> if (config->tso)
> config->tso_max_payload_sz = sh->device_attr.max_tso;
> DRV_LOG(DEBUG, "%sMPS is %s.",
> --
> 2.16.1.windows.4
Tested-by: Odi Assli <odia@nvidia.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dpdk-dev] [PATCH 2/3] common/mlx5: read checksum capability from DevX
2021-04-21 16:34 [dpdk-dev] [PATCH 0/3] mlx5 - support checksum offloads on Windows Tal Shnaiderman
2021-04-21 16:34 ` [dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads disablement Tal Shnaiderman
@ 2021-04-21 16:34 ` Tal Shnaiderman
2021-04-22 10:17 ` Odi Assli
2021-04-21 16:34 ` [dpdk-dev] [PATCH 3/3] net/mlx5: support checksum offload on Windows Tal Shnaiderman
2021-04-28 12:06 ` [dpdk-dev] [PATCH 0/3] mlx5 - support checksum offloads " Raslan Darawsheh
3 siblings, 1 reply; 8+ messages in thread
From: Tal Shnaiderman @ 2021-04-21 16:34 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, odia
mlx5 in Windows needs the hca capability csum_cap
to query the NIC for checksum offloading support
Added the capability as part of the capabilities
queried by the PMD using DevX.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 268bcd0d99..d2e4ab33a2 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -837,6 +837,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, wqe_vlan_insert);
+ attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, csum_cap);
attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
lro_cap);
attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 67b5f771c6..1fb9130e51 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -92,6 +92,7 @@ struct mlx5_hca_attr {
uint32_t eth_net_offloads:1;
uint32_t eth_virt:1;
uint32_t wqe_vlan_insert:1;
+ uint32_t csum_cap:1;
uint32_t wqe_inline_mode:2;
uint32_t vport_inline_mode:3;
uint32_t tunnel_stateless_geneve_rx:1;
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [dpdk-dev] [PATCH 2/3] common/mlx5: read checksum capability from DevX
2021-04-21 16:34 ` [dpdk-dev] [PATCH 2/3] common/mlx5: read checksum capability from DevX Tal Shnaiderman
@ 2021-04-22 10:17 ` Odi Assli
0 siblings, 0 replies; 8+ messages in thread
From: Odi Assli @ 2021-04-22 10:17 UTC (permalink / raw)
To: Tal Shnaiderman, dev
Cc: NBU-Contact-Thomas Monjalon, Matan Azrad, Raslan Darawsheh, Asaf Penso
> Subject: [PATCH 2/3] common/mlx5: read checksum capability from DevX
>
> mlx5 in Windows needs the hca capability csum_cap to query the NIC for
> checksum offloading support
>
> Added the capability as part of the capabilities queried by the PMD using
> DevX.
>
> Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
> drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
> drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index 268bcd0d99..d2e4ab33a2 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -837,6 +837,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
> hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
> attr->wqe_vlan_insert =
> MLX5_GET(per_protocol_networking_offload_caps,
> hcattr, wqe_vlan_insert);
> + attr->csum_cap =
> MLX5_GET(per_protocol_networking_offload_caps,
> + hcattr, csum_cap);
> attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps,
> hcattr,
> lro_cap);
> attr->tunnel_lro_gre =
> MLX5_GET(per_protocol_networking_offload_caps,
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
> b/drivers/common/mlx5/mlx5_devx_cmds.h
> index 67b5f771c6..1fb9130e51 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> @@ -92,6 +92,7 @@ struct mlx5_hca_attr {
> uint32_t eth_net_offloads:1;
> uint32_t eth_virt:1;
> uint32_t wqe_vlan_insert:1;
> + uint32_t csum_cap:1;
> uint32_t wqe_inline_mode:2;
> uint32_t vport_inline_mode:3;
> uint32_t tunnel_stateless_geneve_rx:1;
> --
> 2.16.1.windows.4
Tested-by: Odi Assli <odia@nvidia.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dpdk-dev] [PATCH 3/3] net/mlx5: support checksum offload on Windows
2021-04-21 16:34 [dpdk-dev] [PATCH 0/3] mlx5 - support checksum offloads on Windows Tal Shnaiderman
2021-04-21 16:34 ` [dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads disablement Tal Shnaiderman
2021-04-21 16:34 ` [dpdk-dev] [PATCH 2/3] common/mlx5: read checksum capability from DevX Tal Shnaiderman
@ 2021-04-21 16:34 ` Tal Shnaiderman
2021-04-22 10:17 ` Odi Assli
2021-04-28 12:06 ` [dpdk-dev] [PATCH 0/3] mlx5 - support checksum offloads " Raslan Darawsheh
3 siblings, 1 reply; 8+ messages in thread
From: Tal Shnaiderman @ 2021-04-21 16:34 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, odia
Support of the checksum offloading by checking
the relevant FW capability (csum_cap) for NIC support.
RX supported offloads:
DEV_RX_OFFLOAD_IPV4_CKSUM
DEV_RX_OFFLOAD_UDP_CKSUM
DEV_RX_OFFLOAD_TCP_CKSUM
TX supported offloads:
DEV_TX_OFFLOAD_IPV4_CKSUM
DEV_TX_OFFLOAD_UDP_CKSUM
DEV_TX_OFFLOAD_TCP_CKSUM
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/windows/mlx5_os.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 5e53042b85..3fe3f55f49 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -420,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
err = mlx5_dev_check_sibling_config(priv, config);
if (err)
goto error;
- DRV_LOG(DEBUG, "checksum offloading is %ssupported",
- (config->hw_csum ? "" : "not "));
DRV_LOG(DEBUG, "counters are not supported");
config->ind_table_max_size =
sh->device_attr.max_rwq_indirection_table_size;
@@ -464,6 +462,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
sh->cmng.relaxed_ordering_read =
config->hca_attr.relaxed_ordering_read;
}
+ config->hw_csum = config->hca_attr.csum_cap;
+ DRV_LOG(DEBUG, "checksum offloading is %ssupported",
+ (config->hw_csum ? "" : "not "));
}
if (config->devx) {
uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [dpdk-dev] [PATCH 3/3] net/mlx5: support checksum offload on Windows
2021-04-21 16:34 ` [dpdk-dev] [PATCH 3/3] net/mlx5: support checksum offload on Windows Tal Shnaiderman
@ 2021-04-22 10:17 ` Odi Assli
0 siblings, 0 replies; 8+ messages in thread
From: Odi Assli @ 2021-04-22 10:17 UTC (permalink / raw)
To: Tal Shnaiderman, dev
Cc: NBU-Contact-Thomas Monjalon, Matan Azrad, Raslan Darawsheh, Asaf Penso
> Subject: [PATCH 3/3] net/mlx5: support checksum offload on Windows
>
> Support of the checksum offloading by checking the relevant FW capability
> (csum_cap) for NIC support.
>
> RX supported offloads:
>
> DEV_RX_OFFLOAD_IPV4_CKSUM
> DEV_RX_OFFLOAD_UDP_CKSUM
> DEV_RX_OFFLOAD_TCP_CKSUM
>
> TX supported offloads:
>
> DEV_TX_OFFLOAD_IPV4_CKSUM
> DEV_TX_OFFLOAD_UDP_CKSUM
> DEV_TX_OFFLOAD_TCP_CKSUM
>
> Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
> drivers/net/mlx5/windows/mlx5_os.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/mlx5/windows/mlx5_os.c
> b/drivers/net/mlx5/windows/mlx5_os.c
> index 5e53042b85..3fe3f55f49 100644
> --- a/drivers/net/mlx5/windows/mlx5_os.c
> +++ b/drivers/net/mlx5/windows/mlx5_os.c
> @@ -420,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> err = mlx5_dev_check_sibling_config(priv, config);
> if (err)
> goto error;
> - DRV_LOG(DEBUG, "checksum offloading is %ssupported",
> - (config->hw_csum ? "" : "not "));
> DRV_LOG(DEBUG, "counters are not supported");
> config->ind_table_max_size =
> sh->device_attr.max_rwq_indirection_table_size;
> @@ -464,6 +462,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
> sh->cmng.relaxed_ordering_read =
> config->hca_attr.relaxed_ordering_read;
> }
> + config->hw_csum = config->hca_attr.csum_cap;
> + DRV_LOG(DEBUG, "checksum offloading is %ssupported",
> + (config->hw_csum ? "" : "not "));
> }
> if (config->devx) {
> uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
> --
> 2.16.1.windows.4
Tested-by: Odi Assli <odia@nvidia.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [dpdk-dev] [PATCH 0/3] mlx5 - support checksum offloads on Windows
2021-04-21 16:34 [dpdk-dev] [PATCH 0/3] mlx5 - support checksum offloads on Windows Tal Shnaiderman
` (2 preceding siblings ...)
2021-04-21 16:34 ` [dpdk-dev] [PATCH 3/3] net/mlx5: support checksum offload on Windows Tal Shnaiderman
@ 2021-04-28 12:06 ` Raslan Darawsheh
3 siblings, 0 replies; 8+ messages in thread
From: Raslan Darawsheh @ 2021-04-28 12:06 UTC (permalink / raw)
To: Tal Shnaiderman, dev
Cc: NBU-Contact-Thomas Monjalon, Matan Azrad, Asaf Penso, Odi Assli
Hi,
> -----Original Message-----
> From: Tal Shnaiderman <talshn@nvidia.com>
> Sent: Wednesday, April 21, 2021 7:35 PM
> To: dev@dpdk.org
> Cc: NBU-Contact-Thomas Monjalon <thomas@monjalon.net>; Matan Azrad
> <matan@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>; Asaf Penso
> <asafp@nvidia.com>; Odi Assli <odia@nvidia.com>
> Subject: [PATCH 0/3] mlx5 - support checksum offloads on Windows
>
> Support the following checksum offloads on Windows.
>
> RX supported offloads:
>
> DEV_RX_OFFLOAD_IPV4_CKSUM
> DEV_RX_OFFLOAD_UDP_CKSUM
> DEV_RX_OFFLOAD_TCP_CKSUM
>
> TX supported offloads:
>
> DEV_TX_OFFLOAD_IPV4_CKSUM
> DEV_TX_OFFLOAD_UDP_CKSUM
> DEV_TX_OFFLOAD_TCP_CKSUM
>
> Tal Shnaiderman (3):
> net/mlx5: fix unsupported offloads disablement
> common/mlx5: read checksum capability from DevX
> net/mlx5: support checksum offload on Windows
>
> drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
> drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
> drivers/net/mlx5/windows/mlx5_os.c | 20 ++++----------------
> 3 files changed, 7 insertions(+), 16 deletions(-)
>
> --
> 2.16.1.windows.4
Series applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
^ permalink raw reply [flat|nested] 8+ messages in thread