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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 30c99928-7d48-460a-d3f1-08d6f9349015 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Jun 2019 06:15:46.8300 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2982 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-25_04:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Monday, June 24, 2019 11:11 PM > To: thomas@monjalon.net; Phil Yang (Arm Technology China) > > Cc: Jerin Jacob Kollanukkaran ; dev@dpdk.org; > hemant.agrawal@nxp.com; Gavin Hu (Arm Technology China) > ; Honnappa Nagarahalli > ; nd ; gage.eads@intel.com; > nd > Subject: [EXT] RE: [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare > exchange > > > > 24/06/2019 18:12, Honnappa Nagarahalli: > > > > > > + } else { > > > > > > + rte_panic("Invalid memory order\n"); > > > > > > > > > > > > > > > rte_panic should be removed from library. In this case, I think, > > > > > invalid mo can go for strongest barrier. > > > > > > It is added here to capture programming errors. > > > Memory order can be passed during compilation or during run time. > > > 'rte_panic' supports both of these. > > > Adding code with strongest memory order will mask the programming err= or. > > > > An error must return a specific code from the function. > > rte_panic is really forbidden in libraries. > > We are in the process of removing all of them. > Thank you for clarifying. > In this particular use case, the API is similar to '__atomic_compare_exch= ange' > built-in. Users would expect similar behavior. If we are differing from t= he > standard behavior, we should document it in the API definition. IMO, We should not differ from the standard behavior(return type) of atomic= _compare_exchange. And we should not have rte_panic in library. IMO, Best option would be 1) If mo is compile time constant then check with RTE_BUILD_ON for static a= ssert to find invalid mo 2) if mo is runtime value and it is invalid then move to strongest memory o= rder to make functionally correct >=20 > > > >