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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 08080f4d-29bc-4626-8a0b-08d6f86ef08d X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jun 2019 06:41:08.3803 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2728 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-24_05:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Phil Yang > Sent: Sunday, June 23, 2019 8:46 AM > To: dev@dpdk.org > Cc: thomas@monjalon.net; Jerin Jacob Kollanukkaran ; > hemant.agrawal@nxp.com; Honnappa.Nagarahalli@arm.com; > gavin.hu@arm.com; nd@arm.com; gage.eads@intel.com > Subject: [EXT] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare > exchange >=20 > Add 128-bit atomic compare exchange on aarch64. >=20 > Signed-off-by: Phil Yang > Reviewed-by: Honnappa Nagarahalli > Tested-by: Honnappa Nagarahalli > --- > This patch depends on 'eal/stack: fix 'pointer-sign' warning' > http://patchwork.dpdk.org/patch/54840/ >=20 > + > +#ifdef __ARM_FEATURE_ATOMICS > +static inline rte_int128_t > +__rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated, > +int mo) { Better to change to "const int mo". > + > + /* caspX instructions register pair must start from even-numbered > + * register at operand 1. > + * So, specify registers for local variables here. > + */ > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; > + register uint64_t x1 __asm("x1") =3D (uint64_t)old.val[1]; > + register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; > + register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; > + > + if (mo =3D=3D __ATOMIC_RELAXED) { > + asm volatile( > + "casp %[old0], %[old1], %[upd0], %[upd1], > [%[dst]]" > + : [old0] "+r" (x0), > + [old1] "+r" (x1) > + : [upd0] "r" (x2), > + [upd1] "r" (x3), > + [dst] "r" (dst) > + : "memory"); > + } else if (mo =3D=3D __ATOMIC_ACQUIRE) { > + asm volatile( > + "caspa %[old0], %[old1], %[upd0], %[upd1], > [%[dst]]" > + : [old0] "+r" (x0), > + [old1] "+r" (x1) > + : [upd0] "r" (x2), > + [upd1] "r" (x3), > + [dst] "r" (dst) > + : "memory"); > + } else if (mo =3D=3D __ATOMIC_ACQ_REL) { > + asm volatile( > + "caspal %[old0], %[old1], %[upd0], %[upd1], > [%[dst]]" > + : [old0] "+r" (x0), > + [old1] "+r" (x1) > + : [upd0] "r" (x2), > + [upd1] "r" (x3), > + [dst] "r" (dst) > + : "memory"); > + } else if (mo =3D=3D __ATOMIC_RELEASE) { > + asm volatile( > + "caspl %[old0], %[old1], %[upd0], %[upd1], > [%[dst]]" > + : [old0] "+r" (x0), > + [old1] "+r" (x1) > + : [upd0] "r" (x2), > + [upd1] "r" (x3), > + [dst] "r" (dst) > + : "memory"); I think, This duplication code can be avoid with macro and casp/capsa/casal= /caspl as argument. > + } else { > + rte_panic("Invalid memory order\n"); rte_panic should be removed from library. In this case, I think, invalid mo= can go for strongest barrier. > + } > + > + old.val[0] =3D x0; > + old.val[1] =3D x1; > + > + return old; > +} > +#else > +static inline rte_int128_t > +__rte_ldx128(const rte_int128_t *src, int mo) { > + rte_int128_t ret; > + if (mo =3D=3D __ATOMIC_ACQUIRE) > + asm volatile( > + "ldaxp %0, %1, %2" > + : "=3D&r" (ret.val[0]), > + "=3D&r" (ret.val[1]) > + : "Q" (src->val[0]) > + : "memory"); > + else if (mo =3D=3D __ATOMIC_RELAXED) > + asm volatile( > + "ldxp %0, %1, %2" > + : "=3D&r" (ret.val[0]), > + "=3D&r" (ret.val[1]) > + : "Q" (src->val[0]) > + : "memory"); Same as above comment. > + else > + rte_panic("Invalid memory order\n"); Same as above comment. > + > + return ret; > +} > + > +static inline uint32_t > +__rte_stx128(rte_int128_t *dst, const rte_int128_t src, int mo) { > + uint32_t ret; > + if (mo =3D=3D __ATOMIC_RELEASE) > + asm volatile( > + "stlxp %w0, %1, %2, %3" > + : "=3D&r" (ret) > + : "r" (src.val[0]), > + "r" (src.val[1]), > + "Q" (dst->val[0]) > + : "memory"); > + else if (mo =3D=3D __ATOMIC_RELAXED) > + asm volatile( > + "stxp %w0, %1, %2, %3" > + : "=3D&r" (ret) > + : "r" (src.val[0]), > + "r" (src.val[1]), > + "Q" (dst->val[0]) > + : "memory"); > + else > + rte_panic("Invalid memory order\n"); Same as above comment. > + > + /* Return 0 on success, 1 on failure */ > + return ret; > +} > +#endif > + > +static inline int __rte_experimental > +rte_atomic128_cmp_exchange(rte_int128_t *dst, > + rte_int128_t *exp, > + const rte_int128_t *src, > + unsigned int weak, > + int success, > + int failure) > +{ > + // Always do strong CAS Remove C++ style code comment.