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Fri, 2 Aug 2019 03:58:05 +0000 Received: from BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862]) by BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862%4]) with mapi id 15.20.2115.005; Fri, 2 Aug 2019 03:58:05 +0000 From: Jerin Jacob Kollanukkaran To: Rosen Xu , "dev@dpdk.org" CC: "ferruh.yigit@intel.com" , "tianfei.zhang@intel.com" , "andy.pei@intel.com" , "david.lomartire@intel.com" , "qi.z.zhang@intel.com" , "xiaolong.ye@intel.com" Thread-Topic: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add irq support Thread-Index: AQHVSNAwWxMTLMsD0U6aTXPsnsjO+KbnOvfw Date: Fri, 2 Aug 2019 03:58:05 +0000 Message-ID: References: <1564556752-19257-2-git-send-email-rosen.xu@intel.com> <1564708727-164887-1-git-send-email-rosen.xu@intel.com> <1564708727-164887-3-git-send-email-rosen.xu@intel.com> In-Reply-To: <1564708727-164887-3-git-send-email-rosen.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [14.140.231.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2dad3858-fad4-48c1-b21f-08d716fd9f7f x-microsoft-antispam: BCL:0; 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SCL:1; SRVR:BYAPR18MB2821; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: VhlxUdaD+072cf5w0K/SoKgzsHY8sUgI/SuHyooL5BKPm70i+JcgTvZfn8yhB2E1+b2DtRwDL3fbO8j9PGCY9kg6OEpfT1yo6yyA9w4LLqV2muvTmuICIzB1Zhbq9yWXDUIdTBN6vBK8em7Vb/s0CBpZ/U0Agud/J44AKl7fQTB2O49NrHbxO01arei7Bzz5kpZmz73MOjC365rqRwPYX+gNpqZ1jNjA3vt0ntFQGFHUs3SE5apOw90exK2JacJhiC/R5tdIqGwo0i0l8MigNjTIvoW5gnCyyVQM1xDY/qhzynJDFkyqwzUPJTJIboTFKRRaml0qD3LqIcxu8iw+41OFWukOWAd3HlzrjM8zxpkAbyvzUc048XskKdEpwZINu/Smm6UpvXIse+OKv2WNsm02w1WkUuK4pqfD9xYjoMI= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 2dad3858-fad4-48c1-b21f-08d716fd9f7f X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Aug 2019 03:58:05.2648 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2821 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-02_02:2019-07-31,2019-08-02 signatures=0 Subject: Re: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add irq support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Rosen Xu > Sent: Friday, August 2, 2019 6:49 AM > To: dev@dpdk.org > Cc: ferruh.yigit@intel.com; tianfei.zhang@intel.com; rosen.xu@intel.com; > andy.pei@intel.com; david.lomartire@intel.com; qi.z.zhang@intel.com; > xiaolong.ye@intel.com > Subject: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add irq > support >=20 > From: Tianfei zhang >=20 > Add irq support for ifpga FME globle error, port error and uint unit. > We implmented this feature by vfio interrupt mechanism. >=20 > Signed-off-by: Tianfei zhang > --- > drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c | 61 > +++++++++++++++++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_fme_error.c | 22 ++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_port.c | 20 ++++++++ > drivers/raw/ifpga_rawdev/base/ifpga_port_error.c | 21 ++++++++ > 4 files changed, 124 insertions(+) >=20 > diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c > b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c > index 63c8bcc..6b942e6 100644 > --- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c > +++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c > @@ -3,6 +3,7 @@ > */ >=20 > #include > +#include >=20 > #include "ifpga_feature_dev.h" >=20 > @@ -331,3 +332,63 @@ int port_hw_init(struct ifpga_port_hw *port) > port_hw_uinit(port); > return ret; > } > + > +/* > + * FIXME: we should get msix vec count during pci enumeration instead > +of > + * below hardcode value. > + */ > +#define FPGA_MSIX_VEC_COUNT 20 > +/* irq set buffer length for interrupt */ #define MSIX_IRQ_SET_BUF_LEN > +(sizeof(struct vfio_irq_set) + \ > + sizeof(int) * FPGA_MSIX_VEC_COUNT) > + > +/* only support msix for now*/ > +static int vfio_msix_enable_block(s32 vfio_dev_fd, unsigned int vec_star= t, > + unsigned int count, s32 *fds) Isn't better to use generic EAL function for the same? > +{ > + char irq_set_buf[MSIX_IRQ_SET_BUF_LEN]; > + struct vfio_irq_set *irq_set; > + int len, ret; > + int *fd_ptr; > + > + len =3D sizeof(irq_set_buf); > + > + irq_set =3D (struct vfio_irq_set *)irq_set_buf; > + irq_set->argsz =3D len; > + irq_set->count =3D count; > + irq_set->flags =3D VFIO_IRQ_SET_DATA_EVENTFD | > + VFIO_IRQ_SET_ACTION_TRIGGER; > + irq_set->index =3D VFIO_PCI_MSIX_IRQ_INDEX; > + irq_set->start =3D vec_start; > + > + fd_ptr =3D (int *)&irq_set->data; > + memcpy(fd_ptr, fds, sizeof(int) * count); > + > + ret =3D ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set); > + if (ret) > + printf("Error enabling MSI-X interrupts\n"); > + > + return ret; > +} > +