From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 88DCBA0471 for ; Mon, 17 Jun 2019 10:24:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5A2D61BE17; Mon, 17 Jun 2019 10:24:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 020361BB43 for ; Mon, 17 Jun 2019 10:24:46 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5H8ObZO032145 for ; Mon, 17 Jun 2019 01:24:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=6/kr3dg1PTIDy8Y63vcRwAzxk+tsmbFf4UM2gRUN0tQ=; b=SYJAmc8QPcewOHafnn+YhYB1LajhPLeQp1jytzaKj2/pjLR0eD2Ay7rX/+/l4s7JKdy4 bmnWuqVlTgvzwVVS8zLqi80ebirtnPbyJ145Nyf2SYoZe0Xy9zoSqwZ7W1LgZFU7Tdwc 3/PY0ldjqQacUSfAudghv9jyrW2vprL4kQF+bVDu5lONd7fZLnxrIoAPIHbkJayEXrnt WspWGk4HhhUPzEumjegcIIJZRcVekysCHSV7Szbi/yLpM54fomrZYuQb4dUU73i6xbLy 5E/Q86/emyH9+CqdDBv9iANFk8LIgDHJxN0DZyojSAssUni4tsyRnh48Tn4OQ5b7zRna ew== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2t506hwv42-9 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 17 Jun 2019 01:24:45 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Mon, 17 Jun 2019 01:24:07 -0700 Received: from NAM04-CO1-obe.outbound.protection.outlook.com (104.47.45.51) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Mon, 17 Jun 2019 01:24:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6/kr3dg1PTIDy8Y63vcRwAzxk+tsmbFf4UM2gRUN0tQ=; b=EfFD2TXe6vCbQXcElRDrJ8RtAq030aYcX6yD9CgzJF5baRtohqeBwC0SB0Z+VOria4ahPA5yoUFfNg73g46Pvc0z3Dvim8jSkPo3JlqMT8eyq5m2qibIL4C5OwRrMMoWEelE1H9wTjJrXS8iQcFgPAAlSzW3jDfT/m0bzeIKBsI= Received: from BYAPR18MB2424.namprd18.prod.outlook.com (20.179.91.149) by BYAPR18MB2646.namprd18.prod.outlook.com (20.179.92.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.11; Mon, 17 Jun 2019 08:24:05 +0000 Received: from BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::75fd:a528:a1bf:bef4]) by BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::75fd:a528:a1bf:bef4%3]) with mapi id 15.20.1987.014; Mon, 17 Jun 2019 08:24:05 +0000 From: Jerin Jacob Kollanukkaran To: Pavan Nikhilesh Bhagavatula , "Pavan Nikhilesh Bhagavatula" CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify chunk slots Thread-Index: AQHVGKu18UxqNg9MtkCwYtKXHgEm96afmodw Date: Mon, 17 Jun 2019 08:24:05 +0000 Message-ID: References: <20190601185355.370-1-pbhagavatula@marvell.com> <20190601185355.370-33-pbhagavatula@marvell.com> In-Reply-To: <20190601185355.370-33-pbhagavatula@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [14.140.231.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ee489b63-fe1b-4d57-b004-08d6f2fd298c x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:BYAPR18MB2646; x-ms-traffictypediagnostic: BYAPR18MB2646: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1002; x-forefront-prvs: 0071BFA85B x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(376002)(366004)(346002)(396003)(39850400004)(136003)(189003)(199004)(13464003)(6506007)(9686003)(256004)(14444005)(2906002)(86362001)(5660300002)(6116002)(3846002)(26005)(110136005)(76176011)(68736007)(71190400001)(7696005)(316002)(53546011)(478600001)(55236004)(99286004)(186003)(52536014)(102836004)(476003)(6246003)(305945005)(7736002)(6436002)(446003)(8936002)(486006)(66446008)(229853002)(71200400001)(4326008)(73956011)(11346002)(14454004)(66946007)(74316002)(25786009)(6636002)(66066001)(81166006)(8676002)(53936002)(33656002)(81156014)(66556008)(66476007)(76116006)(55016002)(64756008); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2646; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: dJIy6GeghNHzieTL8Q7uD7QDswqEHc3AX6Q3K84+Kg8bWEtW9+jqwLQSQ7XIP/1RipSJUh9CJYu/eN+vAPqwpSCZOLPiiM3OMYMVwJwOfpdv+EGcaPPCFWGaNGk2/sr1dmTCsLxuiPDrlLepBdXCg0CZ5eG0YKtPkNeiWS3ZO0xZ4Nzx+v5D6ojZArYaXZ3ewKrf+qQcCPpZR8WgCqdBvsXavLXjTsn/4nC8bKb+CK5EFPTqnvwYg+8mm9fdzQUQbGPxHH0tfd4gtU+Gd5TJLWwxe4MXqnuLHNunKCelUzFbQNDy7y/HL7wn2keDX0mIzGtfi1gUVziXNTwazkpXOuIQL9Aa37aw7aQKgFy/A9HP5ih5oPkmVq5vAVqfNV5YniUyVwgvFM8PzhkBzqv9Zi1Onu3++cvFavfyEO/RX0U= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ee489b63-fe1b-4d57-b004-08d6f2fd298c X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jun 2019 08:24:05.5888 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2646 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-17_05:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify chunk slots X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: pbhagavatula@marvell.com > Sent: Sunday, June 2, 2019 12:24 AM > To: Jerin Jacob Kollanukkaran ; Pavan Nikhilesh > Bhagavatula > Cc: dev@dpdk.org > Subject: [dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify > chunk slots >=20 > From: Pavan Nikhilesh >=20 > Add devargs support to modify number of chunk slots. Chunks are used to s= tore > event timers, a chunk can be visualised as an array where the last elemen= t points > to the next chunk and rest of them are used to store events. TIM traverse= s the > list of chunks and enqueues the event timers to SSO. > If no argument is passed then a default value of 255 is taken. > Example: >=20 > --dev "0002:0e:00.0,tim_chnk_slots=3D511" >=20 > Signed-off-by: Pavan Nikhilesh > --- > drivers/event/octeontx2/otx2_tim_evdev.c | 11 ++++++++++- > drivers/event/octeontx2/otx2_tim_evdev.h | 2 ++ > 2 files changed, 12 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c > b/drivers/event/octeontx2/otx2_tim_evdev.c > index 9cceafd77..bba6cc609 100644 > --- a/drivers/event/octeontx2/otx2_tim_evdev.c > +++ b/drivers/event/octeontx2/otx2_tim_evdev.c > @@ -240,7 +240,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter > *adptr) > tim_ring->tck_nsec =3D RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10); > tim_ring->max_tout =3D rcfg->max_tmo_ns; > tim_ring->nb_bkts =3D (tim_ring->max_tout / tim_ring->tck_nsec); > - tim_ring->chunk_sz =3D OTX2_TIM_RING_DEF_CHNK_SZ; > + tim_ring->chunk_sz =3D dev->chunk_sz; > nb_timers =3D rcfg->nb_timers; > tim_ring->disable_npa =3D dev->disable_npa; >=20 > @@ -355,6 +355,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, > uint64_t flags, } >=20 > #define OTX2_TIM_DISABLE_NPA "tim_disable_npa" > +#define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots" >=20 > static void > tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *de= v) > @@ -370,6 +371,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct > otx2_tim_evdev *dev) >=20 > rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA, > &parse_kvargs_flag, &dev->disable_npa); > + rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS, > + &parse_kvargs_value, &dev->chunk_slots); > } >=20 > void > @@ -423,6 +426,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct > otx2_dev *cmn_dev) > goto mz_free; > } >=20 > + if (!dev->chunk_slots) > + dev->chunk_sz =3D OTX2_TIM_RING_DEF_CHNK_SZ; > + else > + dev->chunk_sz =3D (dev->chunk_slots + 1) * > + OTX2_TIM_CHUNK_ALIGNMENT; Please check the chuck_sz upper bound also.