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DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2839; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: VswNLErIk8jvPi3mMRMnu74dXMzIvyvWYrW6w0qsitoppdlv09f8xmw+GGLQneNXO7PZ4eDlyFiSESgJVzu8J6N0P5h64AUxgKD3cW60mqKW59VzQaHC2IAARvKfwRJUdew/aA5sSeqgpWc46iYwgf7jM5+c/F90bNoNQc73llo708+C3NAIfp4jCdHGz3G+KQL0IgcpynWKjzerjootBLrM6McsYMQoFeBV+Hkyu3wk8VxO/5AKm9qD01arFI9g1dtN8uhMjAQosNFCeB2ZZcuDgotDeFesk3IhOTkoshzpbXf4YVm9ns1/DJcVZZDK6o01WPP9f6ZELGqT4imSXlFAlEjIMmKe6TsQjUqA68txTWzM4j8RqWIqOFmi59eWH/1jV9Kjr3bznZcy3kbQCGNH0tukhx1csh2hBCJHAu4= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: da41d032-76b3-4220-b050-08d7045e9dd0 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jul 2019 11:14:31.4922 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2839 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-09_04:, , signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Phil Yang (Arm Technology China) > Sent: Tuesday, July 9, 2019 2:58 PM > To: Pavan Nikhilesh Bhagavatula ; Honnappa > Nagarahalli ; Jerin Jacob Kollanukkaran > ; dev@dpdk.org > Cc: thomas@monjalon.net; hemant.agrawal@nxp.com; Gavin Hu (Arm > Technology China) ; nd ; > gage.eads@intel.com; nd ; nd > Subject: RE: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare > exchange >=20 > > -----Original Message----- > > From: Pavan Nikhilesh Bhagavatula > > Sent: Friday, July 5, 2019 12:37 PM > > To: Honnappa Nagarahalli ; > > jerinj@marvell.com; Phil Yang (Arm Technology China) > > ; dev@dpdk.org > > Cc: thomas@monjalon.net; hemant.agrawal@nxp.com; Gavin Hu (Arm > > Technology China) ; nd ; > > gage.eads@intel.com; nd > > Subject: RE: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic > > compare exchange > > > > >=20 > >=20 > > >> > > +#ifdef __ARM_FEATURE_ATOMICS > > >> > > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) > > >> \ > > >> > > +static inline rte_int128_t = \ > > >> > > +cas_op_name(rte_int128_t *dst, rte_int128_t old, = \ > > >> > > + rte_int128_t updated) = \ > > >> > > +{ = \ > > >> > > + /* caspX instructions register pair must start from even- > > >numbered > > >> > > + * register at operand 1. > > >> > > + * So, specify registers for local variables here. > > >> > > + */ = \ > > >> > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; > > \ > > >> > > > >> > I understand CASP limitation on register has to be even and odd. > > >> > Is there anyway to remove explicit x0 register allocation and > > >> > choose compiler to decide the register. Some reason with > > >> > optimize(03) gcc makes correctly but not clang. > > >> > > > >> > Hardcoding to specific register makes compiler to not optimize > > >> > the stuff, especially if it is inline function. > > >> > > >> It look like the limitation fixed recently in gcc. > > >> https://patches.linaro.org/patch/147991/ > > >> > > >> Not sure about old gcc and clang. ARM compiler experts may know > > >the exact > > >> status > > >> > > >We could use syntax as follows, an example is in [1] static inline > > >rte_int128_t __rte_casp(rte_int128_t *dst, rte_int128_t old, > > >rte_int128_t updated, int mo) { > > > __asm__ volatile("caspl %0, %H0, %1, %H1, [%2]" > > > : "+r" (old) > > > : "r" (updated), "r" (dst) > > > : "memory"); > > > return old; > > >} > > > > We have used this format for mempool/octeontx2 but clang wasn't too > > happy. > > > > dpdk/drivers/mempool/octeontx2/otx2_mempool_ops.c:151:15: error: > > value size does not match register size specified by the constraint > > and modifier [-Werror,-Wasm-operand-widths] > > [t0] "=3D&r" (t0), [t1] "=3D&r" (t1), [t2] "=3D&r" (t2)= , > > ^ > > dpdk/drivers/mempool/octeontx2/otx2_mempool_ops.c:82:9: note: use > > constraint modifier "w" > > "casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n" > > > > Had to change it to hand coded asm > > > > http://patches.dpdk.org/patch/56110/ >=20 > Hi Jerin, >=20 > The update from the compiler team is 'the LSE CASP fix has not been > backported to older GCC branches'. > So, currently, this seems the only approach works for all versions of GCC= and > Clang. > I think we can add another optimization patch for this once all the compi= lers > were ready. We are on same page. >=20 > Thanks, > Phil > > > > > > > >[1] https://godbolt.org/z/EUJnuG