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DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2534; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: xCPFtfqkqk3IxNE9W/cQIFGOENv1F2prwPncLVyHdJiTWjx0aKGcDhBcIR+KypFZjssawKEDRInnhbj368UnnC1wrL0J30p6ever2KonNttSjcTYCWZsr+tCBDcNVtTPjrE9He7g0o67kkoGVtd4drtTxJ8K0NlBTAD8Y9erNxIKsIPQOLA3Sj6x0Y1OIH5uPZkl0DQ38KlenYBGML3J5zefqVewMTyQvh4yBZjmLOEmIlS7noL2n/xBVtFjSwWvQuh46zDmeC7kQ293FVUylZ4k9SKWK2Z7pOyFH/YXdRfai8XqZvBVEIF0hJVyut8Zj9Spwg4FiHbXQa6Lb7vNhiRmjYzH9OyHvYJRZlzPaCEJn+ilb1uspVr+mMKrPY3bieMwf4oOPikAAqoqqj4kku0pJtj7QCATIOyqMaQKOpU= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: bd90ba47-0229-45a3-2345-08d6ffb769d0 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2019 13:07:33.7530 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2534 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-03_03:, , signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Jerin Jacob Kollanukkaran > Sent: Wednesday, July 3, 2019 5:56 PM > To: Phil Yang ; dev@dpdk.org > Cc: thomas@monjalon.net; hemant.agrawal@nxp.com; > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com; > gage.eads@intel.com > Subject: RE: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare > exchange >=20 > > -----Original Message----- > > From: Phil Yang > > Sent: Friday, June 28, 2019 1:42 PM > > To: dev@dpdk.org > > Cc: thomas@monjalon.net; Jerin Jacob Kollanukkaran > > ; hemant.agrawal@nxp.com; > > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com; > > gage.eads@intel.com > > Subject: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare > > exchange > > > > Add 128-bit atomic compare exchange on aarch64. > > > > Signed-off-by: Phil Yang > > Tested-by: Honnappa Nagarahalli > > Reviewed-by: Honnappa Nagarahalli > > --- > > v3: > > 1. Avoid duplication code with macro. (Jerin Jocob) 2. Make invalid > > memory order to strongest barrier. (Jerin Jocob) 3. Update > > doc/guides/prog_guide/env_abstraction_layer.rst. (Eads Gage) 4. Fix > > 32-bit x86 builds issue. (Eads Gage) 5. Correct documentation issues > > in UT. (Eads Gage) > > > > .../common/include/arch/arm/rte_atomic_64.h | 165 > > +++++++++++++++++++++ > > .../common/include/arch/x86/rte_atomic_64.h | 12 -- > > lib/librte_eal/common/include/generic/rte_atomic.h | 17 ++- > > 3 files changed, 181 insertions(+), 13 deletions(-) > > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > index 97060e4..2080c4d 100644 > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > @@ -1,5 +1,6 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > * Copyright(c) 2015 Cavium, Inc > > + * Copyright(c) 2019 Arm Limited > > */ > > > > #ifndef _RTE_ATOMIC_ARM64_H_ > > @@ -14,6 +15,9 @@ extern "C" { > > #endif > > > > #include "generic/rte_atomic.h" > > +#include > > +#include > > +#include > > > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define > > dmb(opt) asm volatile("dmb " #opt : : : "memory") @@ -40,6 +44,167 @@ > > extern "C" { > > > > #define rte_cio_rmb() dmb(oshld) > > > > +/*------------------------ 128 bit atomic operations > > +-------------------------*/ > > + > > +#define RTE_HAS_ACQ(mo) ((mo) !=3D __ATOMIC_RELAXED && (mo) !=3D > > +__ATOMIC_RELEASE) #define RTE_HAS_RLS(mo) ((mo) =3D=3D > __ATOMIC_RELEASE > > || \ > > + (mo) =3D=3D __ATOMIC_ACQ_REL || \ > > + (mo) =3D=3D __ATOMIC_SEQ_CST) > > + > > +#define RTE_MO_LOAD(mo) (RTE_HAS_ACQ((mo)) \ > > + ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED) #define > > RTE_MO_STORE(mo) > > +(RTE_HAS_RLS((mo)) \ > > + ? __ATOMIC_RELEASE : __ATOMIC_RELAXED) > > + > > +#ifdef __ARM_FEATURE_ATOMICS > > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) = \ > > +static inline rte_int128_t = \ > > +cas_op_name(rte_int128_t *dst, rte_int128_t old, = \ > > + rte_int128_t updated) = \ > > +{ = \ > > + /* caspX instructions register pair must start from even-numbered > > + * register at operand 1. > > + * So, specify registers for local variables here. > > + */ = \ > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; = \ >=20 > I understand CASP limitation on register has to be even and odd. > Is there anyway to remove explicit x0 register allocation and choose comp= iler to > decide the register. Some reason with optimize(03) gcc makes correctly bu= t not > clang. >=20 > Hardcoding to specific register makes compiler to not optimize the stuff, > especially if it is inline function. It look like the limitation fixed recently in gcc. https://patches.linaro.org/patch/147991/ Not sure about old gcc and clang. ARM compiler experts may know the exact s= tatus =20