From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA887A0471 for ; Fri, 19 Jul 2019 08:25:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 600332BE5; Fri, 19 Jul 2019 08:25:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 16264231E for ; Fri, 19 Jul 2019 08:25:03 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x6J6OxEH025546; Thu, 18 Jul 2019 23:24:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=nhkS61cZtQQyoN3eJ3tEEmpkefS9rWf13SMvU1g/2V4=; b=NWzFJEO9bOJAbd4uVRbxw3WkXioFVkYJrAed8ZPgSOgnn6uKgLjI6UJybwNCBW/9lsDE QAj+f7tX8C81FcLXaa5XW/DpfQS6HBWdXmuhnj9nMI03yYOL77uPxJTX/tuIKHUzzkhy qBXwTED+v2Yv1H4YXhfdJXerWadiSZL7rW4XOjhvoVAdfg0nSB8BMmmO7cwcLnDsDOAJ BBRUXIt9q1NeP3AeT800JNmFPTbFNe72Z3r9/y+yTm1WF8tWwzr7qQBOyrjj3LyGZrkZ 1OZcSBqIHGxqkqfPG+Lz42+EtDmhfOO0/eNfXOecHHnLOzLdjfL9nPj5izGLKHb1yMIG ag== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 2ts07vrbpu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 18 Jul 2019 23:24:59 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 18 Jul 2019 23:24:55 -0700 Received: from NAM01-BY2-obe.outbound.protection.outlook.com (104.47.34.58) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Thu, 18 Jul 2019 23:24:55 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QUNgE968Msb1OiQi+7qLxxcKSA2xd1TIB3/Ba+w0JxYImC24SCbEBCrXUn5rd/EZepTUugfDHmY2Gw9mWMZ4uI9HBZUsACA6xwtGYkutJS/hSwvqmr41nAwFAfDuwiqNgqMWv297weh4Etwy1QcrasKUFNr9GhwUQZmssvC3ve+OVjrZ755lcl1OtZFv9K+AuGr1LvwzgNUFkoXgZLfKysczDbLeVUCo2FbSmVrgQaW8L0waRuiAu0iJpxnnAsfVem7P71huiAUGQqJIemzJK+kFqioNfzN/vgBYMJgW7iigPPHCVEyQPrTsb7vfaFrhqVJnlC4CD4qXSfv4ev2BPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nhkS61cZtQQyoN3eJ3tEEmpkefS9rWf13SMvU1g/2V4=; b=XAwUMubNVEzLl0EOyOLWWY7l4lpUVXj5E0HmrRnOl2Kvrz5p74969/VojdLK4cTzuJFDXtI/PfRCf8CrjM4sz9PA9lxP2Eg9tnxIaZIpbZ5ZEi9AYHbtfwEDPEC6WgTjN0cq6CknR1F7SYIrhiYM/B1mpSJ4njKewmioh58fu3qJoPJ3GPK+UhsmMg06s8wYI0SUZyMTGsi4ul8g2j56gHTDArK0CYt6V9YZBpGkTiXqkADe4MAL1HIx8qafHZCuc02/sknAqRStmgGAlt9dv9JhoBdHtiu2uUuys8Ybk7WkTJFLWFW8xRFJTZPsYo3Pm5EmTCRE/DbRVOIZJZAEKg== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=marvell.com;dmarc=pass action=none header.from=marvell.com;dkim=pass header.d=marvell.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nhkS61cZtQQyoN3eJ3tEEmpkefS9rWf13SMvU1g/2V4=; b=FItEhkT8Mf0WThR6cY0u6ymyJlBbxqwMwXtfyyLaShaBlvFg74xmaIUhEGRkTOdkAZ898MUGk+Qvde1FK0upHRB7rJhZHE5Q/vAUT72k2z1RfoaHtFPX5OBNgCmPUNNiFGL6tpLevXWUaBCA5+nredqiMK4CEt6aMtFVhSnH3TQ= Received: from BYAPR18MB2424.namprd18.prod.outlook.com (20.179.91.149) by BYAPR18MB2728.namprd18.prod.outlook.com (20.179.56.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2094.11; Fri, 19 Jul 2019 06:24:54 +0000 Received: from BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862]) by BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862%4]) with mapi id 15.20.2073.012; Fri, 19 Jul 2019 06:24:54 +0000 From: Jerin Jacob Kollanukkaran To: Phil Yang , "dev@dpdk.org" CC: "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , "Honnappa.Nagarahalli@arm.com" , "gavin.hu@arm.com" , "nd@arm.com" , "gage.eads@intel.com" Thread-Topic: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare exchange Thread-Index: AQHVLYk2hpq4OasZX0+HEFxbT7xNTqbRjN6A Date: Fri, 19 Jul 2019 06:24:54 +0000 Message-ID: References: <1561257671-10316-1-git-send-email-phil.yang@arm.com> <1561709503-11665-1-git-send-email-phil.yang@arm.com> In-Reply-To: <1561709503-11665-1-git-send-email-phil.yang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [14.140.231.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 91614c22-d734-40eb-61bd-08d70c11d033 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:BYAPR18MB2728; x-ms-traffictypediagnostic: BYAPR18MB2728: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 01039C93E4 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(366004)(346002)(136003)(376002)(39860400002)(13464003)(199004)(189003)(71200400001)(71190400001)(54906003)(2906002)(110136005)(68736007)(316002)(2501003)(305945005)(86362001)(25786009)(14454004)(53546011)(55236004)(486006)(66476007)(66946007)(52536014)(76116006)(8676002)(7696005)(76176011)(102836004)(5660300002)(64756008)(55016002)(9686003)(66446008)(256004)(6506007)(66556008)(53936002)(229853002)(6436002)(66066001)(99286004)(186003)(6246003)(4326008)(26005)(7736002)(11346002)(446003)(476003)(74316002)(8936002)(3846002)(81166006)(478600001)(33656002)(81156014)(6116002); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2728; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 7F2syg4dTk46chlPVaQbogP4EINyqH/+ayfMuwuJo9jWzl6VnAc7ZmZMiYnZhiwAeQ+YWs2Qa9cakDg6x66bvxg5Q7BMQRD1iT2G73bXAnETUU8d+4CpKx54MgfNNaEnWLhgPVvsXIpxEoSAFRvjEde/rFeMtqe/syUdXuz/UNkIidycQ3TRDosM3PwWt4x3dmKmKR6LjPnVzQEexTpxMos6docp7JNTIOC/ANrNWP5M7Eo0L+GE7oOlr3G6S/v0IL2KLoNMsm9PoF1ECpsb+l00X+rxAVxGhqwXZhwpUKFVzpWgn665LRJcX0+a10fbqPe9He5G7TGahKMoPHvqRItFa4ydo9no0tjRYmwAAkjh6PZdhM/vibkLxd9nn1gqfSIVItqxjUfJ5INhB3noiO/wGOjfwgiUgLVhxyNlNM0= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 91614c22-d734-40eb-61bd-08d70c11d033 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Jul 2019 06:24:54.1461 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2728 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-07-19_04:2019-07-19,2019-07-19 signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Phil Yang > Sent: Friday, June 28, 2019 1:42 PM > To: dev@dpdk.org > Cc: thomas@monjalon.net; Jerin Jacob Kollanukkaran ; > hemant.agrawal@nxp.com; Honnappa.Nagarahalli@arm.com; > gavin.hu@arm.com; nd@arm.com; gage.eads@intel.com > Subject: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare > exchange >=20 > External Email >=20 > ---------------------------------------------------------------------- > Add 128-bit atomic compare exchange on aarch64. >=20 > Signed-off-by: Phil Yang > Tested-by: Honnappa Nagarahalli > Reviewed-by: Honnappa Nagarahalli > --- > +#define RTE_HAS_ACQ(mo) ((mo) !=3D __ATOMIC_RELAXED && (mo) !=3D > +__ATOMIC_RELEASE) #define RTE_HAS_RLS(mo) ((mo) =3D=3D > __ATOMIC_RELEASE || \ > + (mo) =3D=3D __ATOMIC_ACQ_REL || \ > + (mo) =3D=3D __ATOMIC_SEQ_CST) > + > +#define RTE_MO_LOAD(mo) (RTE_HAS_ACQ((mo)) \ > + ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED) #define > RTE_MO_STORE(mo) > +(RTE_HAS_RLS((mo)) \ > + ? __ATOMIC_RELEASE : __ATOMIC_RELAXED) > + The one starts with RTE_ are public symbols, If it is generic enough, Move to common layer so that every architecturse can use. If you think, otherwise make it internal=20 > +#ifdef __ARM_FEATURE_ATOMICS This define is added in gcc 9.1 and I believe for clang it is not supported= yet. So old gcc and clang this will be undefined. I think, With meson + native build, we can find the presence of=20 ATOMIC support by running a.out. Not sure about make and cross build case. I don't want block this feature because of this, IMO, We can add this code with existing __ARM_FEATURE_ATOMICS scheme and later find a method to enhance it. But please check how to fix it. > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) = \ > +static inline rte_int128_t = \ > +cas_op_name(rte_int128_t *dst, rte_int128_t old, = \ > + rte_int128_t updated) \ > +{ = \ > + /* caspX instructions register pair must start from even-numbered > + * register at operand 1. > + * So, specify registers for local variables here. > + */ = \ > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; = \ Since direct x0 register used in the code and cas_op_name() and rte_atomic128_cmp_exchange() is inline function, Based on parent function load, we may corrupt x0 register aka Break arm64 ABI. Not sure clobber list will help here or not? Making it as no_inline will help but not sure about the performance impact. May be you can check with compiler team.=20 We burned our hands with this scheme, see 5b40ec6b966260e0ff66a8a2c689664f75d6a0e6 ("mempool/octeontx2: fix possible = arm64 ABI break") Probably we can choose a scheme for rc2 and adjust as when we have complete= clarity. > + register uint64_t x1 __asm("x1") =3D (uint64_t)old.val[1]; = \ > + register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; = \ > + register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; = \ > + asm volatile( = \ > + op_string " %[old0], %[old1], %[upd0], %[upd1], > [%[dst]]" \ > + : [old0] "+r" (x0), \ > + [old1] "+r" (x1) \ > + : [upd0] "r" (x2), \ > + [upd1] "r" (x3), \ > + [dst] "r" (dst) \ > + : "memory"); \ Should n't we add x0,x1, x2, x3 in clobber list? > static inline int __rte_experimental > rte_atomic128_cmp_exchange(rte_int128_t *dst, > rte_int128_t *exp, > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h > b/lib/librte_eal/common/include/generic/rte_atomic.h > index 9958543..2355e50 100644 > --- a/lib/librte_eal/common/include/generic/rte_atomic.h > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h > @@ -1081,6 +1081,20 @@ static inline void > rte_atomic64_clear(rte_atomic64_t *v) >=20 > /*------------------------ 128 bit atomic operations -------------------= ------*/ >=20 > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) There is nothing specific to x86 and arm64 here, Can we remove this #ifdef = ? > +/** > + * 128-bit integer structure. > + */ > +RTE_STD_C11 > +typedef struct { > + RTE_STD_C11 > + union { > + uint64_t val[2]; > + __extension__ __int128 int128; > + }; > +} __rte_aligned(16) rte_int128_t; > +#endif > + > #ifdef __DOXYGEN__