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SFP:1101; SCL:1; SRVR:BYAPR18MB2520; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 0MX1DARHo3TeK+S/4mJOwpqga+8VecSSnnxNBIsetPypby19G1I7ab/76n+FAqwa9g4jxHAjr8GagPPjX421jFic9Arvt1CsBRBFNUSLfhpCtH6vExsC7o54cYQ/+Dvl1xNnCzgMWlvZQYGJArL+fZTnnkZowEeTBc8/elrixFxusaox94yx55/n1yfi2lEozvN+yrph/EK4TH8dRULoKTyao0bHCmYGYp6yJdN2xnY6jH0l8WZChMxWLEeWo1UF2C7Cw3J+uEenPBDOro+P2NN4nYJJO1HM6css2Keo6QbTtpAs+5eAjGBRu1WLZ421Jxqc9aS9tUJ3bRYGGT0p2nXjVbEuMcYiWXVeigxoG2UOixkTX9bn+qMSc6/5wBbQgU4Bma1MDkR1CLPms5jBU2oHKtBUwB9PpveFWgeQluQ= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: bb3348b9-bc69-4ca5-aee4-08d71735e943 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Aug 2019 10:41:00.8138 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2520 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-02_05:2019-07-31,2019-08-02 signatures=0 Subject: Re: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add irq support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Zhang, Tianfei > Sent: Friday, August 2, 2019 3:36 PM > To: Jerin Jacob Kollanukkaran ; Xu, Rosen > ; dev@dpdk.org > Cc: Yigit, Ferruh ; Pei, Andy ; > Lomartire, David ; Zhang, Qi Z > ; Ye, Xiaolong > Subject: [EXT] RE: [dpdk-dev] [PATCH v2 02/12] raw/ifpga_rawdev/base: add > irq support >=20 > > > + > > > +/* only support msix for now*/ > > > +static int vfio_msix_enable_block(s32 vfio_dev_fd, unsigned int > vec_start, > > > + unsigned int count, s32 *fds) > > > > Isn't better to use generic EAL function for the same? >=20 > In our PAC N3000 Card, we have 6 PCIe MSI-X vectors, for example: > 0~3 for AFU > 4 for Port > 6 for FME >=20 > FME (FPGA Management Engine ) will manage all resources in FPGA, like > partition reconfiguration, Power manager, thermal, Error reporting. > Port is a bridge between FME and AFU. > AFU is the accelerator unit which for customers logic. >=20 > So, we reserve some MSI-X vectors for end-user/customers to use the AFU, > and end-user/customers can use the AFU for networking acceleration or > other acceleration. >=20 > The DPDK existing API like rte_intr_enable()->vfio_enable_msix() will bin= d all > of the vectors at the same time and those vectors will register into one > evenfd and one interrupt handler function. > That cannot satisfy our design. we hope that, each MSI-X vector bind into > VFIO and register the interrupt handler function separately. Because the > reserve vectors like > 0~3 vectors for AFU, we don't know what exact usage for the end- > user/customers in AFU logic, so it had better let them bind VFIO and regi= ster > interrupt handler themselves. >=20 > One suggestion is we expand the vfio_enable_msix() function, let the call= er > to specify the start vector and the numbers of vectors to bind the VFIO. Yes, Probably have two variants, vfio_enable_msix() alias to count of 1 > static int > vfio_enable_msix(const struct rte_intr_handle *intr_handle, int start, in= t > count) { > ... > irq_set->count =3D count; > irq_set->start =3D start; > ... > return 0; > } >=20