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SFP:1101; SCL:1; SRVR:BYAPR18MB2760; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 4O33jD9W1bSpXT3v7kJw7XkKHwkHDFu+nz82uOgVBoInln9iZ75ZSz7pPVCjqOKq/pEgglL0wU0VflwR3e3IL9WbtLsHxyMkwL8HiICxhqRjMz/BS4LEMTbGpsuU0v5oRVal38D+jPtoISpV1lphhOTuJKJ8S6e48aAck6vm4cHYU2QRaF0mpnGJrE6BLRqJ6tAp0nQMick1uMnsa/L3s5BPXfJ3T0LRmOzlx1gkiCrsHbMFZoiXopcUtbkCAjJJMcdlsIBhDlmhmrrZGxjMMH6osRZC8NCMBAz9/9NEXfuYjK1kzgMtnj0RNDa5cOzn4OHliw+G21pfhAUNBRMoV+lq5tZ7Y5rykKj57sIDLvsUDBAl7prb1ChdRIJRPDbbVBuUORHHBDkTN2ImbQNE/gyvsM9i62UJ4rXxOE9FN/c= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 5b53e6a6-8fa3-47c3-0875-08d70e8e2abe X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jul 2019 10:20:05.8927 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2760 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-07-22_08:2019-07-22,2019-07-22 signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Phil Yang > Sent: Monday, July 22, 2019 2:14 PM > To: dev@dpdk.org > Cc: thomas@monjalon.net; Jerin Jacob Kollanukkaran ; > gage.eads@intel.com; hemant.agrawal@nxp.com; > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com > Subject: [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare excha= nge > Add 128-bit atomic compare exchange on aarch64. >=20 > Suggested-by: Jerin Jacob > Signed-off-by: Phil Yang > Tested-by: Honnappa Nagarahalli > Reviewed-by: Honnappa Nagarahalli > + > +# > +# Compile ARM LSE ATOMIC instructions statically # There is NO value for the keyword "statically" here. Right? > +CONFIG_RTE_ARM_FEATURE_ATOMICS=3Dn > diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc > b/config/defconfig_arm64-thunderx2-linuxapp-gcc > index cc5c64b..17b6dec 100644 > --- a/config/defconfig_arm64-thunderx2-linuxapp-gcc > +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc > @@ -6,6 +6,7 @@ >=20 > CONFIG_RTE_MACHINE=3D"thunderx2" >=20 > +CONFIG_RTE_ARM_FEATURE_ATOMICS=3Dy Add for octeontx2 as well. > CONFIG_RTE_CACHE_LINE_SIZE=3D64 > CONFIG_RTE_MAX_NUMA_NODES=3D2 > CONFIG_RTE_MAX_LCORE=3D256 > +rte_atomic128_cmp_exchange(rte_int128_t *dst, > + rte_int128_t *exp, > + const rte_int128_t *src, > + unsigned int weak, > + int success, > + int failure) > +{ > + /* Always do strong CAS */ > + RTE_SET_USED(weak); > + /* Ignore memory ordering for failure, memory order for > + * success must be stronger or equal > + */ > + RTE_SET_USED(failure); > + /* Find invalid memory order */ > + RTE_ASSERT(success =3D=3D __ATOMIC_RELAXED > + || success =3D=3D __ATOMIC_ACQUIRE > + || success =3D=3D __ATOMIC_RELEASE > + || success =3D=3D __ATOMIC_ACQ_REL > + || success =3D=3D __ATOMIC_SEQ_CST); > + > +#ifdef __ARM_FEATURE_ATOMICS Shouldn't it be #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEAT= URE_ATOMICS) ?