DPDK patches and discussions
 help / color / mirror / Atom feed
From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
To: Phil Yang <phil.yang@arm.com>,
	"thomas@monjalon.net" <thomas@monjalon.net>,
	"gage.eads@intel.com" <gage.eads@intel.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: "hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
	"Honnappa.Nagarahalli@arm.com" <Honnappa.Nagarahalli@arm.com>,
	"gavin.hu@arm.com" <gavin.hu@arm.com>, "nd@arm.com" <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare exchange
Date: Wed, 14 Aug 2019 08:45:59 +0000	[thread overview]
Message-ID: <BYAPR18MB24248BE5D5CA545E9D92FA75C8AD0@BYAPR18MB2424.namprd18.prod.outlook.com> (raw)

> -----Original Message-----
> From: Phil Yang <phil.yang@arm.com>
> Sent: Wednesday, August 14, 2019 1:58 PM
> To: thomas@monjalon.net; Jerin Jacob Kollanukkaran <jerinj@marvell.com>;
> gage.eads@intel.com; dev@dpdk.org
> Cc: hemant.agrawal@nxp.com; Honnappa.Nagarahalli@arm.com;
> gavin.hu@arm.com; nd@arm.com
> Subject: [EXT] [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare
> exchange
> +#define __HAS_ACQ(mo) ((mo) != __ATOMIC_RELAXED && (mo) !=
> +__ATOMIC_RELEASE) #define __HAS_RLS(mo) ((mo) ==
> __ATOMIC_RELEASE || (mo) == __ATOMIC_ACQ_REL || \
> +					  (mo) == __ATOMIC_SEQ_CST)
> +
> +#define __MO_LOAD(mo)  (__HAS_ACQ((mo)) ? __ATOMIC_ACQUIRE :
> +__ATOMIC_RELAXED) #define __MO_STORE(mo) (__HAS_RLS((mo)) ?
> +__ATOMIC_RELEASE : __ATOMIC_RELAXED)
> +
> +#if defined(__ARM_FEATURE_ATOMICS) ||
> defined(RTE_ARM_FEATURE_ATOMICS)
> +#define __ATOMIC128_CAS_OP(cas_op_name, op_string)                          \
> +static __rte_noinline rte_int128_t                                          \


Could you check the cost of making it as __rte_noinline?
If it is costly, How about having two versions, one with __rte_noinline
to make compliance with arm64 procedure call standard for
old gcc and clang.
Other one without explicit register hardcoding + inline for latest
gcc


> +cas_op_name(rte_int128_t *dst, rte_int128_t old,                            \
> +		rte_int128_t updated)                                       \
> +{                                                                           \
> +	/* caspX instructions register pair must start from even-numbered
> +	 * register at operand 1.
> +	 * So, specify registers for local variables here.
> +	 */                                                                 \
> +	register uint64_t x0 __asm("x0") = (uint64_t)old.val[0];            \
> +	register uint64_t x1 __asm("x1") = (uint64_t)old.val[1];            \
> +	register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0];        \
> +	register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1];        \
> +	asm volatile(                                                       \
> +		op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]"   \
> +		: [old0] "+r" (x0),                                         \
> +		[old1] "+r" (x1)                                            \
> +		: [upd0] "r" (x2),                                          \
> +		[upd1] "r" (x3),                                            \
> +		[dst] "r" (dst)                                             \
> +		: "memory");                                                \
> +	old.val[0] = x0;                                                    \
> +	old.val[1] = x1;                                                    \
> +	return old;                                                         \
> +}
> +

             reply	other threads:[~2019-08-14  8:46 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-14  8:45 Jerin Jacob Kollanukkaran [this message]
2019-08-14 10:24 ` Phil Yang (Arm Technology China)
2019-08-14 12:40   ` Jerin Jacob Kollanukkaran
  -- strict thread matches above, loose matches on Subject: below --
2019-07-23  7:05 [dpdk-dev] [PATCH v8 " jerinj
2019-08-14  8:27 ` [dpdk-dev] [PATCH v9 " Phil Yang
2019-10-14 15:43   ` David Marchand
2019-10-15 11:32     ` Phil Yang (Arm Technology China)
2019-10-15 12:16       ` David Marchand
2019-10-16  9:04         ` Phil Yang (Arm Technology China)
2019-10-17 12:45           ` David Marchand

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=BYAPR18MB24248BE5D5CA545E9D92FA75C8AD0@BYAPR18MB2424.namprd18.prod.outlook.com \
    --to=jerinj@marvell.com \
    --cc=Honnappa.Nagarahalli@arm.com \
    --cc=dev@dpdk.org \
    --cc=gage.eads@intel.com \
    --cc=gavin.hu@arm.com \
    --cc=hemant.agrawal@nxp.com \
    --cc=nd@arm.com \
    --cc=phil.yang@arm.com \
    --cc=thomas@monjalon.net \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).