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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 106be4fa-1e31-4df6-7310-08d72093d4bb X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Aug 2019 08:45:59.6430 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MYTpSARyel99WzXf7LbAxJbIrorObhsMZGQNtf9OPxuLalh8IXwpttzTQPqsT2H9LTe7t2J5nKBjLgMLinMIoA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB3064 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-14_03:2019-08-14,2019-08-14 signatures=0 Subject: Re: [dpdk-dev] [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Phil Yang > Sent: Wednesday, August 14, 2019 1:58 PM > To: thomas@monjalon.net; Jerin Jacob Kollanukkaran ; > gage.eads@intel.com; dev@dpdk.org > Cc: hemant.agrawal@nxp.com; Honnappa.Nagarahalli@arm.com; > gavin.hu@arm.com; nd@arm.com > Subject: [EXT] [PATCH v9 1/3] eal/arm64: add 128-bit atomic compare > exchange > +#define __HAS_ACQ(mo) ((mo) !=3D __ATOMIC_RELAXED && (mo) !=3D > +__ATOMIC_RELEASE) #define __HAS_RLS(mo) ((mo) =3D=3D > __ATOMIC_RELEASE || (mo) =3D=3D __ATOMIC_ACQ_REL || \ > + (mo) =3D=3D __ATOMIC_SEQ_CST) > + > +#define __MO_LOAD(mo) (__HAS_ACQ((mo)) ? __ATOMIC_ACQUIRE : > +__ATOMIC_RELAXED) #define __MO_STORE(mo) (__HAS_RLS((mo)) ? > +__ATOMIC_RELEASE : __ATOMIC_RELAXED) > + > +#if defined(__ARM_FEATURE_ATOMICS) || > defined(RTE_ARM_FEATURE_ATOMICS) > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) = \ > +static __rte_noinline rte_int128_t = \ Could you check the cost of making it as __rte_noinline? If it is costly, How about having two versions, one with __rte_noinline to make compliance with arm64 procedure call standard for old gcc and clang. Other one without explicit register hardcoding + inline for latest gcc > +cas_op_name(rte_int128_t *dst, rte_int128_t old, = \ > + rte_int128_t updated) \ > +{ = \ > + /* caspX instructions register pair must start from even-numbered > + * register at operand 1. > + * So, specify registers for local variables here. > + */ \ > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; \ > + register uint64_t x1 __asm("x1") =3D (uint64_t)old.val[1]; \ > + register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; \ > + register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; \ > + asm volatile( \ > + op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]" \ > + : [old0] "+r" (x0), \ > + [old1] "+r" (x1) \ > + : [upd0] "r" (x2), \ > + [upd1] "r" (x3), \ > + [dst] "r" (dst) \ > + : "memory"); \ > + old.val[0] =3D x0; \ > + old.val[1] =3D x1; \ > + return old; \ > +} > +