From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85950A10DA for ; Fri, 2 Aug 2019 06:15:00 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6C39C1C212; Fri, 2 Aug 2019 06:14:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 0F0BF1C20C for ; Fri, 2 Aug 2019 06:14:57 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x724AIGg004061; Thu, 1 Aug 2019 21:14:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=qaiqRNNqX3VqlgJzy8L32omSfRK7ou1SgIXy15GZ8VQ=; b=lNWvrSxnw4FfiqK0Mx31w+UPYsmAru2yGbBCB1wQyBf47QuFZPuan+qpG+iB+tZ1pYKW OkBYf/y+jbIUIgdKYvLXVThASSNfVrnYn1tCFTYhFG4Wbs+Kl/FiVQDFvIuwnh1CSz44 90AhqRDM03wi+j2w1vtGioQAQS1WWkRtWqj6zUYExaeCMn+kmHTnN8O1vftJK9aaVzns f0n/N/3FK2xWu3ll+1t1i3eSczNC2aMIaY/pK3nhvEsnm6tz9nj6bmmk1J5m4bd4O1ac ldL+eZZ/BrnX90N00hPOtdJs5War5mGTLRafYi1feQWcOj0iTicaN5E0jCyJPqMSTQ2x +A== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2u42fsjrk8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 01 Aug 2019 21:14:56 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 1 Aug 2019 21:14:55 -0700 Received: from NAM04-BN3-obe.outbound.protection.outlook.com (104.47.46.54) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Thu, 1 Aug 2019 21:14:54 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Grp8DpsVl+plzKgVGupEB0BvSpGcITTMXaJz+ercI09kbPgKiV8h29q9fo1qa+PaPUUlLssFVZbgCy8eBCySaTjiwURQ56cKG5LIJGw7GYP+WR61oYeDLU1oKoY9chriproZ7PuhWe1zgSu3aUU1ddGwKDS3Ry7u21iI76ePh2bFvyWAP6UC9ygfc76Gf39R2sN1kuwAhD+T0a14Oy5/EMIgAoq0I/henexGdyDuH4qK2JW5qlnEYypQPannGaD9iCCMDxZguTXCMd6jb2JNVYsMNUb4f+FPu8mvfZ63L9bKhDaDKImxUjpvN0ghcBvQHcJqPbRdlwtz+Luy/OA24g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qaiqRNNqX3VqlgJzy8L32omSfRK7ou1SgIXy15GZ8VQ=; b=Z67Rv0q30FxnH5lf+bmIvaYTcI3wjND3QGzve/86/7OuSOH50AVp4uu8HHfDFaZMGONU/ByfCTLASHf18dsVneSMJFEhEZwhsUBHMfSFG3O0wR3IGATsXDbYPJBzkTQ4afy2L0Jg8I1s16htDSmSPE+djd916ZQ6DldEjB2XcvTRD+RAsB+RwpqrID1Yak21LEw5IB9fDALMdtAjHemfstjt0L8XVilMid0CqGnQbz7YnbCZJn/1xmRuy00SMwdN2+WP0KzPEDNLWnlRvPl0k5YGIu0SbJx/Tg8aP1r81+8CBR96riJ8bhI9oKH2OlOcQ4Z9kP3/oRlnCaNLpAbjJQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=marvell.com;dmarc=pass action=none header.from=marvell.com;dkim=pass header.d=marvell.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qaiqRNNqX3VqlgJzy8L32omSfRK7ou1SgIXy15GZ8VQ=; b=vxWuwCr7cBBf0lumBbTIh+VN+tQmlovh0BNChJP4J3qrfjo+rF0zVu7seunVI7SZaWSubng0MbJ6lXwxM7gnHiqUr74+HksJpN4wQgytM36brQ1naR/bl2ZQwcuNJUw5vMc2KE0cm60CbwMwOJe6cm3DrFXgen/pQ2q0otzPQi8= Received: from BYAPR18MB2424.namprd18.prod.outlook.com (20.179.91.149) by BYAPR18MB3031.namprd18.prod.outlook.com (20.179.94.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2115.13; Fri, 2 Aug 2019 04:14:53 +0000 Received: from BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862]) by BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2d42:12b6:aa2e:2862%4]) with mapi id 15.20.2115.005; Fri, 2 Aug 2019 04:14:53 +0000 From: Jerin Jacob Kollanukkaran To: Rosen Xu , "dev@dpdk.org" CC: "ferruh.yigit@intel.com" , "tianfei.zhang@intel.com" , "andy.pei@intel.com" , "david.lomartire@intel.com" , "qi.z.zhang@intel.com" , "xiaolong.ye@intel.com" Thread-Topic: [dpdk-dev] [PATCH v2 00/12] Add PCIe AER disable and IRQ support for ipn3ke Thread-Index: AQHVSNAlRtWpLrIKnEqX/YRzyoZfRqbnO6kw Date: Fri, 2 Aug 2019 04:14:53 +0000 Message-ID: References: <1564556752-19257-2-git-send-email-rosen.xu@intel.com> <1564708727-164887-1-git-send-email-rosen.xu@intel.com> In-Reply-To: <1564708727-164887-1-git-send-email-rosen.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [14.140.231.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bab0784a-327d-4a80-533e-08d716fff840 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600148)(711020)(4605104)(1401327)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:BYAPR18MB3031; x-ms-traffictypediagnostic: BYAPR18MB3031: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5236; x-forefront-prvs: 011787B9DD x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(366004)(136003)(346002)(376002)(39860400002)(396003)(199004)(189003)(13464003)(6116002)(316002)(9686003)(66556008)(64756008)(66446008)(66066001)(186003)(71190400001)(6436002)(305945005)(4326008)(99286004)(86362001)(76116006)(7696005)(5660300002)(110136005)(81156014)(55016002)(81166006)(256004)(6246003)(53936002)(66476007)(3846002)(66946007)(54906003)(102836004)(52536014)(76176011)(229853002)(6506007)(53546011)(11346002)(68736007)(55236004)(74316002)(478600001)(486006)(8936002)(71200400001)(2501003)(476003)(7736002)(14454004)(33656002)(25786009)(2906002)(26005)(446003)(32563001); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB3031; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 4pQrmBjpr8pDBXIfLC7gTWGYGPTrBnnaQILuBvpjsj49Vqd08nvWPfmXGJv7KpC2poaqnCHZwJZl/YocJ/z4SaBDA8H2tvuDqhwjv5DV5W/uhbui6JiCu+wT+P8GIETSw5IlDOWXLCJE7LeWjKcIUjSMPHJy3zkH9Li7f3d4riUvMLKY8qtd5dDDGy0vcuLfc4UYvmn3fWW/1H/ryjXyFSUU+C9XoVbU4QSs67z3QuDSTU5qMyZNWNXZrkawnivfZ9em5ljEeY7trqPlgG7OY2Tt9TEqW+QqTbPYOVNkA10h/kPs4vA7/lkPN7aYYkRIQtw89UqWyRrXCbVy6oTqDM0DquuH1w/NIyORlP/1PopKnpxi4QUUYMxnblntVtaDe9Hwblol3XuoOzxG3vWaaDKkb1ufbbIHk5LNBTrhmYI= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: bab0784a-327d-4a80-533e-08d716fff840 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Aug 2019 04:14:53.2132 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jerinj@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB3031 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-02_02:2019-07-31,2019-08-02 signatures=0 Subject: Re: [dpdk-dev] [PATCH v2 00/12] Add PCIe AER disable and IRQ support for ipn3ke X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Rosen Xu > Sent: Friday, August 2, 2019 6:49 AM > To: dev@dpdk.org > Cc: ferruh.yigit@intel.com; tianfei.zhang@intel.com; rosen.xu@intel.com; > andy.pei@intel.com; david.lomartire@intel.com; qi.z.zhang@intel.com; > xiaolong.ye@intel.com > Subject: [dpdk-dev] [PATCH v2 00/12] Add PCIe AER disable and IRQ support > for ipn3ke >=20 > This patch set adds PCIe AER disable and IRQ support for ipn3ke. > Disable PCIe AER is very useful when FPGA reload. IRQ is used very widely= in > interrupt process. Shouldn't it better to have common code in PCI subsystem to disable PCIe AE= R etc, So that other drivers can be used in future. >=20 > For ipn3ke is connect to CPU with PCIe switch, driver needs to scan all P= CIe Do we need a special PCIe switch for this? Or Generic PCIe switch would do? > devices of ipn3ke, it also can get all i40e of card, so ipn3ke driver doe= sn't > need to take some configuration of i40e. Is communication between i40e and ipn3ke proprietary scheme? Who is the PCIe bus master here? Ipn3ke or i40e?